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annotate packages/devs/eth/via/rhine/current/src/if_rhine.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // dev/if_rhine.c
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4 //
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5 // Ethernet device driver for VIA RHINE compatible controllers
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //####BSDCOPYRIGHTBEGIN####
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41 //
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42 // -------------------------------------------
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43 //
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44 // Portions of this software may have been derived from OpenBSD or other sources,
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45 // and are covered by the appropriate copyright disclaimers included herein.
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46 //
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47 // -------------------------------------------
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48 //
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49 //####BSDCOPYRIGHTEND####
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50 //==========================================================================
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51 //#####DESCRIPTIONBEGIN####
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52 //
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53 // Author(s): jskov, based on pcnet driver
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54 // Contributors: gthomas, jskov, hmt
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55 // Date: 2001-05-30
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56 // Purpose:
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57 // Description: hardware driver for VIA Rhine ethernet
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58 //
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59 // FIXME: Make endian safe
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60 // Make use of virtual addressing for memory shared over PCI
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61 // (see _ADDR_MASK).
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62 // Link failure not detected for some reason.
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63 //
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64 //####DESCRIPTIONEND####
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65 //
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66 //==========================================================================
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67
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68 #include <pkgconf/system.h>
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69 #include <pkgconf/devs_eth_via_rhine.h>
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70 #include <cyg/infra/cyg_type.h>
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71 #include <cyg/hal/hal_arch.h>
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72 #include <cyg/hal/hal_intr.h>
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73 #include <cyg/infra/cyg_ass.h>
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74 #include <cyg/infra/diag.h>
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75 #include <cyg/hal/drv_api.h>
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76 #include <cyg/io/eth/netdev.h>
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77 #include <cyg/io/eth/eth_drv.h>
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78 #ifdef CYGPKG_NET
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79 #include <pkgconf/net.h>
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80 #include <cyg/kernel/kapi.h>
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81 #include <net/if.h> /* Needed for struct ifnet */
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82 #include <pkgconf/io_eth_drivers.h>
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83 #endif
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84 #include CYGHWR_MEMORY_LAYOUT_H
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85
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86 #ifdef CYGPKG_IO_PCI
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87 #include <cyg/io/pci.h>
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88 #else
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89 #error "Need PCI package here"
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90 #endif
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91
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92 #define _BUF_SIZE 1544
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93
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94 #ifdef CYGPKG_INFRA_DEBUG
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95 // Then we log, OOI, the number of times we get a bad packet number
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96 // from the tx done fifo.
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97 int rhine_txfifo_good = 0;
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98 int rhine_txfifo_bad = 0;
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99 #endif
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100
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101 #include "via_rhine.h"
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102
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103 #define __WANT_DEVS
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104 #include CYGDAT_DEVS_ETH_VIA_RHINE_INL
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105 #undef __WANT_DEVS
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106
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107 static void rhine_poll(struct eth_drv_sc *sc);
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108
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109 // This ISR is called when the ethernet interrupt occurs
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110 static cyg_uint32
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111 rhine_isr(cyg_vector_t vector, cyg_addrword_t data)
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112 {
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113 struct rhine_priv_data *cpd = (struct rhine_priv_data *)data;
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114
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115 DEBUG_FUNCTION();
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116
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117 INCR_STAT( interrupts );
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118
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119 cyg_drv_interrupt_mask(cpd->interrupt);
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120 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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121 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
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122 }
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123
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124 static void
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125 rhine_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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126 {
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127 // This conditioning out is necessary because of explicit calls to this
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128 // DSR - which would not ever be called in the case of a polled mode
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129 // usage ie. in RedBoot.
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130 #ifdef CYGPKG_IO_ETH_DRIVERS_NET
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131 struct rhine_priv_data* cpd = (struct rhine_priv_data *)data;
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132 struct cyg_netdevtab_entry *ndp = (struct cyg_netdevtab_entry *)(cpd->ndp);
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133 struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
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134
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135 // but here, it must be a *sc:
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136 eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
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137 #else
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138 # ifndef CYGPKG_REDBOOT
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139 # error Empty Rhine ethernet DSR is compiled. Is this what you want?
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140 # endif
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141 #endif
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142 }
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143
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144 // The deliver function (ex-DSR) handles the ethernet [logical] processing
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145 static void
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146 rhine_deliver(struct eth_drv_sc *sc)
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147 {
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148 struct rhine_priv_data *cpd = (struct rhine_priv_data *)sc->driver_private;
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149
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150 DEBUG_FUNCTION();
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151
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152 // Service the interrupt:
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153 rhine_poll(sc);
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154 // Allow interrupts to happen again
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155 cyg_drv_interrupt_unmask(cpd->interrupt);
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156 }
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157
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158 static int
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159 rhine_int_vector(struct eth_drv_sc *sc)
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160 {
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161 struct rhine_priv_data *cpd =
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162 (struct rhine_priv_data *)sc->driver_private;
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163
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164 return (cpd->interrupt);
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165 }
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166
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167 // ------------------------------------------------------------------------
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168 // Physical interface
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169 #if 0 // fix warning since this isn't actually used
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170 static void
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171 rhine_write_MII(struct rhine_priv_data *cpd, int id, int reg, cyg_uint16 value)
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172 {
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173 cyg_uint8 stat;
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174 int i = 1000;
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175
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176 // Wait for a previous access to complete (within reason)
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177 do {
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178 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_MIICR, stat);
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179 } while ((stat & (RHINE_MIICR_RCMD | RHINE_MIICR_WCMD)) && i-- > 0);
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180
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181 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIICR, 0);
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182 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_PHYADR, id);
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183 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIIAD, reg);
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184 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_MIIDATA, value);
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185 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIICR, RHINE_MIICR_WCMD);
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186 }
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187 #endif
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188
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189 static int
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190 rhine_read_MII(struct rhine_priv_data *cpd, int id, int reg)
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191 {
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192 int i = 1000;
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193 cyg_uint8 stat;
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194 cyg_uint16 val;
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195
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196 // Wait for a previous access to complete (within reason)
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197 do {
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198 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_MIICR, stat);
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199 } while ((stat & (RHINE_MIICR_RCMD | RHINE_MIICR_WCMD)) && i-- > 0);
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200
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201 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIICR, 0);
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202 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_PHYADR, id);
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203 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIIAD, reg);
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204 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_MIICR, RHINE_MIICR_RCMD);
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205
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206 i = 1000;
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207 do {
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208 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_MIICR, stat);
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209 } while ((stat & RHINE_MIICR_RCMD) && i-- > 0);
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210
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211 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_MIIDATA, val);
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212 return val;
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213 }
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214
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215 // ------------------------------------------------------------------------
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216 // Memory management
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217 //
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218 // Simply carve off from the front of the PCI mapped window into real memory
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219 static cyg_uint32 rhine_heap_size;
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220 static cyg_uint8 *rhine_heap_base;
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221 static cyg_uint8 *rhine_heap_free;
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222
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223 static void*
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224 pciwindow_mem_alloc(int size)
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225 {
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226 void *p_memory;
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227 int _size = size;
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228
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229 CYG_ASSERT(
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230 (CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE <= (int)rhine_heap_free)
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231 &&
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232 ((CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE +
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233 CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE) > (int)rhine_heap_free)
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234 &&
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235 (0 < rhine_heap_size)
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236 &&
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237 (CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE >= rhine_heap_size)
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238 &&
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239 (CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE == (int)rhine_heap_base),
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240 "Heap variables corrupted" );
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241
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242 p_memory = (void *)0;
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243 size = (size + 3) & ~3;
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244 if ( (rhine_heap_free+size) < (rhine_heap_base+rhine_heap_size) ) {
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245 cyg_uint32 *p;
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246 p_memory = (void *)rhine_heap_free;
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247 rhine_heap_free += size;
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248 for ( p = (cyg_uint32 *)p_memory; _size > 0; _size -= 4 )
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249 *p++ = 0;
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250 }
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251
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252 #if DEBUG & 9
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253 diag_printf("Allocated %d bytes at %08x\n", size, p_memory);
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254 #endif
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255
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256 return p_memory;
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257 }
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258
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259 static cyg_pci_match_func find_rhine_match_func;
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260
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261 static cyg_bool
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262 find_rhine_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
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263 {
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264 #if DEBUG & 9
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265 diag_printf("PCI match vendor %04x device %04x\n", v, d);
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266 #endif
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267 return
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268 (0x1106 == v) && // vendor: VIA
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269 ((0x3065 == d) || // device: DL10030A
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270 (0x3043 == d)); // device: VT86C100A
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271 }
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272
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273 static int
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274 pci_init_find_rhines( void )
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275 {
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276 cyg_pci_device_id devid;
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277 cyg_pci_device dev_info;
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278 cyg_uint16 cmd;
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279 int device_index;
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280 int found_devices = 0;
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281
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282 DEBUG_FUNCTION();
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283
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284 #ifdef CYGARC_UNCACHED_ADDRESS
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285 CYG_ASSERT( CYGARC_UNCACHED_ADDRESS((CYG_ADDRWORD)CYGMEM_SECTION_pci_window) ==
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286 CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE,
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287 "PCI window configured does not match PCI memory section base" );
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288 #else
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289 CYG_ASSERT( (CYG_ADDRWORD)CYGMEM_SECTION_pci_window ==
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290 CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE,
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291 "PCI window configured does not match PCI memory section base" );
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292 #endif
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293 CYG_ASSERT( CYGMEM_SECTION_pci_window_SIZE ==
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294 CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE,
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295 "PCI window configured does not match PCI memory section size" );
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296
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297 if (
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298 #ifdef CYGARC_UNCACHED_ADDRESS
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299 CYGARC_UNCACHED_ADDRESS((CYG_ADDRWORD)CYGMEM_SECTION_pci_window) !=
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300 #else
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301 (CYG_ADDRWORD)CYGMEM_SECTION_pci_window !=
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302 #endif
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303 CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE
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304 ||
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305 CYGMEM_SECTION_pci_window_SIZE !=
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306 CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE ) {
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307 #if DEBUG & 8
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308 diag_printf("pci_init_find_rhines(): PCI window misconfigured\n");
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309 #endif
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310 return 0;
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311 }
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312
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313 // First initialize the heap in PCI window'd memory
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314 rhine_heap_size = CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE;
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315 rhine_heap_base = (cyg_uint8 *)CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE;
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316 rhine_heap_free = rhine_heap_base;
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317
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318 cyg_pci_init();
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319 #if DEBUG & 8
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320 diag_printf("Finished cyg_pci_init();\n");
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321 #endif
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322
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323 devid = CYG_PCI_NULL_DEVID;
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324
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325 for (device_index = 0;
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326 device_index < CYGNUM_DEVS_ETH_VIA_RHINE_DEV_COUNT;
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327 device_index++) {
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328 struct rhine_priv_data* cpd = rhine_priv_array[device_index];
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329
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330 cpd->index = device_index;
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331
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332 // See above for find_rhine_match_func - it selects any of several
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333 // variants. This is necessary in case we have multiple mixed-type
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334 // devices on one board in arbitrary orders.
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335 if (cyg_pci_find_matching( &find_rhine_match_func, NULL, &devid )) {
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336 #if DEBUG & 8
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337 diag_printf("eth%d = rhine\n", device_index);
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338 #endif
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339 cyg_pci_get_device_info(devid, &dev_info);
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340
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341 cpd->interrupt_handle = 0; // Flag not attached.
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342 if (cyg_pci_translate_interrupt(&dev_info, &cpd->interrupt)) {
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343 #if DEBUG & 8
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344 diag_printf(" Wired to HAL vector %d\n", cpd->interrupt);
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345 #endif
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346 cyg_drv_interrupt_create(
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347 cpd->interrupt,
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348 1, // Priority - unused
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349 (cyg_addrword_t)cpd,// Data item passed to ISR & DSR
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350 rhine_isr, // ISR
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351 rhine_dsr, // DSR
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352 &cpd->interrupt_handle, // handle to intr obj
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353 &cpd->interrupt_object ); // space for int obj
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354
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355 cyg_drv_interrupt_attach(cpd->interrupt_handle);
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356
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357 // Don't unmask the interrupt yet, that could get us into a
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358 // race.
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359 }
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360 else {
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361 cpd->interrupt = 0;
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362 #if DEBUG & 8
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363 diag_printf(" Does not generate interrupts.\n");
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364 #endif
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365 }
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366
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367 if (cyg_pci_configure_device(&dev_info)) {
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368 #if DEBUG & 8
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369 int i;
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370 diag_printf("Found device on bus %d, devfn 0x%02x:\n",
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371 CYG_PCI_DEV_GET_BUS(devid),
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372 CYG_PCI_DEV_GET_DEVFN(devid));
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373
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374 if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
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375 diag_printf(" Note that board is active. Probed"
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376 " sizes and CPU addresses invalid!\n");
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377 }
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378 diag_printf(" Vendor 0x%04x", dev_info.vendor);
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379 diag_printf("\n Device 0x%04x", dev_info.device);
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380 diag_printf("\n Command 0x%04x, Status 0x%04x\n",
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381 dev_info.command, dev_info.status);
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382
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383 diag_printf(" Class/Rev 0x%08x", dev_info.class_rev);
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384 diag_printf("\n Header 0x%02x\n", dev_info.header_type);
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385
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386 diag_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
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387 dev_info.header.normal.sub_vendor,
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388 dev_info.header.normal.sub_id);
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389
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390 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
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391 diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
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392 diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
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393 dev_info.base_size[i], dev_info.base_map[i]);
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394 }
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395 diag_printf(" eth%d configured\n", device_index);
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396 #endif
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397 found_devices++;
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398 cpd->found = 1;
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399 cpd->active = 0;
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400 cpd->devid = devid;
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401 cpd->base = (unsigned char*) dev_info.base_map[0];
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402 #if DEBUG & 8
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403 diag_printf(" I/O address = 0x%08x\n", cpd->base);
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404 #endif
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405
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406 // Don't use cyg_pci_set_device_info since it clears
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407 // some of the fields we want to print out below.
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408 cyg_pci_read_config_uint16(dev_info.devid,
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409 CYG_PCI_CFG_COMMAND, &cmd);
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410 cmd |= (CYG_PCI_CFG_COMMAND_IO // enable I/O space
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411 | CYG_PCI_CFG_COMMAND_MEMORY // enable memory space
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412 | CYG_PCI_CFG_COMMAND_MASTER); // enable bus master
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413 cyg_pci_write_config_uint16(dev_info.devid,
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diff changeset
414 CYG_PCI_CFG_COMMAND, cmd);
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jlarmour
parents:
diff changeset
415
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jlarmour
parents:
diff changeset
416 // Extra init code needed for D-Link controller. This
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jlarmour
parents:
diff changeset
417 // is snuffed from the Linux driver and was provided
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jlarmour
parents:
diff changeset
418 // by D-Link. I've been unable to find documentation
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jlarmour
parents:
diff changeset
419 // for the part.
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jlarmour
parents:
diff changeset
420 if (0x3065 == dev_info.device) {
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jlarmour
parents:
diff changeset
421 cyg_uint8 tmp;
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jlarmour
parents:
diff changeset
422
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jlarmour
parents:
diff changeset
423 #if DEBUG & 8
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diff changeset
424 diag_printf("Pre-reset init code for D-Link.\n");
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diff changeset
425 #endif
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diff changeset
426 HAL_PCI_IO_READ_UINT8(cpd->base+RHINE_STICKYHW, tmp);
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jlarmour
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diff changeset
427 tmp &= 0xfc;
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jlarmour
parents:
diff changeset
428 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_STICKYHW, tmp);
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jlarmour
parents:
diff changeset
429
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parents:
diff changeset
430 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_WOL_CG_CLR, 0x80);
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jlarmour
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431 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_WOL_CR_CLR, 0xff);
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432 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_PWR_CSR_CLR, 0xff);
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diff changeset
433 }
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jlarmour
parents:
diff changeset
434
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jlarmour
parents:
diff changeset
435 // Now the PCI part of the device is configured, reset
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jlarmour
parents:
diff changeset
436 // it. This should make it safe to enable the
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jlarmour
parents:
diff changeset
437 // interrupt
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jlarmour
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diff changeset
438 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_CR1, RHINE_CR1_SRST);
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jlarmour
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diff changeset
439
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jlarmour
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diff changeset
440 // Reload ESA from EEPROM
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parents:
diff changeset
441 {
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diff changeset
442 cyg_uint8 tmp;
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jlarmour
parents:
diff changeset
443 int i;
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jlarmour
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diff changeset
444
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jlarmour
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diff changeset
445 #if DEBUG & 8
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diff changeset
446 diag_printf("Reload ESA from EEPROM...");
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diff changeset
447 #endif
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diff changeset
448 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_EECSR, 0x20);
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449 for (i = 0; i < 150; i++) {
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diff changeset
450 HAL_PCI_IO_READ_UINT8(cpd->base+RHINE_EECSR, tmp);
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diff changeset
451 if (!(tmp & 0x20)) {
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jlarmour
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diff changeset
452 break;
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diff changeset
453 }
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diff changeset
454 }
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jlarmour
parents:
diff changeset
455 #if DEBUG & 8
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jlarmour
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diff changeset
456 if (tmp & 0x20)
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diff changeset
457 diag_printf("Timed out\n");
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diff changeset
458 else
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diff changeset
459 diag_printf("Done\n");
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jlarmour
parents:
diff changeset
460 #endif
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diff changeset
461 }
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diff changeset
462
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jlarmour
parents:
diff changeset
463 // This is the indicator for "uses an interrupt"
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jlarmour
parents:
diff changeset
464 if (cpd->interrupt_handle != 0) {
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diff changeset
465 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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diff changeset
466 cyg_drv_interrupt_unmask(cpd->interrupt);
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diff changeset
467 #if DEBUG & 8
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468 diag_printf(" Enabled interrupt %d\n", cpd->interrupt);
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jlarmour
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diff changeset
469 #endif
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diff changeset
470 }
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diff changeset
471 #if DEBUG & 8
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jlarmour
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diff changeset
472 diag_printf(" **** Device enabled for I/O and Memory "
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jlarmour
parents:
diff changeset
473 "and Bus Master\n");
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jlarmour
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diff changeset
474 #endif
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diff changeset
475 }
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jlarmour
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diff changeset
476 else {
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jlarmour
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diff changeset
477 cpd->found = 0;
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diff changeset
478 cpd->active = 0;
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diff changeset
479 #if DEBUG & 8
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480 diag_printf("Failed to configure device %d\n", device_index);
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diff changeset
481 #endif
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diff changeset
482 }
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jlarmour
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diff changeset
483 }
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jlarmour
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diff changeset
484 else {
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jlarmour
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diff changeset
485 cpd->found = 0;
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diff changeset
486 cpd->active = 0;
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diff changeset
487 #if DEBUG & 8
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diff changeset
488 diag_printf("eth%d not found\n", device_index);
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jlarmour
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diff changeset
489 #endif
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jlarmour
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diff changeset
490 }
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jlarmour
parents:
diff changeset
491 }
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jlarmour
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diff changeset
492
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jlarmour
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diff changeset
493 if (0 == found_devices)
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diff changeset
494 return 0;
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diff changeset
495
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jlarmour
parents:
diff changeset
496 return 1;
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jlarmour
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diff changeset
497 }
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jlarmour
parents:
diff changeset
498
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jlarmour
parents:
diff changeset
499 static bool
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jlarmour
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diff changeset
500 via_rhine_init(struct cyg_netdevtab_entry *tab)
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jlarmour
parents:
diff changeset
501 {
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jlarmour
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diff changeset
502 static int initialized = 0; // only probe PCI et al *once*
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jlarmour
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diff changeset
503 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
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jlarmour
parents:
diff changeset
504 struct rhine_priv_data *cpd =
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jlarmour
parents:
diff changeset
505 (struct rhine_priv_data *)sc->driver_private;
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jlarmour
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diff changeset
506 cyg_uint8 *d, *p, *p_next;
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jlarmour
parents:
diff changeset
507 int i;
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jlarmour
parents:
diff changeset
508 cyg_addrword_t ba;
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jlarmour
parents:
diff changeset
509
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jlarmour
parents:
diff changeset
510 DEBUG_FUNCTION();
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jlarmour
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diff changeset
511
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jlarmour
parents:
diff changeset
512 if ( 0 == initialized++ ) {
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jlarmour
parents:
diff changeset
513 // then this is the first time ever:
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jlarmour
parents:
diff changeset
514 if ( ! pci_init_find_rhines() ) {
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jlarmour
parents:
diff changeset
515 #if DEBUG & 8
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jlarmour
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diff changeset
516 diag_printf( "pci_init_find_rhines failed" );
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jlarmour
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diff changeset
517 #endif
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jlarmour
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diff changeset
518 return false;
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jlarmour
parents:
diff changeset
519 }
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jlarmour
parents:
diff changeset
520 }
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jlarmour
parents:
diff changeset
521
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jlarmour
parents:
diff changeset
522 // If this device is not present, exit
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jlarmour
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diff changeset
523 if (0 == cpd->found)
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jlarmour
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diff changeset
524 return 0;
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jlarmour
parents:
diff changeset
525
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jlarmour
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diff changeset
526 #if DEBUG & 8
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jlarmour
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diff changeset
527 diag_printf( "Rhine device SC %08x CPD %08x\n", sc, cpd);
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jlarmour
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diff changeset
528 #endif
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jlarmour
parents:
diff changeset
529
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jlarmour
parents:
diff changeset
530 // Look for physical MII device
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jlarmour
parents:
diff changeset
531 for (i = 0; i < 32; i++) {
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jlarmour
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diff changeset
532 cyg_uint16 mii_status = rhine_read_MII(cpd, i, MII_BMSR);
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jlarmour
parents:
diff changeset
533 if (mii_status != 0x0000 && mii_status != 0xffff) {
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jlarmour
parents:
diff changeset
534 cpd->phys_id = i;
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jlarmour
parents:
diff changeset
535 #if DEBUG & 8
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jlarmour
parents:
diff changeset
536 diag_printf("Found MII interface at id %d, status %04x, adv 0x%04x, link 0x%04x\n",
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jlarmour
parents:
diff changeset
537 cpd->phys_id, mii_status, rhine_read_MII(cpd,i,4), rhine_read_MII(cpd,i,5));
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jlarmour
parents:
diff changeset
538 #endif
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jlarmour
parents:
diff changeset
539 break;
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jlarmour
parents:
diff changeset
540 }
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jlarmour
parents:
diff changeset
541 }
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jlarmour
parents:
diff changeset
542 #if DEBUG & 8
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jlarmour
parents:
diff changeset
543 if (i == 32)
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jlarmour
parents:
diff changeset
544 diag_printf("No MII interface found!");
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jlarmour
parents:
diff changeset
545 #endif
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jlarmour
parents:
diff changeset
546
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jlarmour
parents:
diff changeset
547 // Prepare ESA
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jlarmour
parents:
diff changeset
548 if (cpd->hardwired_esa) {
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jlarmour
parents:
diff changeset
549 // Force the NIC to use the specified ESA
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jlarmour
parents:
diff changeset
550 p = cpd->base + RHINE_PAR0;
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jlarmour
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diff changeset
551 for (i = 0; i < 6; i++)
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jlarmour
parents:
diff changeset
552 *p++ = cpd->esa[i];
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jlarmour
parents:
diff changeset
553 } else {
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jlarmour
parents:
diff changeset
554 // Use the address from the serial EEPROM
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jlarmour
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diff changeset
555 p = cpd->base + RHINE_PAR0;
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jlarmour
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diff changeset
556 for (i = 0; i < 6; i++)
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diff changeset
557 cpd->esa[i] = *p++;
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diff changeset
558 }
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diff changeset
559 #if DEBUG & 8
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560 diag_printf("RHINE - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
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561 (cpd->hardwired_esa) ? "static" : "eeprom",
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diff changeset
562 cpd->esa[0],
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diff changeset
563 cpd->esa[1],
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diff changeset
564 cpd->esa[2],
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diff changeset
565 cpd->esa[3],
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parents:
diff changeset
566 cpd->esa[4],
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diff changeset
567 cpd->esa[5] );
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diff changeset
568 #endif
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diff changeset
569
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diff changeset
570 // Prepare RX and TX rings
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571 p = cpd->rx_ring = (cyg_uint8*) CYGARC_UNCACHED_ADDRESS(pciwindow_mem_alloc((1<<cpd->rx_ring_log_cnt)*RHINE_RD_SIZE));
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diff changeset
572 d = cpd->rx_buffers = (cyg_uint8*) CYGARC_UNCACHED_ADDRESS(pciwindow_mem_alloc(_BUF_SIZE*cpd->rx_ring_cnt));
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573 for (i = 0; i < cpd->rx_ring_cnt; i++) {
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diff changeset
574 p_next = p + RHINE_RD_SIZE;
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diff changeset
575 HAL_PCI_CPU_TO_BUS((cyg_uint32)d, ba);
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576 _SU32(p, RHINE_RDES2) = ba;
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diff changeset
577 _SU32(p, RHINE_RDES1) = _BUF_SIZE;
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578 HAL_PCI_CPU_TO_BUS((cyg_uint32)p_next, ba);
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579 _SU32(p, RHINE_RDES3) = ba;
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580 _SU32(p, RHINE_RDES0) = RHINE_RDES0_OWN;
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581 #if DEBUG & 8
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582 diag_printf("Set RDES at 0x%08lx to 0x%08x 0x%08x 0x%08x 0x%08x\n",
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583 (unsigned long)p,
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584 _SU32(p, RHINE_RDES0), _SU32(p, RHINE_RDES1),
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585 _SU32(p, RHINE_RDES2), _SU32(p, RHINE_RDES3));
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586 #endif
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diff changeset
587 p = p_next;
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588 d += _BUF_SIZE;
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diff changeset
589 }
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590 // last entry wraps to the first
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591 p -= RHINE_RD_SIZE;
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592 HAL_PCI_CPU_TO_BUS((cyg_uint32)cpd->rx_ring, ba);
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593 _SU32(p, RHINE_RDES3) = ba;
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594 #if DEBUG & 8
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diff changeset
595 diag_printf("Set RDES at 0x%08lx to 0x%08x 0x%08x 0x%08x 0x%08x\n",
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596 (unsigned long)p,
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597 _SU32(p, RHINE_RDES0), _SU32(p, RHINE_RDES1),
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598 _SU32(p, RHINE_RDES2), _SU32(p, RHINE_RDES3));
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diff changeset
599 #endif
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diff changeset
600 cpd->rx_ring_next = 0;
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jlarmour
parents:
diff changeset
601 // CPU to PCI space translation
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diff changeset
602 HAL_PCI_CPU_TO_BUS((cyg_uint32)cpd->rx_ring, ba);
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603 HAL_PCI_IO_WRITE_UINT32(cpd->base + RHINE_CUR_RX, ba);
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diff changeset
604
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diff changeset
605 p = cpd->tx_ring = (cyg_uint8*) CYGARC_UNCACHED_ADDRESS(pciwindow_mem_alloc((1<<cpd->tx_ring_log_cnt)*RHINE_TD_SIZE));
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diff changeset
606 d = cpd->tx_buffers = (cyg_uint8*) CYGARC_UNCACHED_ADDRESS(pciwindow_mem_alloc(_BUF_SIZE*cpd->tx_ring_cnt));
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diff changeset
607 for (i = 0; i < cpd->tx_ring_cnt; i++) {
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diff changeset
608
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diff changeset
609 _SU32(p, RHINE_TDES0) = 0;
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610 _SU32(p, RHINE_TDES1) = (RHINE_TDES1_IC|RHINE_TDES1_EDP|RHINE_TDES1_STP|RHINE_TDES1_C);
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diff changeset
611 HAL_PCI_CPU_TO_BUS((cyg_uint32)d, ba);
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612 _SU32(p, RHINE_TDES2) = ba;
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613 HAL_PCI_CPU_TO_BUS((cyg_uint32)(p + RHINE_TD_SIZE), ba);
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614 _SU32(p, RHINE_TDES3) = ba;
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615 #if DEBUG & 8
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616 diag_printf("Set TDES at 0x%08lx to 0x%08x 0x%08x 0x%08x 0x%08x\n",
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617 (unsigned long)p,
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618 _SU32(p, RHINE_TDES0), _SU32(p, RHINE_TDES1),
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619 _SU32(p, RHINE_TDES2), _SU32(p, RHINE_TDES3));
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620 #endif
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621 p += RHINE_TD_SIZE;
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622 d += _BUF_SIZE;
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623 }
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624
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625 // last entry wraps to the first
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626 p -= RHINE_TD_SIZE;
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627 HAL_PCI_CPU_TO_BUS((cyg_uint32)cpd->tx_ring, ba);
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628 _SU32(p, RHINE_TDES3) = ba;
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629 #if DEBUG & 8
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630 diag_printf("Set TDES at 0x%08lx to 0x%08x 0x%08x 0x%08x 0x%08x\n",
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diff changeset
631 (unsigned long)p,
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632 _SU32(p, RHINE_TDES0), _SU32(p, RHINE_TDES1),
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633 _SU32(p, RHINE_TDES2), _SU32(p, RHINE_TDES3));
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634 #endif
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diff changeset
635 cpd->tx_ring_free = cpd->tx_ring_alloc = cpd->tx_ring_owned = 0;
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636 HAL_PCI_CPU_TO_BUS((cyg_uint32)cpd->tx_ring, ba);
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diff changeset
637 HAL_PCI_IO_WRITE_UINT32(cpd->base + RHINE_CUR_TX, ba);
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diff changeset
638
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639 cpd->txbusy = 0;
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diff changeset
640
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diff changeset
641 #if DEBUG & 9
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642 {
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643 cyg_uint8 tmp1, tmp2;
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644 HAL_PCI_IO_READ_UINT8(cpd->base+RHINE_CR0, tmp1);
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diff changeset
645 HAL_PCI_IO_READ_UINT8(cpd->base+RHINE_CR1, tmp2);
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646 diag_printf("CR0: %02x CR1: %02x\n", tmp1, tmp2);
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647 }
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diff changeset
648 #endif
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649
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650 // and record the net dev pointer
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651 cpd->ndp = (void *)tab;
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652
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653 // Initialize upper level driver
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654 (sc->funs->eth_drv->init)(sc, cpd->esa);
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655
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656 #if DEBUG & 9
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657 diag_printf("Done\n");
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658 #endif
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659 return true;
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660 }
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diff changeset
661
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662 static void
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663 rhine_stop(struct eth_drv_sc *sc)
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664 {
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665 struct rhine_priv_data *cpd =
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666 (struct rhine_priv_data *)sc->driver_private;
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667
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668 DEBUG_FUNCTION();
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diff changeset
669
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670 // Stop chip
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671 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_CR0, RHINE_CR0_STOP);
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672 }
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673
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674 //
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675 // This function is called to "start up" the interface. It may be called
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diff changeset
676 // multiple times, even when the hardware is already running. It will be
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diff changeset
677 // called whenever something "hardware oriented" changes and should leave
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diff changeset
678 // the hardware ready to send/receive packets.
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diff changeset
679 //
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diff changeset
680 static void
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diff changeset
681 rhine_start(struct eth_drv_sc *sc, unsigned char *esa, int flags)
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diff changeset
682 {
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diff changeset
683 #ifdef CYGPKG_NET
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diff changeset
684 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
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685 #endif
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diff changeset
686 struct rhine_priv_data *cpd =
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diff changeset
687 (struct rhine_priv_data *)sc->driver_private;
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jlarmour
parents:
diff changeset
688
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jlarmour
parents:
diff changeset
689 DEBUG_FUNCTION();
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jlarmour
parents:
diff changeset
690 // Disable device
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jlarmour
parents:
diff changeset
691 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, RHINE_CR0_STOP);
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jlarmour
parents:
diff changeset
692 // Ack old interrupts
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jlarmour
parents:
diff changeset
693 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, 0xffff);
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jlarmour
parents:
diff changeset
694 // Enable interrupts
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jlarmour
parents:
diff changeset
695 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_IMR, RHINE_IMR_INIT);
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jlarmour
parents:
diff changeset
696 // Enable duplex
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parents:
diff changeset
697 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_CR1, RHINE_CR1_DPOLL /* | RHINE_CR1_FDX*/);
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jlarmour
parents:
diff changeset
698 // Accept broadcast, multicast and small packets
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jlarmour
parents:
diff changeset
699 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_RCR, RHINE_RCR_AB | RHINE_RCR_AM | RHINE_RCR_AR);
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jlarmour
parents:
diff changeset
700 // Tweak some magic (undocumented) parameters
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jlarmour
parents:
diff changeset
701 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_BCR0, RHINE_BCR0_MAGIC_INIT);
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jlarmour
parents:
diff changeset
702 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_BCR1, RHINE_BCR1_MAGIC_INIT);
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jlarmour
parents:
diff changeset
703
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jlarmour
parents:
diff changeset
704 #if 1 // FIXME
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jlarmour
parents:
diff changeset
705 HAL_PCI_IO_WRITE_UINT8(cpd->base+RHINE_TCR, 0x20);
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jlarmour
parents:
diff changeset
706 #endif
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jlarmour
parents:
diff changeset
707
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jlarmour
parents:
diff changeset
708 #ifdef CYGPKG_NET
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jlarmour
parents:
diff changeset
709 if (( 0
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parents:
diff changeset
710 #ifdef ETH_DRV_FLAGS_PROMISC_MODE
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parents:
diff changeset
711 != (flags & ETH_DRV_FLAGS_PROMISC_MODE)
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jlarmour
parents:
diff changeset
712 #endif
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jlarmour
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diff changeset
713 ) || (ifp->if_flags & IFF_PROMISC)
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jlarmour
parents:
diff changeset
714 ) {
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jlarmour
parents:
diff changeset
715 // Then we select promiscuous mode.
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jlarmour
parents:
diff changeset
716 cyg_uint8 rcr;
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diff changeset
717 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_RCR, rcr);
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diff changeset
718 rcr |= RHINE_RCR_PRO;
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jlarmour
parents:
diff changeset
719 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_RCR, rcr);
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jlarmour
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diff changeset
720 }
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jlarmour
parents:
diff changeset
721 #endif
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jlarmour
parents:
diff changeset
722 // Enable device
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jlarmour
parents:
diff changeset
723 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, RHINE_CR0_STRT | RHINE_CR0_RXON | RHINE_CR0_TXON);
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jlarmour
parents:
diff changeset
724 }
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jlarmour
parents:
diff changeset
725
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jlarmour
parents:
diff changeset
726 //
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jlarmour
parents:
diff changeset
727 // This routine is called to perform special "control" opertions
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jlarmour
parents:
diff changeset
728 //
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jlarmour
parents:
diff changeset
729 static int
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jlarmour
parents:
diff changeset
730 rhine_control(struct eth_drv_sc *sc, unsigned long key,
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jlarmour
parents:
diff changeset
731 void *data, int data_length)
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jlarmour
parents:
diff changeset
732 {
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jlarmour
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diff changeset
733 cyg_uint8 *esa = (cyg_uint8 *)data;
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jlarmour
parents:
diff changeset
734 int i, res;
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jlarmour
parents:
diff changeset
735 cyg_uint8 reg, old_stat;
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jlarmour
parents:
diff changeset
736 struct rhine_priv_data *cpd =
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jlarmour
parents:
diff changeset
737 (struct rhine_priv_data *)sc->driver_private;
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jlarmour
parents:
diff changeset
738
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jlarmour
parents:
diff changeset
739 DEBUG_FUNCTION();
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jlarmour
parents:
diff changeset
740
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jlarmour
parents:
diff changeset
741 // Stop the controller while accessing (possibly altering) registers
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jlarmour
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diff changeset
742 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_CR0, old_stat);
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jlarmour
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diff changeset
743 reg = old_stat;
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jlarmour
parents:
diff changeset
744 reg |= RHINE_CR0_STOP;
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jlarmour
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diff changeset
745 reg &= ~RHINE_CR0_STRT;
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jlarmour
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diff changeset
746 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, reg);
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jlarmour
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diff changeset
747
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jlarmour
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diff changeset
748 res = 0; // expect success
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jlarmour
parents:
diff changeset
749 switch (key) {
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jlarmour
parents:
diff changeset
750 case ETH_DRV_SET_MAC_ADDRESS:
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jlarmour
parents:
diff changeset
751 #if DEBUG & 9
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jlarmour
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diff changeset
752 diag_printf("RHINE - set ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
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jlarmour
parents:
diff changeset
753 esa[0],
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jlarmour
parents:
diff changeset
754 esa[1],
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jlarmour
parents:
diff changeset
755 esa[2],
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jlarmour
parents:
diff changeset
756 esa[3],
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jlarmour
parents:
diff changeset
757 esa[4],
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jlarmour
parents:
diff changeset
758 esa[5] );
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jlarmour
parents:
diff changeset
759 #endif // DEBUG
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parents:
diff changeset
760
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jlarmour
parents:
diff changeset
761 for ( i = 0; i < sizeof(cpd->esa); i++ ) {
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jlarmour
parents:
diff changeset
762 cpd->esa[i] = esa[i];
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jlarmour
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diff changeset
763 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_PAR0 + i, esa[i]);
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jlarmour
parents:
diff changeset
764 }
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jlarmour
parents:
diff changeset
765 break;
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jlarmour
parents:
diff changeset
766
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jlarmour
parents:
diff changeset
767 #ifdef ETH_DRV_GET_MAC_ADDRESS
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jlarmour
parents:
diff changeset
768 case ETH_DRV_GET_MAC_ADDRESS:
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jlarmour
parents:
diff changeset
769 // Extract the MAC address that is in the chip, and tell the
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jlarmour
parents:
diff changeset
770 // system about it.
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jlarmour
parents:
diff changeset
771 for (i = 0; i < sizeof(cpd->esa); i++) {
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jlarmour
parents:
diff changeset
772 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_PAR0 + i, esa[i]);
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jlarmour
parents:
diff changeset
773 }
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jlarmour
parents:
diff changeset
774 break;
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jlarmour
parents:
diff changeset
775 #endif
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jlarmour
parents:
diff changeset
776
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jlarmour
parents:
diff changeset
777 #ifdef ETH_DRV_GET_IF_STATS_UD
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jlarmour
parents:
diff changeset
778 case ETH_DRV_GET_IF_STATS_UD: // UD == UPDATE
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jlarmour
parents:
diff changeset
779 #endif
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jlarmour
parents:
diff changeset
780 // drop through
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jlarmour
parents:
diff changeset
781 #ifdef ETH_DRV_GET_IF_STATS
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jlarmour
parents:
diff changeset
782 case ETH_DRV_GET_IF_STATS:
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jlarmour
parents:
diff changeset
783 #endif
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jlarmour
parents:
diff changeset
784
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jlarmour
parents:
diff changeset
785 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
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jlarmour
parents:
diff changeset
786 {
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jlarmour
parents:
diff changeset
787 cyg_uint8 reg;
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jlarmour
parents:
diff changeset
788 struct ether_drv_stats *p = (struct ether_drv_stats *)data;
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jlarmour
parents:
diff changeset
789 // Chipset entry is no longer supported; RFC1573.
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jlarmour
parents:
diff changeset
790 for ( i = 0; i < SNMP_CHIPSET_LEN; i++ )
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jlarmour
parents:
diff changeset
791 p->snmp_chipset[i] = 0;
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jlarmour
parents:
diff changeset
792
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jlarmour
parents:
diff changeset
793 // This perhaps should be a config opt, so you can make up your own
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jlarmour
parents:
diff changeset
794 // description, or supply it from the instantiation.
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jlarmour
parents:
diff changeset
795 strcpy( p->description, "VIA Rhine" );
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jlarmour
parents:
diff changeset
796 // CYG_ASSERT( 48 > strlen(p->description), "Description too long" );
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jlarmour
parents:
diff changeset
797
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jlarmour
parents:
diff changeset
798 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_MIISR, reg);
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jlarmour
parents:
diff changeset
799 if (reg & RHINE_MIISR_LNKFL) {
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jlarmour
parents:
diff changeset
800 p->operational = 2; // LINK DOWN
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jlarmour
parents:
diff changeset
801 p->duplex = 1; // UNKNOWN
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jlarmour
parents:
diff changeset
802 p->speed = 0;
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jlarmour
parents:
diff changeset
803 }
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jlarmour
parents:
diff changeset
804 else {
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jlarmour
parents:
diff changeset
805 p->operational = 3; // LINK UP
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jlarmour
parents:
diff changeset
806 p->speed = (reg & RHINE_MIISR_SPEED) ? 10 * 1000000 : 100 * 1000000;
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jlarmour
parents:
diff changeset
807 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_CR1, reg);
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jlarmour
parents:
diff changeset
808 if (reg & RHINE_CR1_FDX)
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jlarmour
parents:
diff changeset
809 p->duplex = 3; // 3 = DUPLEX
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jlarmour
parents:
diff changeset
810 else
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jlarmour
parents:
diff changeset
811 p->duplex = 2; // 2 = SIMPLEX
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jlarmour
parents:
diff changeset
812 }
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jlarmour
parents:
diff changeset
813
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jlarmour
parents:
diff changeset
814 #ifdef KEEP_STATISTICS
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jlarmour
parents:
diff changeset
815 {
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jlarmour
parents:
diff changeset
816 struct via_rhine_stats *ps = &(cpd->stats);
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jlarmour
parents:
diff changeset
817
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jlarmour
parents:
diff changeset
818 // Admit to it...
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jlarmour
parents:
diff changeset
819 p->supports_dot3 = true;
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jlarmour
parents:
diff changeset
820
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jlarmour
parents:
diff changeset
821 p->tx_good = ps->tx_good ;
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jlarmour
parents:
diff changeset
822 p->tx_max_collisions = ps->tx_max_collisions ;
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jlarmour
parents:
diff changeset
823 p->tx_late_collisions = ps->tx_late_collisions ;
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jlarmour
parents:
diff changeset
824 p->tx_underrun = ps->tx_underrun ;
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jlarmour
parents:
diff changeset
825 p->tx_carrier_loss = ps->tx_carrier_loss ;
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jlarmour
parents:
diff changeset
826 p->tx_deferred = ps->tx_deferred ;
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jlarmour
parents:
diff changeset
827 p->tx_sqetesterrors = ps->tx_sqetesterrors ;
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jlarmour
parents:
diff changeset
828 p->tx_single_collisions = ps->tx_single_collisions;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
829 p->tx_mult_collisions = ps->tx_mult_collisions ;
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jlarmour
parents:
diff changeset
830 p->tx_total_collisions = ps->tx_total_collisions ;
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jlarmour
parents:
diff changeset
831 p->rx_good = ps->rx_good ;
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jlarmour
parents:
diff changeset
832 p->rx_crc_errors = ps->rx_crc_errors ;
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jlarmour
parents:
diff changeset
833 p->rx_align_errors = ps->rx_align_errors ;
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jlarmour
parents:
diff changeset
834 p->rx_resource_errors = ps->rx_resource_errors ;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
835 p->rx_overrun_errors = ps->rx_overrun_errors ;
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jlarmour
parents:
diff changeset
836 p->rx_collisions = ps->rx_collisions ;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
837 p->rx_short_frames = ps->rx_short_frames ;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
838 p->rx_too_long_frames = ps->rx_too_long_frames ;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
839 p->rx_symbol_errors = ps->rx_symbol_errors ;
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jlarmour
parents:
diff changeset
840
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jlarmour
parents:
diff changeset
841 p->interrupts = ps->interrupts ;
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jlarmour
parents:
diff changeset
842 p->rx_count = ps->rx_count ;
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jlarmour
parents:
diff changeset
843 p->rx_deliver = ps->rx_deliver ;
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jlarmour
parents:
diff changeset
844 p->rx_resource = ps->rx_resource ;
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jlarmour
parents:
diff changeset
845 p->rx_restart = ps->rx_restart ;
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jlarmour
parents:
diff changeset
846 p->tx_count = ps->tx_count ;
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jlarmour
parents:
diff changeset
847 p->tx_complete = ps->tx_complete ;
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jlarmour
parents:
diff changeset
848 p->tx_dropped = ps->tx_dropped ;
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jlarmour
parents:
diff changeset
849 }
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jlarmour
parents:
diff changeset
850 #endif // KEEP_STATISTICS
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jlarmour
parents:
diff changeset
851
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jlarmour
parents:
diff changeset
852 p->tx_queue_len = 1;
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jlarmour
parents:
diff changeset
853 break;
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jlarmour
parents:
diff changeset
854 }
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jlarmour
parents:
diff changeset
855 #endif
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jlarmour
parents:
diff changeset
856 default:
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jlarmour
parents:
diff changeset
857 res = 1;
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jlarmour
parents:
diff changeset
858 break;
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jlarmour
parents:
diff changeset
859 }
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jlarmour
parents:
diff changeset
860
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jlarmour
parents:
diff changeset
861 // Restore controller state
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jlarmour
parents:
diff changeset
862 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, old_stat);
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jlarmour
parents:
diff changeset
863
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jlarmour
parents:
diff changeset
864 return res;
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jlarmour
parents:
diff changeset
865 }
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jlarmour
parents:
diff changeset
866
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
867 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
868 // This routine is called to see if it is possible to send another packet.
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jlarmour
parents:
diff changeset
869 // It will return non-zero if a transmit is possible, zero otherwise.
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jlarmour
parents:
diff changeset
870 //
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jlarmour
parents:
diff changeset
871 static int
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jlarmour
parents:
diff changeset
872 rhine_can_send(struct eth_drv_sc *sc)
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jlarmour
parents:
diff changeset
873 {
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jlarmour
parents:
diff changeset
874 cyg_uint8 stat;
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jlarmour
parents:
diff changeset
875 struct rhine_priv_data *cpd =
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jlarmour
parents:
diff changeset
876 (struct rhine_priv_data *)sc->driver_private;
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jlarmour
parents:
diff changeset
877
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jlarmour
parents:
diff changeset
878 DEBUG_FUNCTION();
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
879
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jlarmour
parents:
diff changeset
880 // This MII read forces the MIISR to get updated
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
881 (void) rhine_read_MII(cpd, cpd->phys_id, MII_BMSR);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
882 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_MIISR, stat);
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jlarmour
parents:
diff changeset
883 if (stat & RHINE_MIISR_LNKFL) {
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jlarmour
parents:
diff changeset
884 #if DEBUG & 1
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jlarmour
parents:
diff changeset
885 diag_printf("*** Link failure\n");
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jlarmour
parents:
diff changeset
886 #endif
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jlarmour
parents:
diff changeset
887 return false; // Link not connected
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jlarmour
parents:
diff changeset
888 }
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jlarmour
parents:
diff changeset
889
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jlarmour
parents:
diff changeset
890 return (cpd->txbusy == 0);
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jlarmour
parents:
diff changeset
891 }
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jlarmour
parents:
diff changeset
892
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
893 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
894 // This routine is called to send data to the hardware.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
895 static void
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
896 rhine_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
897 int total_len, unsigned long key)
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jlarmour
parents:
diff changeset
898 {
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
899 struct rhine_priv_data *cpd =
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
900 (struct rhine_priv_data *)sc->driver_private;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
901 int i, len, plen, ring_entry;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
902
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
903 cyg_uint8* sdata = NULL;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
904 cyg_uint8 *d, *buf, *txd;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
905 cyg_uint16 status;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
906 cyg_uint8 cr0;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
907
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
908 DEBUG_FUNCTION();
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
909
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
910 INCR_STAT( tx_count );
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
911
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
912 // Worry about the engine stopping.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
913 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_CR0, status);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
914 if ( 0 == (RHINE_CR0_STRT & status) ) {
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
915 #if DEBUG & 1
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
916 diag_printf("%s: ENGINE RESTART: status %04x\n", __FUNCTION__, status);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
917 #endif
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
918 status &= ~RHINE_CR0_STOP;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
919 status |= RHINE_CR0_STRT;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
920 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, status);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
921 }
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
922
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
923 cpd->txbusy = 1;
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jlarmour
parents:
diff changeset
924 cpd->txkey = key;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
925
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
926 // Find packet length
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
927 plen = 0;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
928 for (i = 0; i < sg_len; i++)
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
929 plen += sg_list[i].len;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
930
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
931 CYG_ASSERT( plen == total_len, "sg data length mismatch" );
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
932
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
933 // Get next TX descriptor
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
934 ring_entry = cpd->tx_ring_free;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
935 do {
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
936 if (cpd->tx_ring_owned == cpd->tx_ring_cnt) {
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
937 // Is this a dead end? Probably is.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
938 #if DEBUG & 1
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
939 diag_printf("%s: Allocation failed! Retrying...\n", __FUNCTION__ );
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
940 #endif
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
941 continue;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
942 }
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
943
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
944 cpd->tx_ring_free++;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
945 cpd->tx_ring_owned++;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
946 if (cpd->tx_ring_free == cpd->tx_ring_cnt)
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
947 cpd->tx_ring_free = 0;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
948 } while (0);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
949
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
950 txd = cpd->tx_ring + ring_entry*RHINE_TD_SIZE;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
951 buf = cpd->tx_buffers + ring_entry*_BUF_SIZE;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
952 CYG_ASSERT(0 == (_SU32(txd, RHINE_TDES0) & RHINE_TDES0_OWN),
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
953 "TX descriptor not free");
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
954
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
955 #if DEBUG & 4
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
956 diag_printf("##Tx descriptor index %d TDES %08x buffer %08x\n",
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
957 ring_entry, txd, buf);
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
958 #endif
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jlarmour
parents:
diff changeset
959
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
960 // Put data into buffer
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
961 d = buf;
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST
jlarmour
parents:
diff changeset
962 for (i = 0; i < sg_len; i++) {
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jlarmour
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963 sdata = (cyg_uint8 *)sg_list[i].buf;
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diff changeset
964 len = sg_list[i].len;
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diff changeset
965
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diff changeset
966 CYG_ASSERT( sdata, "No sg data pointer here" );
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diff changeset
967 while(len--)
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diff changeset
968 *d++ = *sdata++;
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diff changeset
969 }
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diff changeset
970 CYG_ASSERT( sdata, "No sg data pointer outside" );
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971
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diff changeset
972 // Annoyingly the chip doesn't pad to minimal packet size, so do
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diff changeset
973 // that by steam
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diff changeset
974 if (plen < 60) {
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diff changeset
975 plen = 60;
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diff changeset
976 #if DEBUG & 4
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diff changeset
977 diag_printf("Padded %d bytes packet to 60 bytes\n", plen);
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diff changeset
978 #endif
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diff changeset
979 }
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diff changeset
980
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981 CYG_ASSERT( (plen & RHINE_TDES1_TLNG_mask) == plen, "packet too long");
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diff changeset
982 CYG_ASSERT( (plen & RHINE_TDES1_TLNG_mask) >= 60, "packet too short");
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diff changeset
983 _SU32(txd, RHINE_TDES1) &= ~RHINE_TDES1_TLNG_mask;
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diff changeset
984 _SU32(txd, RHINE_TDES1) |= plen;
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diff changeset
985 _SU32(txd, RHINE_TDES0) = RHINE_TDES0_OWN;
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diff changeset
986
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diff changeset
987 #if DEBUG & 1 // FIXME
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diff changeset
988 diag_printf("Before TX: Desc (@0x%08lx) %08x %08x %08x %08x\n Next (@0x%08lx) %08x %08x %08x %08x\n",
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989 (unsigned long) txd,
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990 _SU32(txd, RHINE_TDES0), _SU32(txd, RHINE_TDES1),
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diff changeset
991 _SU32(txd, RHINE_TDES2), _SU32(txd, RHINE_TDES3),
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diff changeset
992 ( (unsigned long)txd)+0x10,
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diff changeset
993 _SU32(txd, (0x10+RHINE_TDES0)), _SU32(txd, (0x10+RHINE_TDES1)),
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994 _SU32(txd,(0x10+ RHINE_TDES2)), _SU32(txd,(0x10+ RHINE_TDES3)));
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diff changeset
995 #endif
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diff changeset
996
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diff changeset
997 // Ack TX empty int
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diff changeset
998 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, RHINE_ISR_PTX);
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diff changeset
999 // Set transmit demand
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diff changeset
1000 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_CR0, cr0);
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diff changeset
1001 cr0 |= RHINE_CR0_TDMD;
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diff changeset
1002 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, cr0);
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1003
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diff changeset
1004 #if DEBUG & 1
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diff changeset
1005 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_ISR, status);
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1006 diag_printf("%s:END: ints at TX: %04x\n", __FUNCTION__, status);
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diff changeset
1007 #endif
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diff changeset
1008
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diff changeset
1009 }
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diff changeset
1010
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1011 static void
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diff changeset
1012 rhine_TxEvent(struct eth_drv_sc *sc, int stat)
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1013 {
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1014 struct rhine_priv_data *cpd =
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diff changeset
1015 (struct rhine_priv_data *)sc->driver_private;
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1016 int success = 1;
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1017 cyg_uint8 *txd;
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1018 cyg_uint8 status;
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diff changeset
1019
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diff changeset
1020 DEBUG_FUNCTION();
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1021
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1022 INCR_STAT( tx_complete );
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1023
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1024 txd = cpd->tx_ring + cpd->tx_ring_alloc*RHINE_TD_SIZE;
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1025 #if DEBUG & 4
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1026 diag_printf("##Tx packet %d freed %08x %08x!\n", cpd->tx_ring_alloc, txd, _SU32(txd, RHINE_TDES0) );
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1027 #endif
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diff changeset
1028 if ((_SU32(txd, RHINE_TDES0) & RHINE_TDES0_OWN)) {
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diff changeset
1029 #if DEBUG & 1
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diff changeset
1030 diag_printf("%s: got TX completion when buffer is still owned\n", __FUNCTION__);
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diff changeset
1031 #endif
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1032 // first dirty ring entry not freed - wtf?
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diff changeset
1033 }
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diff changeset
1034 cpd->tx_ring_alloc++;
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diff changeset
1035 if (cpd->tx_ring_alloc == cpd->tx_ring_cnt)
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diff changeset
1036 cpd->tx_ring_alloc = 0;
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diff changeset
1037 cpd->tx_ring_owned--;
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diff changeset
1038
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diff changeset
1039 #ifdef KEEP_STATISTICS
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1040 {
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diff changeset
1041 cyg_uint32 reg = _SU32(txd, RHINE_TDES0);
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diff changeset
1042 int collisions;
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diff changeset
1043
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diff changeset
1044 // Covering each bit in turn...
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diff changeset
1045 if ( reg & RHINE_TDES0_TXOK ) INCR_STAT( tx_good );
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diff changeset
1046 if ( reg & RHINE_TDES0_CRS ) INCR_STAT( tx_carrier_loss );
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diff changeset
1047 if ( reg & RHINE_TDES0_OWC ) INCR_STAT( tx_late_collisions );
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diff changeset
1048 if ( reg & RHINE_TDES0_ABT ) INCR_STAT( tx_max_collisions );
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diff changeset
1049
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diff changeset
1050 if ( reg & RHINE_TDES0_DFR ) INCR_STAT( tx_deferred );
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diff changeset
1051
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diff changeset
1052 collisions = ((reg & RHINE_TDES0_NCR_mask) >> RHINE_TDES0_NCR_shift);
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diff changeset
1053 if (1 == collisions)
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diff changeset
1054 INCR_STAT( tx_single_collisions );
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diff changeset
1055 else if (1 < collisions)
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diff changeset
1056 INCR_STAT( tx_mult_collisions );
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diff changeset
1057
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diff changeset
1058 cpd->stats.tx_total_collisions =
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diff changeset
1059 cpd->stats.tx_late_collisions +
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diff changeset
1060 cpd->stats.tx_max_collisions +
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diff changeset
1061 cpd->stats.tx_mult_collisions +
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diff changeset
1062 cpd->stats.tx_single_collisions;
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diff changeset
1063 }
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diff changeset
1064 #endif // KEEP_STATISTICS
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diff changeset
1065
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diff changeset
1066 // We do not really care about Tx failure. Ethernet is not a reliable
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diff changeset
1067 // medium. But we do care about the TX engine stopping.
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diff changeset
1068 HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_CR0, status);
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diff changeset
1069 if ( 0 == (RHINE_CR0_STRT & status) ) {
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diff changeset
1070 #if DEBUG & 1
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diff changeset
1071 diag_printf("%s: ENGINE RESTART: status %04x\n", __FUNCTION__, status);
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diff changeset
1072 #endif
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diff changeset
1073 status &= ~RHINE_CR0_STOP;
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diff changeset
1074 status |= RHINE_CR0_STRT;
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diff changeset
1075 HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_CR0, status);
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diff changeset
1076 success = 0; // And treat this as an error...
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diff changeset
1077 }
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diff changeset
1078
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diff changeset
1079 if ( cpd->txbusy ) {
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diff changeset
1080 cpd->txbusy = 0;
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diff changeset
1081 (sc->funs->eth_drv->tx_done)(sc, cpd->txkey, success);
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diff changeset
1082 }
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diff changeset
1083
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diff changeset
1084 // Ack TX interrupt set
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diff changeset
1085 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, RHINE_ISR_PTX);
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diff changeset
1086 }
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diff changeset
1087
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parents:
diff changeset
1088 //
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diff changeset
1089 // This function is called when a packet has been received. Its job is
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diff changeset
1090 // to prepare to unload the packet from the hardware. Once the length of
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diff changeset
1091 // the packet is known, the upper layer of the driver can be told. When
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jlarmour
parents:
diff changeset
1092 // the upper layer is ready to unload the packet, the internal function
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parents:
diff changeset
1093 // 'rhine_recv' will be called to actually fetch it from the hardware.
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jlarmour
parents:
diff changeset
1094 //
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jlarmour
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diff changeset
1095 static void
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1096 rhine_RxEvent(struct eth_drv_sc *sc)
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1097 {
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diff changeset
1098 struct rhine_priv_data *cpd =
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diff changeset
1099 (struct rhine_priv_data *)sc->driver_private;
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1100 cyg_uint8 *rxd;
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diff changeset
1101 cyg_uint32 rstat;
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1102 cyg_uint16 ints, len, mask;
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diff changeset
1103
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1104 DEBUG_FUNCTION();
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1105
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1106 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_ISR, ints);
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1107 #if DEBUG & 1
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1108 diag_printf("RxEvent - CSR: 0x%04x\n", ints);
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1109 #endif
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diff changeset
1110 if ( 0 == (RHINE_ISR_PRX & ints) )
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1111 // Then there's no RX event pending
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1112 return;
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diff changeset
1113
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1114 // Mask interrupt
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diff changeset
1115 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_IMR, mask);
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1116 mask &= ~RHINE_IMR_PRX;
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diff changeset
1117 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_IMR, mask);
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1118
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diff changeset
1119 while (1) {
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diff changeset
1120 // Get state of next (supposedly) full ring entry
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diff changeset
1121 cpd->rxpacket = cpd->rx_ring_next;
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1122 rxd = cpd->rx_ring + cpd->rxpacket*RHINE_RD_SIZE;
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1123 rstat = _SU32(rxd, RHINE_RDES0);
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diff changeset
1124
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diff changeset
1125 // Keep going until we hit an entry that is owned by the
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parents:
diff changeset
1126 // controller.
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1127 if (rstat & RHINE_RDES0_OWN) {
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diff changeset
1128 #ifdef CYGDBG_USE_ASSERTS
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diff changeset
1129 // Sanity check of queue
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diff changeset
1130 int i;
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1131 for (i = 0; i < cpd->rx_ring_cnt; i++) {
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diff changeset
1132 rxd = cpd->rx_ring + i*RHINE_RD_SIZE;
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diff changeset
1133 rstat = _SU32(rxd, RHINE_RDES0);
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diff changeset
1134
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diff changeset
1135 if (!(rstat & RHINE_RDES0_OWN)) {
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diff changeset
1136 int i;
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diff changeset
1137 cyg_uint32 rstat;
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diff changeset
1138 cyg_uint8* rxd;
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1139
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1140 diag_printf("####Rx %s Inconsistent RX state - next was %d\n",
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diff changeset
1141 __FUNCTION__, cpd->rx_ring_next);
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diff changeset
1142 for (i = 0; i < cpd->rx_ring_cnt; i++) {
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diff changeset
1143 rxd = cpd->rx_ring + i*RHINE_RD_SIZE;
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diff changeset
1144 rstat = _SU32(rxd, RHINE_RDES0);
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diff changeset
1145 diag_printf("#### %02d: 0x%08x\n", i, rstat);
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diff changeset
1146 }
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diff changeset
1147 }
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diff changeset
1148 break;
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diff changeset
1149 }
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diff changeset
1150 #endif
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diff changeset
1151 break;
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diff changeset
1152 }
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diff changeset
1153
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diff changeset
1154 #if DEBUG & 4
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diff changeset
1155 diag_printf("##Rx packet %d RDES %08x stat %08x\n",
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diff changeset
1156 cpd->rxpacket, rxd, rstat);
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diff changeset
1157 #endif
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diff changeset
1158
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diff changeset
1159 // Increment counts
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diff changeset
1160 INCR_STAT( rx_count );
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diff changeset
1161 cpd->rx_ring_next++;
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diff changeset
1162 if (cpd->rx_ring_next == cpd->rx_ring_cnt) cpd->rx_ring_next = 0;
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diff changeset
1163
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diff changeset
1164 len = (rstat & RHINE_RDES0_FLNG_mask) >> RHINE_RDES0_FLNG_shift;
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diff changeset
1165
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diff changeset
1166 #ifdef KEEP_STATISTICS
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diff changeset
1167 if ( rstat & RHINE_RDES0_CRC ) INCR_STAT( rx_crc_errors );
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diff changeset
1168 if ( rstat & RHINE_RDES0_FAE ) INCR_STAT( rx_align_errors );
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diff changeset
1169 if ( rstat & RHINE_RDES0_LONG ) INCR_STAT( rx_too_long_frames );
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diff changeset
1170 #endif // KEEP_STATISTICS
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diff changeset
1171
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diff changeset
1172 if (RHINE_RDES0_RXOK & rstat) {
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parents:
diff changeset
1173 // It's OK
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diff changeset
1174 INCR_STAT( rx_good );
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diff changeset
1175
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diff changeset
1176 #if DEBUG & 1
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diff changeset
1177 diag_printf("RxEvent good rx - stat: 0x%08x, len: 0x%04x\n", rstat, len);
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diff changeset
1178 {
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diff changeset
1179 unsigned char *buf = cpd->rx_buffers + cpd->rxpacket*_BUF_SIZE;
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diff changeset
1180
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diff changeset
1181 int i;
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diff changeset
1182 diag_printf("RDES: %08x %08x %08x %08x\n",
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diff changeset
1183 _SU32(rxd, RHINE_RDES0), _SU32(rxd, RHINE_RDES1),
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diff changeset
1184 _SU32(rxd, RHINE_RDES2), _SU32(rxd, RHINE_RDES3));
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diff changeset
1185
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diff changeset
1186 diag_printf("Packet data at %p\n", buf);
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diff changeset
1187 for (i=0;i<len;i++) diag_printf("%02x ", buf[i]);
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diff changeset
1188 diag_printf("\n");
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diff changeset
1189 }
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diff changeset
1190 #endif
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diff changeset
1191 // Check for bogusly short packets; can happen in promisc
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diff changeset
1192 // mode: Asserted against and checked by upper layer
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diff changeset
1193 // driver.
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diff changeset
1194 #ifdef CYGPKG_NET
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diff changeset
1195 if ( len > sizeof( struct ether_header ) )
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diff changeset
1196 // then it is acceptable; offer the data to the network stack
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diff changeset
1197 #endif
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diff changeset
1198 (sc->funs->eth_drv->recv)(sc, len);
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diff changeset
1199 } else {
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diff changeset
1200 // Not OK for one reason or another...
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diff changeset
1201 #if DEBUG & 1
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diff changeset
1202 diag_printf("RxEvent - No RX bit: stat: 0x%08x, len: 0x%04x\n",
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diff changeset
1203 rstat, len);
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diff changeset
1204 #endif
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diff changeset
1205 }
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diff changeset
1206
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diff changeset
1207 // Free packet (clear all status flags, and set OWN)
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diff changeset
1208 _SU32(rxd, RHINE_RDES0) = RHINE_RDES0_OWN;
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jlarmour
parents:
diff changeset
1209 }
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diff changeset
1210
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diff changeset
1211 // Ack RX int
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diff changeset
1212 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, RHINE_ISR_PRX);
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diff changeset
1213 // And reenable the interrupt
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diff changeset
1214 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_IMR, mask);
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diff changeset
1215 mask |= RHINE_IMR_PRX;
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diff changeset
1216 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_IMR, mask);
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jlarmour
parents:
diff changeset
1217 }
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diff changeset
1218
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jlarmour
parents:
diff changeset
1219 //
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jlarmour
parents:
diff changeset
1220 // This function is called as a result of the "eth_drv_recv()" call above.
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parents:
diff changeset
1221 // Its job is to actually fetch data for a packet from the hardware once
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jlarmour
parents:
diff changeset
1222 // memory buffers have been allocated for the packet. Note that the buffers
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diff changeset
1223 // may come in pieces, using a scatter-gather list. This allows for more
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jlarmour
parents:
diff changeset
1224 // efficient processing in the upper layers of the stack.
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jlarmour
parents:
diff changeset
1225 //
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jlarmour
parents:
diff changeset
1226 static void
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diff changeset
1227 rhine_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
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parents:
diff changeset
1228 {
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parents:
diff changeset
1229 struct rhine_priv_data *cpd =
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diff changeset
1230 (struct rhine_priv_data *)sc->driver_private;
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diff changeset
1231 int i, mlen=0, plen;
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1232 cyg_uint8 *data, *rxd, *buf;
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diff changeset
1233
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1234 DEBUG_FUNCTION();
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1235
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1236 rxd = cpd->rx_ring + cpd->rxpacket*RHINE_RD_SIZE;
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1237 buf = cpd->rx_buffers + cpd->rxpacket*_BUF_SIZE;
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diff changeset
1238
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1239 INCR_STAT( rx_deliver );
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diff changeset
1240
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1241 plen = (_SU32(rxd, RHINE_RDES0) & RHINE_RDES0_FLNG_mask) >> RHINE_RDES0_FLNG_shift;
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1242
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1243 for (i = 0; i < sg_len; i++) {
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1244 data = (cyg_uint8*)sg_list[i].buf;
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diff changeset
1245 mlen = sg_list[i].len;
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diff changeset
1246
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diff changeset
1247 #if DEBUG & 1
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diff changeset
1248 diag_printf("%s : mlen %x, plen %x\n", __FUNCTION__, mlen, plen);
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diff changeset
1249 #endif
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diff changeset
1250 if (data) {
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diff changeset
1251 while (mlen > 0) {
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diff changeset
1252 *data++ = *buf++;
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diff changeset
1253 mlen--;
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diff changeset
1254 plen--;
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diff changeset
1255 }
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diff changeset
1256 }
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diff changeset
1257 }
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diff changeset
1258 }
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diff changeset
1259
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diff changeset
1260 static void
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diff changeset
1261 rhine_poll(struct eth_drv_sc *sc)
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jlarmour
parents:
diff changeset
1262 {
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diff changeset
1263 struct rhine_priv_data *cpd =
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diff changeset
1264 (struct rhine_priv_data *)sc->driver_private;
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diff changeset
1265 cyg_uint16 event, mask;
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diff changeset
1266 static volatile bool locked = false;
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diff changeset
1267
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diff changeset
1268 // DEBUG_FUNCTION();
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diff changeset
1269
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diff changeset
1270 while (1) {
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diff changeset
1271 // Get the (unmasked) requests
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diff changeset
1272 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_ISR, event);
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diff changeset
1273 HAL_PCI_IO_READ_UINT16(cpd->base + RHINE_IMR, mask);
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diff changeset
1274
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diff changeset
1275 event &= mask;
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diff changeset
1276
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diff changeset
1277 if (0 == event)
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parents:
diff changeset
1278 break;
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diff changeset
1279
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diff changeset
1280 if (event & RHINE_ISR_PRX) {
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diff changeset
1281 rhine_RxEvent(sc);
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diff changeset
1282 }
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diff changeset
1283 else if (event & RHINE_ISR_PTX) {
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diff changeset
1284 rhine_TxEvent(sc, event);
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parents:
diff changeset
1285 }
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diff changeset
1286 else if (event & RHINE_ISR_RU) {
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parents:
diff changeset
1287 #if DEBUG & 1
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diff changeset
1288 int i;
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parents:
diff changeset
1289 cyg_uint32 rstat;
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diff changeset
1290 cyg_uint8* rxd;
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diff changeset
1291 struct rhine_priv_data *cpd =
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diff changeset
1292 (struct rhine_priv_data *)sc->driver_private;
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diff changeset
1293
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diff changeset
1294 diag_printf("%s: Ran out of RX buffers (%04x)\n", __FUNCTION__, event);
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diff changeset
1295 for (i = 0; i < cpd->rx_ring_cnt; i++) {
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diff changeset
1296 rxd = cpd->rx_ring + i*RHINE_RD_SIZE;
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diff changeset
1297
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diff changeset
1298 rstat = _SU32(rxd, RHINE_RDES0);
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diff changeset
1299 diag_printf(" %02d: 0x%08x\n", i, rstat);
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diff changeset
1300 }
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diff changeset
1301 #endif
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diff changeset
1302 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, RHINE_ISR_RU);
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jlarmour
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diff changeset
1303 }
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diff changeset
1304 else {
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diff changeset
1305 #if DEBUG & 1
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diff changeset
1306 diag_printf("%s: Unknown interrupt: 0x%04x\n", __FUNCTION__, event);
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jlarmour
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diff changeset
1307 #endif
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jlarmour
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diff changeset
1308 // Clear unhandled interrupts and hope for the best
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jlarmour
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diff changeset
1309 // This should never happen though, since we only enable
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jlarmour
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diff changeset
1310 // the sources we handle.
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diff changeset
1311 HAL_PCI_IO_WRITE_UINT16(cpd->base + RHINE_ISR, event);
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jlarmour
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diff changeset
1312 }
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jlarmour
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diff changeset
1313 }
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diff changeset
1314
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jlarmour
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diff changeset
1315 locked = false;
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jlarmour
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diff changeset
1316 }
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jlarmour
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diff changeset
1317 // EOF if_rhine.c