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annotate packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents 0d2b193a635f
children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // io/serial/generic/16x5x/ser_16x5x.c
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4 //
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5 // Generic 16x5x serial driver
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6 //
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7 //==========================================================================
208
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): gthomas
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44 // Contributors: gthomas, jlarmour, jskov
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45 // Date: 1999-02-04
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46 // Purpose: 16x5x generic serial driver
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47 // Description:
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #include <pkgconf/system.h>
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54 #include <pkgconf/io_serial.h>
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55 #include <pkgconf/io.h>
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56
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57 #include <cyg/io/io.h>
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58 #include <cyg/hal/hal_intr.h>
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59 #include <cyg/io/devtab.h>
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60 #include <cyg/io/serial.h>
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61 #include <cyg/infra/diag.h>
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62 #include <cyg/infra/cyg_ass.h>
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63 #include <cyg/hal/hal_io.h>
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64
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65 // Only compile driver if an inline file with driver details was selected.
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66 #ifdef CYGDAT_IO_SERIAL_GENERIC_16X5X_INL
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67
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68 #ifndef CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP
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69 #define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1
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70 #endif
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71
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72 #define SER_REG(_x_) ((_x_)*CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP)
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73
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74 // Receive control Registers
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75 #define REG_rhr SER_REG(0) // Receive holding register
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76 #define REG_isr SER_REG(2) // Interrupt status register
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77 #define REG_lsr SER_REG(5) // Line status register
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78 #define REG_msr SER_REG(6) // Modem status register
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79 #define REG_scr SER_REG(7) // Scratch register
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80
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81 // Transmit control Registers
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82 #define REG_thr SER_REG(0) // Transmit holding register
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83 #define REG_ier SER_REG(1) // Interrupt enable register
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84 #define REG_fcr SER_REG(2) // FIFO control register
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85 #define REG_lcr SER_REG(3) // Line control register
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86 #define REG_mcr SER_REG(4) // Modem control register
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87 #define REG_ldl SER_REG(0) // LSB of baud rate
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88 #define REG_mdl SER_REG(1) // MSB of baud rate
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89
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90 // Interrupt Enable Register
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91 #define IER_RCV 0x01
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92 #define IER_XMT 0x02
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93 #define IER_LS 0x04
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94 #define IER_MS 0x08
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95
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96 // Line Control Register
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97 #define LCR_WL5 0x00 // Word length
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98 #define LCR_WL6 0x01
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99 #define LCR_WL7 0x02
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100 #define LCR_WL8 0x03
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101 #define LCR_SB1 0x00 // Number of stop bits
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102 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
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103 #define LCR_SB2 0x04
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104 #define LCR_PN 0x00 // Parity mode - none
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105 #define LCR_PE 0x18 // Parity mode - even
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106 #define LCR_PO 0x08 // Parity mode - odd
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107 #define LCR_PM 0x28 // Forced "mark" parity
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108 #define LCR_PS 0x38 // Forced "space" parity
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109 #define LCR_DL 0x80 // Enable baud rate latch
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110
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111 // Line Status Register
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112 #define LSR_RSR 0x01
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113 #define LSR_OE 0x02
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114 #define LSR_PE 0x04
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115 #define LSR_FE 0x08
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116 #define LSR_BI 0x10
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117 #define LSR_THE 0x20
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118 #define LSR_TEMT 0x40
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119 #define LSR_FIE 0x80
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120
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121 // Modem Control Register
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122 #define MCR_DTR 0x01
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123 #define MCR_RTS 0x02
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124 #define MCR_INT 0x08 // Enable interrupts
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125 #define MCR_LOOP 0x10 // Loopback mode
126
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126
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127 // Interrupt status Register
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128 #define ISR_MS 0x00
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129 #define ISR_nIP 0x01
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130 #define ISR_Tx 0x02
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131 #define ISR_Rx 0x04
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132 #define ISR_LS 0x06
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133 #define ISR_RxTO 0x0C
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134 #define ISR_64BFIFO 0x20
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135 #define ISR_FIFOworks 0x40
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136 #define ISR_FIFOen 0x80
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137
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138 // Modem Status Register
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139 #define MSR_DCTS 0x01
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140 #define MSR_DDSR 0x02
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141 #define MSR_TERI 0x04
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142 #define MSR_DDCD 0x08
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143 #define MSR_CTS 0x10
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144 #define MSR_DSR 0x20
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145 #define MSR_RI 0x40
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146 #define MSR_CD 0x80
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147
145
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148 // FIFO Control Register
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149 #define FCR_FE 0x01 // FIFO enable
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150 #define FCR_CRF 0x02 // Clear receive FIFO
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151 #define FCR_CTF 0x04 // Clear transmit FIFO
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152 #define FCR_DMA 0x08 // DMA mode select
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153 #define FCR_F64 0x20 // Enable 64 byte fifo (16750+)
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154 #define FCR_RT14 0xC0 // Set Rx trigger at 14
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155 #define FCR_RT8 0x80 // Set Rx trigger at 8
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156 #define FCR_RT4 0x40 // Set Rx trigger at 4
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157 #define FCR_RT1 0x00 // Set Rx trigger at 1
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158
126
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159 static unsigned char select_word_length[] = {
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160 LCR_WL5, // 5 bits / word (char)
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161 LCR_WL6,
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162 LCR_WL7,
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163 LCR_WL8
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164 };
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165
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166 static unsigned char select_stop_bits[] = {
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167 0,
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168 LCR_SB1, // 1 stop bit
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169 LCR_SB1_5, // 1.5 stop bit
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170 LCR_SB2 // 2 stop bits
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171 };
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172
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173 static unsigned char select_parity[] = {
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174 LCR_PN, // No parity
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175 LCR_PE, // Even parity
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176 LCR_PO, // Odd parity
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177 LCR_PM, // Mark parity
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178 LCR_PS, // Space parity
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179 };
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180
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181 // selec_baud[] must be define by the client
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182
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183 typedef struct pc_serial_info {
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184 cyg_addrword_t base;
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185 int int_num;
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186 cyg_interrupt serial_interrupt;
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187 cyg_handle_t serial_interrupt_handle;
161
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188 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
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189 enum {
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190 sNone = 0,
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191 s8250,
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192 s16450,
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193 s16550,
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194 s16550a
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195 } deviceType;
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196 #endif
126
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197 } pc_serial_info;
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198
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199 static bool pc_serial_init(struct cyg_devtab_entry *tab);
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200 static bool pc_serial_putc(serial_channel *chan, unsigned char c);
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201 static Cyg_ErrNo pc_serial_lookup(struct cyg_devtab_entry **tab,
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202 struct cyg_devtab_entry *sub_tab,
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203 const char *name);
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204 static unsigned char pc_serial_getc(serial_channel *chan);
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205 static Cyg_ErrNo pc_serial_set_config(serial_channel *chan, cyg_uint32 key,
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206 const void *xbuf, cyg_uint32 *len);
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207 static void pc_serial_start_xmit(serial_channel *chan);
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208 static void pc_serial_stop_xmit(serial_channel *chan);
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209
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210 static cyg_uint32 pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
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211 static void pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count,
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212 cyg_addrword_t data);
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213
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214 static SERIAL_FUNS(pc_serial_funs,
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215 pc_serial_putc,
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216 pc_serial_getc,
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217 pc_serial_set_config,
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218 pc_serial_start_xmit,
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219 pc_serial_stop_xmit
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220 );
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221
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222 #include CYGDAT_IO_SERIAL_GENERIC_16X5X_INL
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223
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224 // Internal function to actually configure the hardware to desired
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225 // baud rate, etc.
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226 static bool
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227 serial_config_port(serial_channel *chan,
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228 cyg_serial_info_t *new_config, bool init)
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229 {
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230 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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231 cyg_addrword_t base = ser_chan->base;
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232 unsigned short baud_divisor = select_baud[new_config->baud];
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233 unsigned char _lcr, _ier;
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234 if (baud_divisor == 0) return false; // Invalid configuration
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235
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236 // Disable port interrupts while changing hardware
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237 HAL_READ_UINT8(base+REG_ier, _ier);
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238 HAL_WRITE_UINT8(base+REG_ier, 0);
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239
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240 _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
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241 select_stop_bits[new_config->stop] |
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242 select_parity[new_config->parity];
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243 HAL_WRITE_UINT8(base+REG_lcr, _lcr | LCR_DL);
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244 HAL_WRITE_UINT8(base+REG_mdl, baud_divisor >> 8);
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245 HAL_WRITE_UINT8(base+REG_ldl, baud_divisor & 0xFF);
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246 HAL_WRITE_UINT8(base+REG_lcr, _lcr);
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247 if (init) {
156
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248 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
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249 unsigned char _fcr_thresh;
161
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250 cyg_uint8 b;
156
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251
161
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252 /* First, find out what kind of device it is. */
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253 ser_chan->deviceType = sNone;
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254 HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP); // enable loopback mode
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255 HAL_READ_UINT8(base+REG_msr, b);
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256 if (0 == (b & 0xF0)) { // see if MSR had CD, RI, DSR or CTS set
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257 HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP|MCR_DTR|MCR_RTS);
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258 HAL_READ_UINT8(base+REG_msr, b);
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259 if (0xF0 != (b & 0xF0)) // check that all of CD,RI,DSR and CTS set
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260 ser_chan->deviceType = s8250;
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261 }
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262 HAL_WRITE_UINT8(base+REG_mcr, 0); // disable loopback mode
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263
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264 if (ser_chan->deviceType == s8250) {
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265 // Check for a scratch register; scratch register
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266 // indicates 16450 or above.
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267 HAL_WRITE_UINT8(base+REG_scr, 0x55);
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268 HAL_READ_UINT8(base+REG_scr, b);
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269 if (b == 0x55) {
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270 HAL_WRITE_UINT8(base+REG_scr, 0xAA);
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271 HAL_READ_UINT8(base+REG_scr, b);
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272 if (b == 0xAA)
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273 ser_chan->deviceType = s16450;
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274 }
156
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275 }
161
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276
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277 if (ser_chan->deviceType == s16450) {
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278 // Check for a FIFO
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279 HAL_WRITE_UINT8(base+REG_fcr, FCR_FE);
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280 HAL_READ_UINT8(base+REG_isr, b);
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281 if (b & ISR_FIFOen)
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282 ser_chan->deviceType = s16550; // but FIFO doesn't
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283 // necessarily work
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284 if (b & ISR_FIFOworks)
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285 ser_chan->deviceType = s16550a; // 16550a FIFOs work
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286 }
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287
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288 if (ser_chan->deviceType == s16550a) {
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289 switch(CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD) {
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290 default:
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291 case 1:
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292 _fcr_thresh=FCR_RT1; break;
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293 case 4:
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294 _fcr_thresh=FCR_RT4; break;
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295 case 8:
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296 _fcr_thresh=FCR_RT8; break;
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297 case 14:
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298 _fcr_thresh=FCR_RT14; break;
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299 }
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300 _fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF;
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301 HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh); // Enable and clear FIFO
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302 }
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303 else
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304 HAL_WRITE_UINT8(base+REG_fcr, 0); // make sure it's disabled
156
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305 #endif
126
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306 if (chan->out_cbuf.len != 0) {
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307 _ier = IER_RCV;
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308 } else {
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309 _ier = 0;
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310 }
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311 // Master interrupt enable
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312 HAL_WRITE_UINT8(base+REG_mcr, MCR_INT|MCR_DTR|MCR_RTS);
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313 }
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314 #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS
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315 _ier |= (IER_LS|IER_MS);
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316 #endif
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317 HAL_WRITE_UINT8(base+REG_ier, _ier);
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318
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319 if (new_config != &chan->config) {
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320 chan->config = *new_config;
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321 }
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322 return true;
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323 }
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324
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325 // Function to initialize the device. Called at bootstrap time.
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326 static bool
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327 pc_serial_init(struct cyg_devtab_entry *tab)
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328 {
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329 serial_channel *chan = (serial_channel *)tab->priv;
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330 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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331 #ifdef CYGDBG_IO_INIT
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332 diag_printf("16x5x SERIAL init - dev: %x.%d\n",
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333 ser_chan->base, ser_chan->int_num);
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334 #endif
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335 // Really only required for interrupt driven devices
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336 (chan->callbacks->serial_init)(chan);
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337
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338 if (chan->out_cbuf.len != 0) {
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339 cyg_drv_interrupt_create(ser_chan->int_num,
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340 99,
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341 (cyg_addrword_t)chan,
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342 pc_serial_ISR,
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343 pc_serial_DSR,
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344 &ser_chan->serial_interrupt_handle,
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345 &ser_chan->serial_interrupt);
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346 cyg_drv_interrupt_attach(ser_chan->serial_interrupt_handle);
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347 cyg_drv_interrupt_unmask(ser_chan->int_num);
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348 }
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349 serial_config_port(chan, &chan->config, true);
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350 return true;
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351 }
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352
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353 // This routine is called when the device is "looked" up (i.e. attached)
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354 static Cyg_ErrNo
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355 pc_serial_lookup(struct cyg_devtab_entry **tab,
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356 struct cyg_devtab_entry *sub_tab,
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357 const char *name)
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358 {
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359 serial_channel *chan = (serial_channel *)(*tab)->priv;
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360
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361 // Really only required for interrupt driven devices
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362 (chan->callbacks->serial_init)(chan);
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363 return ENOERR;
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364 }
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365
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366 // Send a character to the device output buffer.
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367 // Return 'true' if character is sent to device
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368 static bool
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369 pc_serial_putc(serial_channel *chan, unsigned char c)
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370 {
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371 cyg_uint8 _lsr;
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372 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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373 cyg_addrword_t base = ser_chan->base;
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374
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375 HAL_READ_UINT8(base+REG_lsr, _lsr);
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376 if (_lsr & LSR_THE) {
161
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377 // Transmit buffer is empty
126
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378 HAL_WRITE_UINT8(base+REG_thr, c);
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379 return true;
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380 }
161
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381 // No space
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382 return false;
126
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383 }
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384
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385 // Fetch a character from the device input buffer, waiting if necessary
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386 static unsigned char
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387 pc_serial_getc(serial_channel *chan)
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388 {
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389 unsigned char c;
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390 cyg_uint8 _lsr;
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391 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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392 cyg_addrword_t base = ser_chan->base;
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393
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394 // Wait for char
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395 do {
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396 HAL_READ_UINT8(base+REG_lsr, _lsr);
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397 } while ((_lsr & LSR_RSR) == 0);
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398
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399 HAL_READ_UINT8(base+REG_rhr, c);
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400 return c;
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401 }
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402
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403 // Set up the device characteristics; baud rate, etc.
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404 static Cyg_ErrNo
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405 pc_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf,
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406 cyg_uint32 *len)
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407 {
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408 switch (key) {
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409 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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410 {
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411 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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412 if ( *len < sizeof(cyg_serial_info_t) ) {
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413 return -EINVAL;
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414 }
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415 *len = sizeof(cyg_serial_info_t);
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416 if ( true != serial_config_port(chan, config, false) )
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417 return -EINVAL;
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418 }
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419 break;
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420 #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW
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421 case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE:
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422 {
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423 cyg_uint8 _mcr;
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424 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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425 cyg_addrword_t base = ser_chan->base;
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426 cyg_uint8 *f = (cyg_uint8 *)xbuf;
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427 unsigned char mask=0;
163
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parents: 161
diff changeset
428 if ( *len < sizeof(*f) )
126
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parents:
diff changeset
429 return -EINVAL;
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jlarmour
parents:
diff changeset
430
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jlarmour
parents:
diff changeset
431 if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX )
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parents:
diff changeset
432 mask = MCR_RTS;
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parents:
diff changeset
433 if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX )
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jlarmour
parents:
diff changeset
434 mask |= MCR_DTR;
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jlarmour
parents:
diff changeset
435 HAL_READ_UINT8(base+REG_mcr, _mcr);
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jlarmour
parents:
diff changeset
436 if (*f) // we should throttle
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jlarmour
parents:
diff changeset
437 _mcr &= ~mask;
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jlarmour
parents:
diff changeset
438 else // we should no longer throttle
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jlarmour
parents:
diff changeset
439 _mcr |= mask;
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jlarmour
parents:
diff changeset
440 HAL_WRITE_UINT8(base+REG_mcr, _mcr);
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parents:
diff changeset
441 }
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jlarmour
parents:
diff changeset
442 break;
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jlarmour
parents:
diff changeset
443 case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG:
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jlarmour
parents:
diff changeset
444 // Nothing to do because we do support both RTSCTS and DSRDTR flow
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jlarmour
parents:
diff changeset
445 // control.
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jlarmour
parents:
diff changeset
446 // Other targets would clear any unsupported flags here.
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jlarmour
parents:
diff changeset
447 // We just return ENOERR.
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jlarmour
parents:
diff changeset
448 break;
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jlarmour
parents:
diff changeset
449 #endif
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jlarmour
parents:
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450 default:
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parents:
diff changeset
451 return -EINVAL;
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parents:
diff changeset
452 }
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parents:
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453 return ENOERR;
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jlarmour
parents:
diff changeset
454 }
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jlarmour
parents:
diff changeset
455
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jlarmour
parents:
diff changeset
456 // Enable the transmitter on the device
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jlarmour
parents:
diff changeset
457 static void
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jlarmour
parents:
diff changeset
458 pc_serial_start_xmit(serial_channel *chan)
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parents:
diff changeset
459 {
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diff changeset
460 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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461 cyg_addrword_t base = ser_chan->base;
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parents:
diff changeset
462 cyg_uint8 _ier;
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parents:
diff changeset
463
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diff changeset
464 HAL_READ_UINT8(base+REG_ier, _ier);
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465 _ier |= IER_XMT; // Enable xmit interrupt
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466 HAL_WRITE_UINT8(base+REG_ier, _ier);
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jlarmour
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diff changeset
467 }
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parents:
diff changeset
468
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jlarmour
parents:
diff changeset
469 // Disable the transmitter on the device
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jlarmour
parents:
diff changeset
470 static void
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jlarmour
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diff changeset
471 pc_serial_stop_xmit(serial_channel *chan)
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diff changeset
472 {
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473 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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474 cyg_addrword_t base = ser_chan->base;
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parents:
diff changeset
475 cyg_uint8 _ier;
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jlarmour
parents:
diff changeset
476
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jlarmour
parents:
diff changeset
477 HAL_READ_UINT8(base+REG_ier, _ier);
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478 _ier &= ~IER_XMT; // Disable xmit interrupt
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479 HAL_WRITE_UINT8(base+REG_ier, _ier);
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parents:
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480 }
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jlarmour
parents:
diff changeset
481
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jlarmour
parents:
diff changeset
482 // Serial I/O - low level interrupt handler (ISR)
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jlarmour
parents:
diff changeset
483 static cyg_uint32
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diff changeset
484 pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
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parents:
diff changeset
485 {
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jlarmour
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diff changeset
486 serial_channel *chan = (serial_channel *)data;
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diff changeset
487 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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diff changeset
488 cyg_drv_interrupt_mask(ser_chan->int_num);
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jlarmour
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489 cyg_drv_interrupt_acknowledge(ser_chan->int_num);
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diff changeset
490 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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diff changeset
491 }
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jlarmour
parents:
diff changeset
492
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jlarmour
parents:
diff changeset
493 // Serial I/O - high level interrupt handler (DSR)
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jlarmour
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diff changeset
494 static void
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jlarmour
parents:
diff changeset
495 pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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jlarmour
parents:
diff changeset
496 {
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497 serial_channel *chan = (serial_channel *)data;
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diff changeset
498 pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
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jlarmour
parents:
diff changeset
499 cyg_addrword_t base = ser_chan->base;
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jlarmour
parents:
diff changeset
500 cyg_uint8 _isr;
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jlarmour
parents:
diff changeset
501
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jlarmour
parents:
diff changeset
502 // Check if we have an interrupt pending - note that the interrupt
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jlarmour
parents:
diff changeset
503 // is pending of the low bit of the isr is *0*, not 1.
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jlarmour
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diff changeset
504 HAL_READ_UINT8(base+REG_isr, _isr);
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jlarmour
parents:
diff changeset
505 while ((_isr & ISR_nIP) == 0) {
150
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parents: 145
diff changeset
506 switch (_isr&0xE) {
126
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jlarmour
parents:
diff changeset
507 case ISR_Rx:
150
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parents: 145
diff changeset
508 case ISR_RxTO:
126
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jlarmour
parents:
diff changeset
509 {
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jlarmour
parents:
diff changeset
510 cyg_uint8 _lsr;
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jlarmour
parents:
diff changeset
511 unsigned char c;
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diff changeset
512 HAL_READ_UINT8(base+REG_lsr, _lsr);
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jlarmour
parents:
diff changeset
513 while(_lsr & LSR_RSR) {
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jlarmour
parents:
diff changeset
514 HAL_READ_UINT8(base+REG_rhr, c);
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jlarmour
parents:
diff changeset
515 (chan->callbacks->rcv_char)(chan, c);
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jlarmour
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diff changeset
516 HAL_READ_UINT8(base+REG_lsr, _lsr);
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jlarmour
parents:
diff changeset
517 }
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parents:
diff changeset
518 break;
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jlarmour
parents:
diff changeset
519 }
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jlarmour
parents:
diff changeset
520 case ISR_Tx:
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jlarmour
parents:
diff changeset
521 (chan->callbacks->xmt_char)(chan);
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jlarmour
parents:
diff changeset
522 break;
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jlarmour
parents:
diff changeset
523
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jlarmour
parents:
diff changeset
524 #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS
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jlarmour
parents:
diff changeset
525 case ISR_LS:
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jlarmour
parents:
diff changeset
526 {
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jlarmour
parents:
diff changeset
527 cyg_serial_line_status_t stat;
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jlarmour
parents:
diff changeset
528 cyg_uint8 _lsr;
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jlarmour
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diff changeset
529 HAL_READ_UINT8(base+REG_lsr, _lsr);
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jlarmour
parents:
diff changeset
530
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jlarmour
parents:
diff changeset
531 // this might look expensive, but it is rarely the case that
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jlarmour
parents:
diff changeset
532 // more than one of these is set
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jlarmour
parents:
diff changeset
533 stat.value = 1;
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jlarmour
parents:
diff changeset
534 if ( _lsr & LSR_OE ) {
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jlarmour
parents:
diff changeset
535 stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR;
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jlarmour
parents:
diff changeset
536 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
537 }
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jlarmour
parents:
diff changeset
538 if ( _lsr & LSR_PE ) {
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jlarmour
parents:
diff changeset
539 stat.which = CYGNUM_SERIAL_STATUS_PARITYERR;
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jlarmour
parents:
diff changeset
540 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
541 }
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jlarmour
parents:
diff changeset
542 if ( _lsr & LSR_FE ) {
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jlarmour
parents:
diff changeset
543 stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR;
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jlarmour
parents:
diff changeset
544 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
545 }
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jlarmour
parents:
diff changeset
546 if ( _lsr & LSR_BI ) {
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jlarmour
parents:
diff changeset
547 stat.which = CYGNUM_SERIAL_STATUS_BREAK;
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jlarmour
parents:
diff changeset
548 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
549 }
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jlarmour
parents:
diff changeset
550 }
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jlarmour
parents:
diff changeset
551 break;
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jlarmour
parents:
diff changeset
552
518f42066aba Merge from eCos master repository on 2000-09-19-06:25:26-BST
jlarmour
parents:
diff changeset
553 case ISR_MS:
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jlarmour
parents:
diff changeset
554 {
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jlarmour
parents:
diff changeset
555 cyg_serial_line_status_t stat;
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jlarmour
parents:
diff changeset
556 cyg_uint8 _msr;
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jlarmour
parents:
diff changeset
557
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jlarmour
parents:
diff changeset
558 HAL_READ_UINT8(base+REG_msr, _msr);
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jlarmour
parents:
diff changeset
559 #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW
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jlarmour
parents:
diff changeset
560 if ( _msr & MSR_DDSR )
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jlarmour
parents:
diff changeset
561 if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_TX ) {
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jlarmour
parents:
diff changeset
562 stat.which = CYGNUM_SERIAL_STATUS_FLOW;
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jlarmour
parents:
diff changeset
563 stat.value = (0 != (_msr & MSR_DSR));
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jlarmour
parents:
diff changeset
564 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
565 }
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jlarmour
parents:
diff changeset
566 if ( _msr & MSR_DCTS )
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jlarmour
parents:
diff changeset
567 if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX ) {
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jlarmour
parents:
diff changeset
568 stat.which = CYGNUM_SERIAL_STATUS_FLOW;
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jlarmour
parents:
diff changeset
569 stat.value = (0 != (_msr & MSR_CTS));
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jlarmour
parents:
diff changeset
570 (chan->callbacks->indicate_status)(chan, &stat );
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jlarmour
parents:
diff changeset
571 }
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jlarmour
parents:
diff changeset
572 #endif
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jlarmour
parents:
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573 if ( _msr & MSR_DDCD ) {
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574 stat.which = CYGNUM_SERIAL_STATUS_CARRIERDETECT;
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575 stat.value = (0 != (_msr & MSR_CD));
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576 (chan->callbacks->indicate_status)(chan, &stat );
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577 }
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578 if ( _msr & MSR_RI ) {
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579 stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR;
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580 stat.value = 1;
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581 (chan->callbacks->indicate_status)(chan, &stat );
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582 }
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583 if ( _msr & MSR_TERI ) {
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584 stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR;
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585 stat.value = 0;
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586 (chan->callbacks->indicate_status)(chan, &stat );
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587 }
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588 }
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589 break;
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590 #endif
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591 default:
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592 // Yes, this assertion may well not be visible. *But*
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593 // if debugging, we may still successfully hit a breakpoint
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594 // on cyg_assert_fail, which _is_ useful
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595 CYG_FAIL("unhandled serial interrupt state");
126
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596 }
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597
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598 HAL_READ_UINT8(base+REG_isr, _isr);
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599 } // while
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600
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601 cyg_drv_interrupt_unmask(ser_chan->int_num);
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602 }
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603 #endif
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604
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605 // EOF ser_16x5x.c