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annotate packages/devs/serial/h8300/h8300h/current/src/h8300_sci_serial.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // h8300_sci_serial.c
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4 //
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5 // H8/300 Serial SCI I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): jskov
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44 // Contributors:gthomas, jskov
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45 // Date: 1999-05-24
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46 // Purpose: H8/300 Serial I/O module (interrupt driven version)
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47 // Description:
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48 //
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49 // Note: Since interrupt sources from the same SCI channel share the same
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50 // interrupt level, there is no risk of races when altering the
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51 // channel's control register from ISRs and DSRs. However, when
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52 // altering the control register from user-level code, interrupts
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53 // must be disabled while the register is being accessed.
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54 //
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55 // FIXME: Receiving in polled mode prevents duplex transfers from working for
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56 // some reason.
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57 //####DESCRIPTIONEND####
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58 //==========================================================================
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59
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60 #include <pkgconf/io_serial.h>
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61 #include <pkgconf/io.h>
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62
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63 // FIXME: This is necessary since the SCIF driver may be overriding
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64 // CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two
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65 // different drivers.
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66 #include <pkgconf/io_serial_h8300_sci.h>
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67
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68 #include <cyg/io/io.h>
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69 #include <cyg/hal/hal_intr.h>
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70 #include <cyg/io/devtab.h>
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71 #include <cyg/infra/diag.h>
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72 #include <cyg/io/serial.h>
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73
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74 #ifdef CYGDAT_IO_SERIAL_H8300_SCI
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75 // The SCI controller register layout on the SH3/7708.
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76 #define SCI_SCSMR 0 // serial mode register
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77 #define SCI_SCBRR 1 // bit rate register
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78 #define SCI_SCSCR 2 // serial control register
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79 #define SCI_SCTDR 3 // transmit data register
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80 #define SCI_SCSSR 4 // serial status register
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81 #define SCI_SCRDR 5 // receive data register
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82 #define SCI_SCSPTR -4 // serial port register
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83
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84 static short select_word_length[] = {
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85 -1,
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86 -1,
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87 CYGARC_REG_SCSMR_CHR, // 7 bits
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88 0 // 8 bits
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89 };
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90
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91 static short select_stop_bits[] = {
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92 -1,
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93 0, // 1 stop bit
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94 -1,
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95 CYGARC_REG_SCSMR_STOP // 2 stop bits
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96 };
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97
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98 static short select_parity[] = {
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99 0, // No parity
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100 CYGARC_REG_SCSMR_PE, // Even parity
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101 CYGARC_REG_SCSMR_PE|CYGARC_REG_SCSMR_OE, // Odd parity
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102 -1,
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103 -1
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104 };
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105
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106 static unsigned short select_baud[] = {
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107 0, // Unused
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108 CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
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109 CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
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110 CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
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111 CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
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112 CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
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113 CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
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114 CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
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115 CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
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116 CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
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117 CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
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118 CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
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119 CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
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120 CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
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121 CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
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122 CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
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123 CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
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124 CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),
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125 CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),
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126 CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),
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127 CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),
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128 CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)
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129 };
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130
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131
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132 typedef struct h8300_sci_info {
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133 CYG_ADDRWORD data; // Pointer to data register
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134
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135 CYG_WORD er_int_num, // Error interrupt number
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136 rx_int_num, // Receive interrupt number
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137 tx_int_num; // Transmit interrupt number
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138
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139 CYG_ADDRWORD ctrl_base; // Base address of SCI controller
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140
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141 cyg_interrupt serial_er_interrupt,
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142 serial_rx_interrupt,
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143 serial_tx_interrupt;
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144 cyg_handle_t serial_er_interrupt_handle,
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145 serial_rx_interrupt_handle,
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146 serial_tx_interrupt_handle;
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147
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148 bool tx_enabled;
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149 } sh_sci_info;
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150
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151 static bool h8300_serial_init(struct cyg_devtab_entry *tab);
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152 static bool h8300_serial_putc(serial_channel *chan, unsigned char c);
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153 static Cyg_ErrNo h8300_serial_lookup(struct cyg_devtab_entry **tab,
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154 struct cyg_devtab_entry *sub_tab,
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155 const char *name);
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156 static unsigned char h8300_serial_getc(serial_channel *chan);
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157 static Cyg_ErrNo h8300_serial_set_config(serial_channel *chan, cyg_uint32 key,
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158 const void *xbuf, cyg_uint32 *len);
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159 static void h8300_serial_start_xmit(serial_channel *chan);
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160 static void h8300_serial_stop_xmit(serial_channel *chan);
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161
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162 static cyg_uint32 h8300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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163 static void h8300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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164 cyg_addrword_t data);
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165 static cyg_uint32 h8300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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166 static void h8300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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167 cyg_addrword_t data);
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168 static cyg_uint32 h8300_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data);
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169 static void h8300_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count,
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170 cyg_addrword_t data);
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171
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172 static SERIAL_FUNS(h8300_serial_funs,
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173 h8300_serial_putc,
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174 h8300_serial_getc,
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175 h8300_serial_set_config,
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176 h8300_serial_start_xmit,
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177 h8300_serial_stop_xmit
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178 );
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179
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180
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181 static h8300_sci_info h8300_serial_info =
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182 {
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183 NULL,
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184 CYGNUM_HAL_INTERRUPT_ERI0,
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185 CYGNUM_HAL_INTERRUPT_RXI0,
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186 CYGNUM_HAL_INTERRUPT_TXI0,
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187 CYGARC_REG_SMR0
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188 };
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189
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190 #if CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BUFSIZE > 0
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191 static unsigned char h8300_serial_out_buf[CYGNUM_IO_SERIAL_H8300_CQ7708_SERIAL1_BUFSIZE];
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192 static unsigned char h8300_serial_in_buf[CYGNUM_IO_SERIAL_H8300_CQ7708_SERIAL1_BUFSIZE];
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193
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194 static SERIAL_CHANNEL_USING_INTERRUPTS(h8300_serial_channel,
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195 h8300_serial_funs,
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196 h8300_serial_info,
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197 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BAUD),
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198 CYG_SERIAL_STOP_DEFAULT,
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199 CYG_SERIAL_PARITY_DEFAULT,
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200 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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201 CYG_SERIAL_FLAGS_DEFAULT,
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202 &h8300_serial_out_buf[0],
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203 sizeof(h8300_serial_out_buf),
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204 &h8300_serial_in_buf[0],
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205 sizeof(h8300_serial_in_buf)
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206 );
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207 #else
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208 static SERIAL_CHANNEL(h8300_serial_channel,
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209 h8300_serial_funs,
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210 h8300_serial_info,
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211 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_H8300_H8300H_SERIAL1_BAUD),
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212 CYG_SERIAL_STOP_DEFAULT,
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213 CYG_SERIAL_PARITY_DEFAULT,
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214 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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215 CYG_SERIAL_FLAGS_DEFAULT
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216 );
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217 #endif
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218
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219 DEVTAB_ENTRY(h8300_serial_io,
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220 CYGDAT_IO_SERIAL_H8300_H8300H_SERIAL1_NAME,
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221 0, // Does not depend on a lower level interface
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222 &cyg_io_serial_devio,
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223 h8300_serial_init,
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224 h8300_serial_lookup, // Serial driver may need initializing
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225 &h8300_serial_channel
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226 );
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227
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228 // Internal function to actually configure the hardware to desired baud rate,
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229 // etc.
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230 static bool
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231 h8300_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,
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232 bool init)
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233 {
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234 cyg_uint16 baud_divisor = select_baud[new_config->baud];
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235 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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236 cyg_uint8 _scr, _smr;
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237
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238 // Check configuration request
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239 if ((-1 == select_word_length[(new_config->word_length -
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240 CYGNUM_SERIAL_WORD_LENGTH_5)])
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241 || -1 == select_stop_bits[new_config->stop]
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242 || -1 == select_parity[new_config->parity]
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243 || baud_divisor == 0)
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244 return false;
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245
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246 // Disable SCI interrupts while changing hardware
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247 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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248 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, 0);
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249
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250 // Set databits, stopbits and parity.
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251 _smr = select_word_length[(new_config->word_length -
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252 CYGNUM_SERIAL_WORD_LENGTH_5)] |
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253 select_stop_bits[new_config->stop] |
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254 select_parity[new_config->parity];
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255 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSMR, _smr);
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256
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257 // Set baud rate.
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258 _smr &= ~CYGARC_REG_SCSMR_CKSx_MASK;
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259 _smr |= baud_divisor >> 8;
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260 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSMR, _smr);
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261 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff);
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262
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263 // Clear the status register.
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264 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, 0);
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265
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266 if (init) {
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267 // Always enable transmitter and receiver.
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268 _scr = CYGARC_REG_SCSCR_TE | CYGARC_REG_SCSCR_RE;
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269
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270 if (chan->out_cbuf.len != 0)
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271 _scr |= CYGARC_REG_SCSCR_TIE; // enable tx interrupts
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272
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273 if (chan->in_cbuf.len != 0)
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274 _scr |= CYGARC_REG_SCSCR_RIE; // enable rx interrupts
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275 }
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276
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277 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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278
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279 if (new_config != &chan->config) {
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280 chan->config = *new_config;
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281 }
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282 return true;
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283 }
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284
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285 // Function to initialize the device. Called at bootstrap time.
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286 static bool
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287 h8300_serial_init(struct cyg_devtab_entry *tab)
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288 {
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289 serial_channel *chan = (serial_channel *)tab->priv;
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290 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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291 #ifdef CYGDBG_IO_INIT
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292 diag_printf("SH SERIAL init - dev: %x.%d\n",
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293 h8300_chan->data, h8300_chan->rx_int_num);
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294 #endif
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295 // Really only required for interrupt driven devices
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296 (chan->callbacks->serial_init)(chan);
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297
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298 if (chan->out_cbuf.len != 0) {
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299 cyg_drv_interrupt_create(h8300_chan->tx_int_num,
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300 3,
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301 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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302 h8300_serial_tx_ISR,
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303 h8300_serial_tx_DSR,
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304 &h8300_chan->serial_tx_interrupt_handle,
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305 &h8300_chan->serial_tx_interrupt);
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306 cyg_drv_interrupt_attach(h8300_chan->serial_tx_interrupt_handle);
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307 cyg_drv_interrupt_unmask(h8300_chan->tx_int_num);
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308 h8300_chan->tx_enabled = false;
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309 }
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310 if (chan->in_cbuf.len != 0) {
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311 // Receive interrupt
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312 cyg_drv_interrupt_create(h8300_chan->rx_int_num,
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313 3,
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314 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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315 h8300_serial_rx_ISR,
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316 h8300_serial_rx_DSR,
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317 &h8300_chan->serial_rx_interrupt_handle,
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318 &h8300_chan->serial_rx_interrupt);
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319 cyg_drv_interrupt_attach(h8300_chan->serial_rx_interrupt_handle);
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320 // Receive error interrupt
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321 cyg_drv_interrupt_create(h8300_chan->er_int_num,
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322 3,
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323 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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324 h8300_serial_er_ISR,
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325 h8300_serial_er_DSR,
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326 &h8300_chan->serial_er_interrupt_handle,
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327 &h8300_chan->serial_er_interrupt);
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328 cyg_drv_interrupt_attach(h8300_chan->serial_er_interrupt_handle);
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329 // This unmasks both interrupt sources.
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330 cyg_drv_interrupt_unmask(h8300_chan->rx_int_num);
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331 }
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332 h8300_serial_config_port(chan, &chan->config, true);
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333 return true;
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334 }
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335
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336 // This routine is called when the device is "looked" up (i.e. attached)
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337 static Cyg_ErrNo
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338 h8300_serial_lookup(struct cyg_devtab_entry **tab,
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339 struct cyg_devtab_entry *sub_tab,
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340 const char *name)
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341 {
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342 serial_channel *chan = (serial_channel *)(*tab)->priv;
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343
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344 // Really only required for interrupt driven devices
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345 (chan->callbacks->serial_init)(chan);
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346 return ENOERR;
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347 }
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348
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349 // Send a character to the device output buffer.
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350 // Return 'true' if character is sent to device
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351 static bool
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352 h8300_serial_putc(serial_channel *chan, unsigned char c)
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353 {
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354 cyg_uint8 _ssr;
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355 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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356
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357 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr);
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358 if (_ssr & CYGARC_REG_SCSSR_TDRE) {
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359 // Transmit buffer is empty
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360 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCTDR, c);
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361 // Clear empty flag.
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362 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR,
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363 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_TDRE);
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364 return true;
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365 } else {
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366 // No space
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367 return false;
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368 }
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369 }
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370
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371 // Fetch a character from the device input buffer, waiting if necessary
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372 static unsigned char
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373 h8300_serial_getc(serial_channel *chan)
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374 {
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375 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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376 unsigned char c;
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377 cyg_uint8 _ssr;
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378
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379 do {
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380 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr);
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381 } while ((_ssr & CYGARC_REG_SCSSR_RDRF) == 0);
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382
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383 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCRDR, c);
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384
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385 // Clear buffer full flag.
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386 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR,
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387 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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388
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389 return c;
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390 }
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391
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392 // Set up the device characteristics; baud rate, etc.
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393 static Cyg_ErrNo
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394 h8300_serial_set_config(serial_channel *chan, cyg_uint32 key,
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395 const void *xbuf, cyg_uint32 *len)
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396 {
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397 switch (key) {
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398 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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399 {
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400 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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401 if ( *len < sizeof(cyg_serial_info_t) ) {
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parents:
diff changeset
402 return -EINVAL;
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jlarmour
parents:
diff changeset
403 }
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diff changeset
404 *len = sizeof(cyg_serial_info_t);
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diff changeset
405 if ( true != h8300_serial_config_port(chan, config, false) )
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diff changeset
406 return -EINVAL;
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diff changeset
407 }
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diff changeset
408 break;
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diff changeset
409 default:
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diff changeset
410 return -EINVAL;
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411 }
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412 return ENOERR;
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diff changeset
413 }
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diff changeset
414
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diff changeset
415 // Enable the transmitter on the device
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diff changeset
416 static void
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diff changeset
417 h8300_serial_start_xmit(serial_channel *chan)
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418 {
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419 cyg_uint8 _scr;
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420 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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421
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422 h8300_chan->tx_enabled = true;
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423
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424 // Mask the interrupts (all sources of the unit) while changing
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425 // the CR since a rx interrupt in the middle of this would result
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426 // in a bad CR state.
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427 cyg_drv_interrupt_mask(h8300_chan->rx_int_num);
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428
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429 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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430 _scr |= CYGARC_REG_SCSCR_TIE; // Enable xmit interrupt
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431 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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432
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433 cyg_drv_interrupt_unmask(h8300_chan->rx_int_num);
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434 }
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435
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436 // Disable the transmitter on the device
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437 static void
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438 h8300_serial_stop_xmit(serial_channel *chan)
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439 {
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440 cyg_uint8 _scr;
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441 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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442
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443 h8300_chan->tx_enabled = false;
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diff changeset
444
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445 // Mask the interrupts (all sources of the unit) while changing
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446 // the CR since a rx interrupt in the middle of this would result
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447 // in a bad CR state.
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448 cyg_drv_interrupt_mask(h8300_chan->rx_int_num);
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449
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450 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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451 _scr &= ~CYGARC_REG_SCSCR_TIE; // Disable xmit interrupt
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452 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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453
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454 cyg_drv_interrupt_unmask(h8300_chan->rx_int_num);
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455 }
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diff changeset
456
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457 // Serial I/O - low level tx interrupt handler (ISR)
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458 static cyg_uint32
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459 h8300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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460 {
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461 serial_channel *chan = (serial_channel *)data;
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462 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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463 cyg_uint8 _scr;
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diff changeset
464
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465 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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466 _scr &= ~CYGARC_REG_SCSCR_TIE; // mask out tx interrupts
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467 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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468
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469 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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470 }
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471
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472 // Serial I/O - high level tx interrupt handler (DSR)
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473 static void
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474 h8300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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475 {
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476 serial_channel *chan = (serial_channel *)data;
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477 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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diff changeset
478
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479 (chan->callbacks->xmt_char)(chan);
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480
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481 if (h8300_chan->tx_enabled) {
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diff changeset
482 cyg_uint8 _scr;
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diff changeset
483
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484 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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485 _scr |= CYGARC_REG_SCSCR_TIE; // unmask tx interrupts
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486 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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487 }
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diff changeset
488 }
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diff changeset
489
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diff changeset
490 // Serial I/O - low level RX interrupt handler (ISR)
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diff changeset
491 static cyg_uint32
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diff changeset
492 h8300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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diff changeset
493 {
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494 serial_channel *chan = (serial_channel *)data;
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495 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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diff changeset
496 cyg_uint8 _scr;
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diff changeset
497
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498 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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499 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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diff changeset
500 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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501 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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diff changeset
502 }
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diff changeset
503
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diff changeset
504 // Serial I/O - high level rx interrupt handler (DSR)
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diff changeset
505 static void
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diff changeset
506 h8300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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diff changeset
507 {
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diff changeset
508 serial_channel *chan = (serial_channel *)data;
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509 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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diff changeset
510 cyg_uint8 _ssr, _scr;
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diff changeset
511
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diff changeset
512 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr);
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diff changeset
513 if (_ssr & CYGARC_REG_SCSSR_RDRF) {
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diff changeset
514 cyg_uint8 _c;
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515 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCRDR, _c);
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516 // Clear buffer full flag.
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517 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR,
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diff changeset
518 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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diff changeset
519
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diff changeset
520 (chan->callbacks->rcv_char)(chan, _c);
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521 }
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diff changeset
522
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523 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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diff changeset
524 _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts
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diff changeset
525 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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diff changeset
526 }
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diff changeset
527
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diff changeset
528 static volatile int h8300_serial_error_orer = 0;
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diff changeset
529 static volatile int h8300_serial_error_fer = 0;
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diff changeset
530 static volatile int h8300_serial_error_per = 0;
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diff changeset
531
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532 // Serial I/O - low level error interrupt handler (ISR)
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diff changeset
533 static cyg_uint32
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diff changeset
534 h8300_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data)
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535 {
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536 serial_channel *chan = (serial_channel *)data;
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537 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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538 cyg_uint8 _scr;
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539
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540 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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541 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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542 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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543 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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544 }
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545
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546 // Serial I/O - high level error interrupt handler (DSR)
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547 static void
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548 h8300_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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549 {
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550 serial_channel *chan = (serial_channel *)data;
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551 h8300_sci_info *h8300_chan = (h8300_sci_info *)chan->dev_priv;
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552 cyg_uint8 _ssr, _ssr2, _scr;
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553
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554 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr);
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555 _ssr2 = CYGARC_REG_SCSSR_CLEARMASK;
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556
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557 if (_ssr & CYGARC_REG_SCSSR_ORER) {
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558 _ssr2 &= ~CYGARC_REG_SCSSR_ORER;
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559 h8300_serial_error_orer++;
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560 }
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561 if (_ssr & CYGARC_REG_SCSSR_FER) {
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562 _ssr2 &= ~CYGARC_REG_SCSSR_FER;
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563 h8300_serial_error_fer++;
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564 }
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565 if (_ssr & CYGARC_REG_SCSSR_PER) {
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566 _ssr2 &= ~CYGARC_REG_SCSSR_PER;
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567 h8300_serial_error_per++;
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568 }
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569 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSSR, _ssr2);
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570
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571 HAL_READ_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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572 _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts
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573 HAL_WRITE_UINT8(h8300_chan->ctrl_base+SCI_SCSCR, _scr);
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574 }
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575
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576 #endif // ifdef CYGDAT_IO_SERIAL_H8300_SCI