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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
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2 #define CYGONCE_HAL_PLATFORM_INTS_H
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3 //==========================================================================
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4 //
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5 // hal_platform_ints.h
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6 //
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7 // HAL Interrupt and clock support
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8 //
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9 //==========================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 // at http://sources.redhat.com/ecos/ecos-license
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): jskov
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46 // Contributors: jskov
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47 // Date: 2001-11-02
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48 // Purpose: Define Interrupt support
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49 // Description: The interrupt details for the Agilent AAED2000 are defined here.
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50 // Usage:
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51 // #include <cyg/hal/hal_platform_ints.h>
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52 // ...
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53 //
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54 //
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55 //####DESCRIPTIONEND####
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56 //
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57 //==========================================================================
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58
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59 // These are interrupts on the AAEC-2000 core
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60
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61 #define CYGNUM_HAL_INTERRUPT_GPIO0FIQ 0
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62 #define CYGNUM_HAL_INTERRUPT_TS CYGNUM_HAL_INTERRUPT_GPIO0FIQ
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63 #define CYGNUM_HAL_INTERRUPT_BLINT 1
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64 #define CYGNUM_HAL_INTERRUPT_WEINT 2
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65 #define CYGNUM_HAL_INTERRUPT_MCINT 3
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66 #define CYGNUM_HAL_INTERRUPT_CSINT 4
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67 #define CYGNUM_HAL_INTERRUPT_GPIO1INTR 5
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68 #define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO1INTR
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69 #define CYGNUM_HAL_INTERRUPT_GPIO2INTR 6
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70 #define CYGNUM_HAL_INTERRUPT_PCMCIA_CD2 CYGNUM_HAL_INTERRUPT_GPIO2INTR
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71 #define CYGNUM_HAL_INTERRUPT_GPIO3INTR 7
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72 #define CYGNUM_HAL_INTERRUPT_PCMCIA_CD1 CYGNUM_HAL_INTERRUPT_GPIO3INTR
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73 #define CYGNUM_HAL_INTERRUPT_TC1OI 8
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74 #define CYGNUM_HAL_INTERRUPT_TC2OI 9
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75 #define CYGNUM_HAL_INTERRUPT_RTCMI 10
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76 #define CYGNUM_HAL_INTERRUPT_TINTR 11
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77 #define CYGNUM_HAL_INTERRUPT_UART1INTR 12
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78 #define CYGNUM_HAL_INTERRUPT_UART2INTR 13
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79 #define CYGNUM_HAL_INTERRUPT_LCDINTR 14
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80 #define CYGNUM_HAL_INTERRUPT_SSEOTI 15
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81 #define CYGNUM_HAL_INTERRUPT_UART3INTR 16
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82 #define CYGNUM_HAL_INTERRUPT_SCIINTR 17
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83 #define CYGNUM_HAL_INTERRUPT_AACINTR 18
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84 #define CYGNUM_HAL_INTERRUPT_MMCINTR 19
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85 #define CYGNUM_HAL_INTERRUPT_USBINTR 20
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86 #define CYGNUM_HAL_INTERRUPT_DMAINTR 21
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87 #define CYGNUM_HAL_INTERRUPT_TC3OI 22
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88 #define CYGNUM_HAL_INTERRUPT_GPIO4INTR 23
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89 #define CYGNUM_HAL_INTERRUPT_SCI_VCCEN CYGNUM_HAL_INTERRUPT_GPIO4INTR
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90 #define CYGNUM_HAL_INTERRUPT_GPIO5INTR 24
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91 #define CYGNUM_HAL_INTERRUPT_SCI_DETECT CYGNUM_HAL_INTERRUPT_GPIO5INTR
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92 #define CYGNUM_HAL_INTERRUPT_GPIO6INTR 25
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93 #define CYGNUM_HAL_INTERRUPT_PCMCIA_RDY1 CYGNUM_HAL_INTERRUPT_GPIO6INTR
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94 #define CYGNUM_HAL_INTERRUPT_GPIO7INTR 26
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95 #define CYGNUM_HAL_INTERRUPT_PCMCIA_RDY2 CYGNUM_HAL_INTERRUPT_GPIO7INTR
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96 #define CYGNUM_HAL_INTERRUPT_BMIINTR 27
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97
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98 #define CYGNUM_HAL_INTERRUPT_NONE -1
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99
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100 #define CYGNUM_HAL_ISR_MIN 0
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101 #define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERRUPT_BMIINTR)
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102
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103 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
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104
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105 // The vector used by the Real time clock
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106 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TC1OI
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107
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108 //----------------------------------------------------------------------------
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109 // Reset.
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110
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111 externC void cyg_hal_arm9_soft_reset(CYG_ADDRESS);
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112 #define HAL_PLATFORM_RESET() cyg_hal_arm9_soft_reset(0)
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113
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114 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
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115
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116 #endif // CYGONCE_HAL_PLATFORM_INTS_H