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annotate packages/hal/arm/iq80310/current/include/hal_cache.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents e2d866e32dac
children d2c90368aeef
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
208
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
152
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): hmt
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47 // Contributors:hmt
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48 // Date: 1999-07-05
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <cyg/infra/cyg_type.h>
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62 //#include <cyg/hal/hal_mmu.h>
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63
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64 //-----------------------------------------------------------------------------
154
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65 // FIXME: This definition forces the IO flash driver to use a
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66 // known-good procedure for fiddling flash before calling flash device
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67 // driver functions. The procedure breaks on other platform/driver
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68 // combinations though so is depricated. Hence this definition.
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69 //
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70 // If you work on this target, please try to remove this definition
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71 // and verify that the flash driver still works (both from RAM and
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72 // flash). If it does, remove the definition and this comment for good
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73 // [and the old macro definition if this happens to be the last client
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74 // of that code].
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75 #define HAL_FLASH_CACHES_OLD_MACROS
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76
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77 //-----------------------------------------------------------------------------
152
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78 // Cache dimensions
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79
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80 #define HAL_DCACHE_SIZE 0x8000 // Size of data cache in bytes
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81 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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82 #define HAL_DCACHE_WAYS 32 // Associativity of the cache
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83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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84
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85 #define HAL_ICACHE_SIZE 0x8000 // Size of icache in bytes
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86 #define HAL_ICACHE_LINE_SIZE 32 // Size of ins cache line
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87 #define HAL_ICACHE_WAYS 32 // Associativity of the cache
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88 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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89
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90 //-----------------------------------------------------------------------------
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91 // Global control of data cache
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92
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93 // Enable the data cache
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94 #define HAL_DCACHE_ENABLE() \
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95 CYG_MACRO_START \
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96 asm volatile ( \
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97 "mrc p15,0,r1,c7,c10,4;" /* drain write buffer */ \
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98 "mrc p15,0,r1,c1,c0,0;" \
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99 "orr r1,r1,#0x0007;" /* enable DCache (also ensures the */ \
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100 /* MMU and alignment faults are */ \
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101 /* enabled) */ \
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102 "mcr p15,0,r1,c1,c0,0;" \
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103 : \
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104 : \
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105 : "r1" /* Clobber list */ \
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106 ); \
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107 CYG_MACRO_END
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108
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109 // Disable the data cache (and invalidate it, required semanitcs)
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110 #define HAL_DCACHE_DISABLE() \
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111 CYG_MACRO_START \
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112 asm volatile ( \
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113 "mrc p15,0,r1,c1,c0,0;" \
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114 "bic r1,r1,#4;" \
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115 "mcr p15,0,r1,c1,c0,0;" \
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116 /* cpuwait */ \
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117 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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118 "mov r1,r1;" \
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119 "sub pc,pc,#4;" \
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120 "mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
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121 /* cpuwait */ \
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122 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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123 "mov r1,r1;" \
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124 "sub pc,pc,#4;" \
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125 : \
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126 : \
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127 : "r1" /* Clobber list */ \
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128 ); \
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129 CYG_MACRO_END
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130
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131 // Invalidate the entire cache (and both TLBs, just in case)
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132 #define HAL_DCACHE_INVALIDATE_ALL() \
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133 CYG_MACRO_START \
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134 /* this macro can discard dirty cache lines. */ \
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135 asm volatile ( \
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136 "mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
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137 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
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138 : \
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139 : \
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140 : "r1" /* Clobber list */ \
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141 ); \
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142 CYG_MACRO_END
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143
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144
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145 // Synchronize the contents of the cache with memory.
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146 #define HAL_DCACHE_SYNC() \
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147 CYG_MACRO_START \
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148 /* The best way to evict a dirty line is by using the */ \
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149 /* line allocate operation on non-existent memory. */ \
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150 asm volatile ( \
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151 "mov r0, #0xC0000000;" /* cache flush region */ \
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152 "add r1, r0, #0x8000;" /* 32KB cache */ \
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153 "667: " \
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154 "mcr p15,0,r0,c7,c2,5;" /* allocate a line */ \
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155 "add r0, r0, #32;" /* 32 bytes/line */ \
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156 "teq r1, r0;" \
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157 "bne 667b;" \
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158 "mcr p15,0,r0,c7,c6,0;" /* invalidate data cache */ \
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159 /* cpuwait */ \
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160 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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161 "mov r1,r1;" \
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162 "sub pc,pc,#4;" \
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163 "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
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164 /* cpuwait */ \
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165 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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166 "mov r1,r1;" \
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167 "sub pc,pc,#4;" \
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168 "nop" \
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169 : \
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170 : \
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171 : "r0","r1" /* Clobber list */ \
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172 ); \
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173 CYG_MACRO_END
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174
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175 // Query the state of the data cache
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176 #define HAL_DCACHE_IS_ENABLED(_state_) \
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177 CYG_MACRO_START \
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178 register int reg; \
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179 asm volatile ("mrc p15,0,%0,c1,c0,0" \
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180 : "=r"(reg) \
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181 : \
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182 /*:*/ \
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183 ); \
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184 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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185 CYG_MACRO_END
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186
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187 // Set the data cache refill burst size
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188 //#define HAL_DCACHE_BURST_SIZE(_size_)
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189
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190 // Set the data cache write mode
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191 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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192
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193 #define HAL_DCACHE_WRITETHRU_MODE 0
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194 #define HAL_DCACHE_WRITEBACK_MODE 1
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195
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196 // Get the current writeback mode - or only writeback mode if fixed
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197 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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198 _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
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199 CYG_MACRO_END
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200
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201 // Load the contents of the given address range into the data cache
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202 // and then lock the cache so that it stays there.
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203 //#define HAL_DCACHE_LOCK(_base_, _size_)
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204
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205 // Undo a previous lock operation
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206 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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207
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208 // Unlock entire cache
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209 //#define HAL_DCACHE_UNLOCK_ALL()
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210
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211 //-----------------------------------------------------------------------------
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212 // Data cache line control
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213
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214 // Allocate cache lines for the given address range without reading its
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215 // contents from memory.
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216 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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217
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218 // Write dirty cache lines to memory and invalidate the cache entries
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219 // for the given address range.
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220 // ---- this seems not to work despite the documentation ---
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221 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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222 //CYG_MACRO_START
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223 // HAL_DCACHE_STORE( _base_ , _size_ );
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224 // HAL_DCACHE_INVALIDATE( _base_ , _size_ );
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225 //CYG_MACRO_END
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226
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227 // Invalidate cache lines in the given range without writing to memory.
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228 // ---- this seems not to work despite the documentation ---
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229 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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230 //CYG_MACRO_START
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231 // register int addr, enda;
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232 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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233 // enda = (int)(_base_) + (_size_);
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234 // addr < enda ;
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235 // addr += HAL_DCACHE_LINE_SIZE )
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236 // {
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237 // asm volatile (
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238 // "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
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239 // :
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240 // : "r"(addr)
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241 // : "memory"
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242 // );
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243 // }
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244 //CYG_MACRO_END
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245
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246 // Write dirty cache lines to memory for the given address range.
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247 // ---- this seems not to work despite the documentation ---
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248 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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249 //CYG_MACRO_START
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250 // register int addr, enda;
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251 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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252 // enda = (int)(_base_) + (_size_);
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253 // addr < enda ;
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254 // addr += HAL_DCACHE_LINE_SIZE )
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255 // {
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256 // asm volatile ("mcr p15,0,%0,c7,c10,1" /* push entry to RAM */
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257 // :
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258 // : "r"(addr)
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259 // : "memory"
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260 // );
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261 // }
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262 //CYG_MACRO_END
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263
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264
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265 // Preread the given range into the cache with the intention of reading
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266 // from it later.
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267 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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268
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269 // Preread the given range into the cache with the intention of writing
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270 // to it later.
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271 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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272
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273 // Allocate and zero the cache lines associated with the given range.
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274 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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275
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276 //-----------------------------------------------------------------------------
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277 // Global control of Instruction cache
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278
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279 // Enable the instruction cache
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280 #define HAL_ICACHE_ENABLE() \
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281 CYG_MACRO_START \
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282 asm volatile ( \
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283 "mrc p15,0,r1,c1,c0,0;" \
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284 "orr r1,r1,#0x1000;" /* enable ICache */ \
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285 "mcr p15,0,r1,c1,c0,0;" \
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286 : \
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287 : \
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288 : "r1" /* Clobber list */ \
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289 ); \
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290 CYG_MACRO_END
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291
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292 // Disable the instruction cache (and invalidate it, required semanitcs)
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293 #define HAL_ICACHE_DISABLE() \
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294 CYG_MACRO_START \
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295 asm volatile ( \
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296 "mrc p15,0,r1,c1,c0,0;" \
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297 "bic r1,r1,#0x1000;" /* disable Icache */ \
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298 "mcr p15,0,r1,c1,c0,0;" \
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299 "mcr p15,0,r1,c7,c5,0;" /* invalidate instruction cache */ \
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300 "nop;" /* next few instructions may be via cache */ \
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301 "nop;" \
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302 "nop;" \
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303 "nop;" \
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304 "nop;" \
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305 "nop" \
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306 : \
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307 : \
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308 : "r1" /* Clobber list */ \
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309 ); \
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310 CYG_MACRO_END
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311
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312 // Invalidate the entire cache
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313 #define HAL_ICACHE_INVALIDATE_ALL() \
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314 CYG_MACRO_START \
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315 asm volatile ( \
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316 "mcr p15,0,r1,c7,c5,0;" /* clear instruction cache */ \
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317 "mcr p15,0,r1,c8,c5,0;" /* flush I TLB only */ \
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318 /* cpuwait */ \
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319 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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320 "mov r1,r1;" \
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321 "sub pc,pc,#4;" \
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322 "nop;" /* next few instructions may be via cache */ \
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323 "nop;" \
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324 "nop;" \
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325 "nop;" \
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326 "nop;" \
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327 "nop" \
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328 : \
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329 : \
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330 : "r1" /* Clobber list */ \
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331 ); \
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332 CYG_MACRO_END
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333
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334
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335 // Synchronize the contents of the cache with memory.
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336 // (which includes flushing out pending writes)
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337 #define HAL_ICACHE_SYNC() \
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338 CYG_MACRO_START \
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339 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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340 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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341 CYG_MACRO_END
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342
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343 // Query the state of the instruction cache
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344 #define HAL_ICACHE_IS_ENABLED(_state_) \
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345 CYG_MACRO_START \
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346 /* SA-110 manual states clearly that the control reg is readable */ \
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347 register cyg_uint32 reg; \
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348 asm volatile ("mrc p15,0,%0,c1,c0,0" \
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349 : "=r"(reg) \
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350 : \
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351 /*:*/ \
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352 ); \
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353 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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354 CYG_MACRO_END
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355
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356 // Set the instruction cache refill burst size
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357 //#define HAL_ICACHE_BURST_SIZE(_size_)
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358
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359 // Load the contents of the given address range into the instruction cache
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360 // and then lock the cache so that it stays there.
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361 //#define HAL_ICACHE_LOCK(_base_, _size_)
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362
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363 // Undo a previous lock operation
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364 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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365
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366 // Unlock entire cache
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367 //#define HAL_ICACHE_UNLOCK_ALL()
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368
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369 //-----------------------------------------------------------------------------
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370 // Instruction cache line control
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371
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372 // Invalidate cache lines in the given range without writing to memory.
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373 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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374
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375 //-----------------------------------------------------------------------------
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376 #endif // ifndef CYGONCE_HAL_CACHE_H
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377 // End of hal_cache.h