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annotate packages/hal/arm/sa11x0/assabet/current/src/assabet_misc.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents 2e9a636d9de9
children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // assabet_misc.c
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4 //
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5 // HAL misc board support code for StrongARM SA1110/Assabet
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): gthomas
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44 // Contributors: hmt
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45 // Travis C. Furrer <furrer@mit.edu>
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46 // Date: 2000-05-21
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47 // Purpose: HAL board support
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48 // Description: Implementations of HAL board interfaces
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //========================================================================*/
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53
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54 #include <pkgconf/hal.h>
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55 #include <pkgconf/system.h>
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56 #include CYGBLD_HAL_PLATFORM_H
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57
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58 #include <cyg/infra/cyg_type.h> // base types
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59 #include <cyg/infra/cyg_trac.h> // tracing macros
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60 #include <cyg/infra/cyg_ass.h> // assertion macros
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61
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62 #include <cyg/hal/hal_io.h> // IO macros
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63 #include <cyg/hal/hal_arch.h> // Register state info
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64 #include <cyg/hal/hal_diag.h>
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65 #include <cyg/hal/hal_intr.h> // Interrupt names
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66 #include <cyg/hal/hal_cache.h>
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67 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
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68 #include <cyg/hal/assabet.h> // Platform specifics
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69
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70 #include <cyg/infra/diag.h> // diag_printf
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71
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72 // All the MM table layout is here:
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73 #include <cyg/hal/hal_mm.h>
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74
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75 externC void* memset(void *, int, size_t);
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76
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77 void
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78 hal_mmu_init(void)
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79 {
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80 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
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81 unsigned long i;
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82
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83 /*
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84 * Set the TTB register
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85 */
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86 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
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87
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88 /*
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89 * Set the Domain Access Control Register
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90 */
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91 i = ARM_ACCESS_DACR_DEFAULT;
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92 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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93
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94 /*
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95 * First clear all TT entries - ie Set them to Faulting
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96 */
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97 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
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98
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99 /* Actual Virtual Size Attributes Function */
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100 /* Base Base MB cached? buffered? access permissions */
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101 /* xxx00000 xxx00000 */
117
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102 X_ARM_MMU_SECTION(0x000, 0x500, 32, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
108
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103 X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
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104 X_ARM_MMU_SECTION(0x100, 0x100, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA-1101 Development Board Registers */
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105 X_ARM_MMU_SECTION(0x180, 0x180, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ethernet Adaptor */
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106 X_ARM_MMU_SECTION(0x184, 0x184, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* XBusReg */
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107 X_ARM_MMU_SECTION(0x188, 0x188, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegA */
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108 X_ARM_MMU_SECTION(0x18C, 0x18C, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegB */
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109 X_ARM_MMU_SECTION(0x190, 0x190, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD A */
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110 X_ARM_MMU_SECTION(0x194, 0x194, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD B */
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111 X_ARM_MMU_SECTION(0x200, 0x200, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket A */
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112 X_ARM_MMU_SECTION(0x300, 0x300, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets B */
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113 X_ARM_MMU_SECTION(0x400, 0x400, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA1111 Daughter card */
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114 X_ARM_MMU_SECTION(0x480, 0x480, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Video Controller Daughter card */
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115 X_ARM_MMU_SECTION(0x800, 0x800, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
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116 X_ARM_MMU_SECTION(0xC00, 0, 32, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
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117 X_ARM_MMU_SECTION(0xC00, 0xC00, 32, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
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118 X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
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119
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120 }
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121
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122 //
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123 // Board control register support
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124 // Update the board control register (write only). Only the bits
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125 // specified by 'mask' are changed to 'value'.
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126 //
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127
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128 void
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129 assabet_BCR(unsigned long mask, unsigned long value)
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130 {
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131 _assabet_BCR = (_assabet_BCR & ~mask) | (mask & value);
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132 *SA1110_BOARD_CONTROL = _assabet_BCR;
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133 }
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134
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135 //
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136 // Platform specific initialization
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137 //
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138
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139 void
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140 plf_hardware_init(void)
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141 {
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142 // Force "alternate" use of GPIO pins used for LCD screen
126
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143 *SA11X0_GPIO_ALTERNATE_FUNCTION |= 0x000003FC; // Bits 2..9
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144 *SA11X0_GPIO_PIN_DIRECTION |= 0x000003FC; // Bits 2..9
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145 *SA11X0_GPIO_PIN_OUTPUT_CLEAR = 0x000003FC; // Bits 2..9
108
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146 }
143
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147
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148 #include CYGHWR_MEMORY_LAYOUT_H
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149 typedef void code_fun(void);
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150 void assabet_program_new_stack(void *func)
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151 {
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152 register CYG_ADDRESS stack_ptr asm("sp");
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153 register CYG_ADDRESS old_stack asm("r4");
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154 register code_fun *new_func asm("r0");
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155 old_stack = stack_ptr;
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156 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
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157 new_func = (code_fun*)func;
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158 new_func();
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159 stack_ptr = old_stack;
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160 return;
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161 }
145
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162
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163 // ------------------------------------------------------------------------
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164 // EOF assabet_misc.c