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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 /*=============================================================================
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2 //
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3 // hal_diag.c
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4 //
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5 // HAL diagnostic output code
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6 //
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7 //=============================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //=============================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): nickg, gthomas
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44 // Contributors:nickg, gthomas, msalter
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45 // Date: 1998-03-02
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46 // Purpose: HAL diagnostic output
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47 // Description: Implementations of HAL diagnostic output support.
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //===========================================================================*/
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52
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53 #include <pkgconf/hal.h>
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54 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
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55 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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56
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57 #include <cyg/infra/cyg_type.h> // base types
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58 #include <cyg/infra/cyg_trac.h> // tracing macros
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59 #include <cyg/infra/cyg_ass.h> // assertion macros
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60
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61 #include <cyg/hal/hal_arch.h> // basic machine info
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62 #include <cyg/hal/hal_intr.h> // interrupt macros
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63 #include <cyg/hal/hal_io.h> // IO macros
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64 #include <cyg/hal/hal_diag.h>
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65 #include <cyg/hal/drv_api.h>
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66 #include <cyg/hal/hal_if.h> // interface API
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67 #include <cyg/hal/hal_misc.h> // Helper functions
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68 #include <cyg/hal/iq80321.h> // platform definitions
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69
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70 /*---------------------------------------------------------------------------*/
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71 /* From serial_16550.h */
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72
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73 //-----------------------------------------------------------------------------
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74 // Based on 1.8432 MHz xtal
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75 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
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76 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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77 #define CYG_DEV_SERIAL_BAUD_LSB 0x0c
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78 #endif
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79 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
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80 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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81 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
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82 #endif
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83 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
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84 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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85 #define CYG_DEV_SERIAL_BAUD_LSB 0x03
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86 #endif
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87 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
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88 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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89 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
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90 #endif
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91 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
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92 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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93 #define CYG_DEV_SERIAL_BAUD_LSB 0x01
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94 #endif
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95
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96 #ifndef CYG_DEV_SERIAL_BAUD_MSB
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97 #error Missing/incorrect serial baud rate defined - CDL error?
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98 #endif
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99
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100 // Define the serial registers.
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101 #define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
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102 #define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
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103 #define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
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104 #define CYG_DEV_IER 0x01 // interrupt enable register, read/write, dlab = 0
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105 #define CYG_DEV_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
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106 #define CYG_DEV_IIR 0x02 // interrupt identification register, read, dlab = 0
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107 #define CYG_DEV_FCR 0x02 // fifo control register, write, dlab = 0
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108 #define CYG_DEV_LCR 0x03 // line control register, write
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109 #define CYG_DEV_MCR 0x04 // modem control register, write
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110 #define CYG_DEV_LSR 0x05 // line status register, read
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111 #define CYG_DEV_MSR 0x06 // modem status register, read
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112 #define CYG_DEV_SCR 0x07 // scratch pad register
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113
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114 // Interrupt Enable Register
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115 #define SIO_IER_RCV 0x01
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116 #define SIO_IER_XMT 0x02
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117 #define SIO_IER_LS 0x04
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118 #define SIO_IER_MS 0x08
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119
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120 // The line status register bits.
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121 #define SIO_LSR_DR 0x01 // data ready
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122 #define SIO_LSR_OE 0x02 // overrun error
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123 #define SIO_LSR_PE 0x04 // parity error
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124 #define SIO_LSR_FE 0x08 // framing error
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125 #define SIO_LSR_BI 0x10 // break interrupt
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126 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
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127 #define SIO_LSR_TEMT 0x40 // transmitter register empty
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128 #define SIO_LSR_ERR 0x80 // any error condition
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129
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130 // The modem status register bits.
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131 #define SIO_MSR_DCTS 0x01 // delta clear to send
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132 #define SIO_MSR_DDSR 0x02 // delta data set ready
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133 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
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134 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
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135 #define SIO_MSR_CTS 0x10 // clear to send
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136 #define SIO_MSR_DSR 0x20 // data set ready
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137 #define SIO_MSR_RI 0x40 // ring indicator
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138 #define SIO_MSR_DCD 0x80 // data carrier detect
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139
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140 // The line control register bits.
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141 #define SIO_LCR_WLS0 0x01 // word length select bit 0
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142 #define SIO_LCR_WLS1 0x02 // word length select bit 1
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143 #define SIO_LCR_STB 0x04 // number of stop bits
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144 #define SIO_LCR_PEN 0x08 // parity enable
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145 #define SIO_LCR_EPS 0x10 // even parity select
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146 #define SIO_LCR_SP 0x20 // stick parity
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147 #define SIO_LCR_SB 0x40 // set break
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148 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
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149
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150 // Modem Control Register
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151 #define SIO_MCR_DTR 0x01
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152 #define SIO_MCR_RTS 0x02
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153
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154
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155 //-----------------------------------------------------------------------------
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156 typedef struct {
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157 cyg_uint8* base;
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158 cyg_int32 msec_timeout;
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159 int isr_vector;
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160 } channel_data_t;
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161
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162
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163 //-----------------------------------------------------------------------------
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164
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165 static void
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166 cyg_hal_plf_serial_init_channel(void* __ch_data)
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167 {
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168 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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169 cyg_uint8 lcr;
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170
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171 // 8-1-no parity.
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172 HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
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173 HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
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174 lcr |= SIO_LCR_DLAB;
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175 HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
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176 HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEV_SERIAL_BAUD_LSB);
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177 HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEV_SERIAL_BAUD_MSB);
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178 lcr &= ~SIO_LCR_DLAB;
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179 HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
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180 HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO
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181 }
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182
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183 void
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184 cyg_hal_plf_serial_putc(void *__ch_data, char c)
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185 {
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186 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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187 cyg_uint8 lsr;
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188 CYGARC_HAL_SAVE_GP();
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189
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190 do {
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191 HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
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192 } while ((lsr & SIO_LSR_THRE) == 0);
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193
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194 HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
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195
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196 CYGARC_HAL_RESTORE_GP();
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197 }
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198
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199 static cyg_bool
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200 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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201 {
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202 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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203 cyg_uint8 lsr;
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204
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205 HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
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206 if ((lsr & SIO_LSR_DR) == 0)
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207 return false;
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208
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209 HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
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210
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211 return true;
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212 }
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213
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214 cyg_uint8
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215 cyg_hal_plf_serial_getc(void* __ch_data)
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216 {
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217 cyg_uint8 ch;
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218 CYGARC_HAL_SAVE_GP();
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219
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220 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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221
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222 CYGARC_HAL_RESTORE_GP();
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223 return ch;
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224 }
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225
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226 static channel_data_t plf_ser_channels[1] = {
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227 { (cyg_uint8*)IQ80321_UART_ADDR, 1000, CYGNUM_HAL_INTERRUPT_UART }
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228 };
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229
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230 static void
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231 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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232 cyg_uint32 __len)
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233 {
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234 CYGARC_HAL_SAVE_GP();
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235
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236 while(__len-- > 0)
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237 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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238
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239 CYGARC_HAL_RESTORE_GP();
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240 }
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241
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242 static void
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243 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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244 {
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245 CYGARC_HAL_SAVE_GP();
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246
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247 while(__len-- > 0)
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248 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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249
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250 CYGARC_HAL_RESTORE_GP();
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251 }
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252
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253 cyg_bool
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254 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
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255 {
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256 int delay_count;
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257 channel_data_t* chan = (channel_data_t*)__ch_data;
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258 cyg_bool res;
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259 CYGARC_HAL_SAVE_GP();
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260
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261 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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262
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263 for(;;) {
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264 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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265 if (res || 0 == delay_count--)
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266 break;
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267
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268 CYGACC_CALL_IF_DELAY_US(100);
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269 }
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270
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271 CYGARC_HAL_RESTORE_GP();
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272 return res;
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273 }
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274
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275 static int
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276 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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277 {
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278 static int irq_state = 0;
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279 channel_data_t* chan = (channel_data_t*)__ch_data;
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280 int ret = 0;
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281 CYGARC_HAL_SAVE_GP();
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282
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283 switch (__func) {
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284 case __COMMCTL_IRQ_ENABLE:
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285 irq_state = 1;
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286
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287 HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
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288 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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289 break;
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290 case __COMMCTL_IRQ_DISABLE:
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291 ret = irq_state;
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292 irq_state = 0;
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293
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294 HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
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295 HAL_INTERRUPT_MASK(chan->isr_vector);
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296 break;
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297 case __COMMCTL_DBG_ISR_VECTOR:
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298 ret = chan->isr_vector;
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299 break;
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300 case __COMMCTL_SET_TIMEOUT:
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301 {
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302 va_list ap;
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303
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304 va_start(ap, __func);
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305
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306 ret = chan->msec_timeout;
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307 chan->msec_timeout = va_arg(ap, cyg_uint32);
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308
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309 va_end(ap);
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310 }
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311 default:
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312 break;
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313 }
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314 CYGARC_HAL_RESTORE_GP();
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315 return ret;
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316 }
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317
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318 static int
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319 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
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320 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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321 {
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322 int res = 0;
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323 channel_data_t* chan = (channel_data_t*)__ch_data;
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324 char c;
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325 cyg_uint8 lsr;
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326 CYGARC_HAL_SAVE_GP();
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327
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328 cyg_drv_interrupt_acknowledge(chan->isr_vector);
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329
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330 *__ctrlc = 0;
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331 HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
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332 if ( (lsr & SIO_LSR_DR) != 0 ) {
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333
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334 HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
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335 if( cyg_hal_is_break( &c , 1 ) )
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336 *__ctrlc = 1;
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337
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338 res = CYG_ISR_HANDLED;
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339 }
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340
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341 CYGARC_HAL_RESTORE_GP();
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342 return res;
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343 }
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344
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345 static void
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346 cyg_hal_plf_serial_init(void)
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347 {
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348 hal_virtual_comm_table_t* comm;
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349 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
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350
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351 // Disable interrupts.
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352 HAL_INTERRUPT_MASK(plf_ser_channels[0].isr_vector);
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353
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354 // Init channels
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355 cyg_hal_plf_serial_init_channel(&plf_ser_channels[0]);
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356
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357 // Setup procs in the vector table
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358
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359 // Set channel 0
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360 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
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361 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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362 CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[0]);
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363 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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364 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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365 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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366 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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367 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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368 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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369 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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370
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371 // Restore original console
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372 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
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373 }
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374
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375 void
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376 cyg_hal_plf_comms_init(void)
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377 {
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378 static int initialized = 0;
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379
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380 if (initialized)
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381 return;
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382
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383 initialized = 1;
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384
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385 cyg_hal_plf_serial_init();
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386 }
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387
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388 /*---------------------------------------------------------------------------*/
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389
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390 cyg_uint8 cyg_hal_led_segment[16] = {
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391 DISPLAY_0, DISPLAY_1, DISPLAY_2, DISPLAY_3,
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392 DISPLAY_4, DISPLAY_5, DISPLAY_6, DISPLAY_7,
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393 DISPLAY_8, DISPLAY_9, DISPLAY_A, DISPLAY_B,
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394 DISPLAY_C, DISPLAY_D, DISPLAY_E, DISPLAY_F };
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395
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396 void
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397 hal_diag_led(int n)
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398 {
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399 HAL_WRITE_UINT8(DISPLAY_RIGHT, cyg_hal_led_segment[n & 0x0f]);
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400 }
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401
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402 /*---------------------------------------------------------------------------*/
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403 /* End of hal_diag.c */