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annotate packages/hal/calmrisc16/arch/current/include/hal_cache.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors: nickg
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48 // Date: 1998-02-17
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <pkgconf/hal.h>
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62 #include <cyg/infra/cyg_type.h>
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63
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64 #include <cyg/hal/var_cache.h>
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65
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66
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67 //-----------------------------------------------------------------------------
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68 // Cache dimensions.
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69 // These really should be defined in var_cache.h. If they are not, then provide
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70 // a set of numbers that are typical of many variants.
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71
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72 #ifndef HAL_DCACHE_SIZE
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73
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74 // Data cache
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75 //#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
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76 //#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
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77 //#define HAL_DCACHE_WAYS 0 // Associativity of the cache
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78
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79 // Instruction cache
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80 //#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
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81 //#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
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82 //#define HAL_ICACHE_WAYS 0 // Associativity of the cache
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83
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84 //#define HAL_DCACHE_SETS 0
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85 //#define HAL_ICACHE_SETS 0
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86
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87 #endif
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88
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89 //-----------------------------------------------------------------------------
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90 // Global control of data cache
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91
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92 // Enable the data cache
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93 // There is no default mechanism for enabling or disabling the caches.
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94 #ifndef HAL_DCACHE_ENABLE_DEFINED
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95 #define HAL_DCACHE_ENABLE()
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96 #endif
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97
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98 // Disable the data cache
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99 #ifndef HAL_DCACHE_DISABLE_DEFINED
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100 #define HAL_DCACHE_DISABLE()
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101 #endif
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102
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103 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
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104 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
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105 #endif
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106
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107 // Invalidate the entire cache
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108 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
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109 // is not quite what we want, but there is no index-invalidate operation
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110 // available.
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111 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
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112 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
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113 #endif
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114
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115 // Synchronize the contents of the cache with memory.
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116 // This uses the index-writeback-invalidate operation.
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117 #ifndef HAL_DCACHE_SYNC_DEFINED
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118 #define HAL_DCACHE_SYNC() \
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119 CYG_MACRO_START \
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120 CYG_MACRO_END
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121 #endif
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122
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123 // Set the data cache refill burst size
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124 //#define HAL_DCACHE_BURST_SIZE(_size_)
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125
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126 // Set the data cache write mode
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127 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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128
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129 //#define HAL_DCACHE_WRITETHRU_MODE 0
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130 //#define HAL_DCACHE_WRITEBACK_MODE 1
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131
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132 // Load the contents of the given address range into the data cache
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133 // and then lock the cache so that it stays there.
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134 // This uses the fetch-and-lock cache operation.
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135 #ifndef HAL_DCACHE_LOCK_DEFINED
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136 #define HAL_DCACHE_LOCK(_base_, _asize_) \
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137 CYG_MACRO_START \
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138 CYG_MACRO_END
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139 #endif
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140
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141 // Undo a previous lock operation.
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142 // Do this by flushing the cache, which is defined to clear the lock bit.
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143 #ifndef HAL_DCACHE_UNLOCK_DEFINED
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144 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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145 HAL_DCACHE_FLUSH( _base_, _size_ )
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146 #endif
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147
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148 // Unlock entire cache
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149 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
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150 #define HAL_DCACHE_UNLOCK_ALL() \
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151 HAL_DCACHE_INVALIDATE_ALL()
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152 #endif
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153
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154 //-----------------------------------------------------------------------------
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155 // Data cache line control
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156
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157 // Allocate cache lines for the given address range without reading its
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158 // contents from memory.
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159 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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160
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161 // Write dirty cache lines to memory and invalidate the cache entries
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162 // for the given address range.
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163 // This uses the hit-writeback-invalidate cache operation.
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164 #ifndef HAL_DCACHE_FLUSH_DEFINED
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165 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
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166 CYG_MACRO_START \
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167 CYG_MACRO_END
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168 #endif
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169
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170 // Invalidate cache lines in the given range without writing to memory.
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171 // This uses the hit-invalidate cache operation.
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172 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
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173 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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174 CYG_MACRO_START \
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175 CYG_MACRO_END
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176 #endif
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177
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178 // Write dirty cache lines to memory for the given address range.
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179 // This uses the hit-writeback cache operation.
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180 #ifndef HAL_DCACHE_STORE_DEFINED
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181 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
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182 CYG_MACRO_START \
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183 CYG_MACRO_END
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184 #endif
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185
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186 // Preread the given range into the cache with the intention of reading
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187 // from it later.
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188 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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189
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190 // Preread the given range into the cache with the intention of writing
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191 // to it later.
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192 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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193
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194 // Allocate and zero the cache lines associated with the given range.
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195 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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196
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197 //-----------------------------------------------------------------------------
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198 // Global control of Instruction cache
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199
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200 // Enable the instruction cache
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201 // There is no default mechanism for enabling or disabling the caches.
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202 #ifndef HAL_ICACHE_ENABLE_DEFINED
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203 #define HAL_ICACHE_ENABLE()
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204 #endif
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205
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206 // Disable the instruction cache
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207 #ifndef HAL_ICACHE_DISABLE_DEFINED
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208 #define HAL_ICACHE_DISABLE()
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209 #endif
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210
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211 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
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212 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
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213 #endif
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214
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215 // Invalidate the entire cache
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216 // This uses the index-invalidate cache operation.
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217 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
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218 #define HAL_ICACHE_INVALIDATE_ALL() \
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219 CYG_MACRO_START \
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220 CYG_MACRO_END
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221 #endif
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222
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223 // Synchronize the contents of the cache with memory.
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224 // Simply force the cache to reload.
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225 #ifndef HAL_ICACHE_SYNC_DEFINED
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226 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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227 #endif
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228
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229 // Set the instruction cache refill burst size
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230 //#define HAL_ICACHE_BURST_SIZE(_size_)
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231
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232 // Load the contents of the given address range into the instruction cache
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233 // and then lock the cache so that it stays there.
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234 // This uses the fetch-and-lock cache operation.
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235 #ifndef HAL_ICACHE_LOCK_DEFINED
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236 #define HAL_ICACHE_LOCK(_base_, _asize_) \
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237 CYG_MACRO_START \
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238 CYG_MACRO_END
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239 #endif
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240
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241 // Undo a previous lock operation.
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242 // Do this by invalidating the cache, which is defined to clear the lock bit.
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243 #ifndef HAL_ICACHE_UNLOCK_DEFINED
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244 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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245 HAL_ICACHE_INVALIDATE( _base_, _size_ )
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246 #endif
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247
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248 // Unlock entire cache
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249 //#define HAL_ICACHE_UNLOCK_ALL()
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250
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251 //-----------------------------------------------------------------------------
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252 // Instruction cache line control
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253
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254 // Invalidate cache lines in the given range without writing to memory.
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255 // This uses the hit-invalidate cache operation.
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256 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
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257 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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258 CYG_MACRO_START \
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259 CYG_MACRO_END
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260 #endif
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261
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262
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263 //-----------------------------------------------------------------------------
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264 #endif // ifndef CYGONCE_HAL_CACHE_H
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265 // End of hal_cache.h