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annotate packages/hal/frv/arch/current/include/hal_cache.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): gthomas
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47 // Contributors:hmt
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48 // Date: 2000-05-08
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <cyg/infra/cyg_type.h>
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62 #include CYGBLD_HAL_PLF_DEFS_H
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63 #include <cyg/hal/plf_cache.h> // Platform (model) details
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64
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65 //-----------------------------------------------------------------------------
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66 // Global control of Instruction cache
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67
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68 // Enable the instruction cache
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69 #define HAL_ICACHE_ENABLE() \
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70 CYG_MACRO_START \
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71 cyg_uint32 mask = _HSR0_ICE; \
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72 asm volatile ( \
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73 "movsg hsr0,gr4\n" \
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74 "\tor gr4,%0,gr4\n" \
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75 "\tmovgs gr4,hsr0\n" \
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76 : \
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77 : "r"(mask) \
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78 : "gr4" /* Clobber list */ \
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79 ); \
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80 CYG_MACRO_END
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81
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82 // Disable the instruction cache (and invalidate it, required semanitcs)
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83 #define HAL_ICACHE_DISABLE() \
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84 CYG_MACRO_START \
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85 cyg_uint32 mask = ~_HSR0_ICE; \
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86 asm volatile ( \
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87 "movsg hsr0,gr4\n" \
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88 "\tand gr4,%0,gr4\n" \
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89 "\tmovgs gr4,hsr0\n" \
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90 : \
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91 : "r"(mask) \
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92 : "gr4" /* Clobber list */ \
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93 ); \
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94 CYG_MACRO_END
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95
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96 // Query the state of the instruction cache
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97 #define HAL_ICACHE_IS_ENABLED(_state_) \
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98 CYG_MACRO_START \
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99 register cyg_uint32 reg; \
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100 asm volatile ("movsg hsr0,%0" \
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101 : "=r"(reg) \
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102 : \
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103 ); \
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104 (_state_) = (0 != (_HSR0_ICE & reg)); \
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105 CYG_MACRO_END
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106
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107 // Invalidate the entire cache
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108 #define HAL_ICACHE_INVALIDATE_ALL() \
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109 CYG_MACRO_START \
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110 asm volatile ("icei @(gr4,gr0),1" \
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111 : \
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112 : \
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113 ); \
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114 CYG_MACRO_END
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115
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116 // Synchronize the contents of the cache with memory.
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117 // (which includes flushing out pending writes)
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118 #define HAL_ICACHE_SYNC() \
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119 CYG_MACRO_START \
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120 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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121 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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122 CYG_MACRO_END
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123
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124 // Set the instruction cache refill burst size
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125 //#define HAL_ICACHE_BURST_SIZE(_size_)
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126
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127 // Load the contents of the given address range into the instruction cache
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128 // and then lock the cache so that it stays there.
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129 //#define HAL_ICACHE_LOCK(_base_, _size_)
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130
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131 // Undo a previous lock operation
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132 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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133
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134 // Unlock entire cache
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135 //#define HAL_ICACHE_UNLOCK_ALL()
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136
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137 //-----------------------------------------------------------------------------
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138 // Instruction cache line control
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139
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140 // Invalidate cache lines in the given range without writing to memory.
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141 #define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \
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142 CYG_MACRO_START \
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143 cyg_uint32 _b = _base_; \
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144 cyg_uint32 _s = _size_; \
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145 while (_s > HAL_DCACHE_LINE_SIZE) { \
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146 asm volatile ("ici @(%0,gr0)" \
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147 : \
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148 : "r"(_b) \
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149 ); \
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150 _s -= HAL_DCACHE_LINE_SIZE; \
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151 _b += HAL_DCACHE_LINE_SIZE; \
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152 } \
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153 CYG_MACRO_END
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154
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155 //-----------------------------------------------------------------------------
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156 // Global control of data cache
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157
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158 // Enable the data cache
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159 #define HAL_DCACHE_ENABLE() \
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160 CYG_MACRO_START \
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161 cyg_uint32 mask = _HSR0_DCE; \
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162 asm volatile ( \
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163 "movsg hsr0,gr4\n" \
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164 "\tor gr4,%0,gr4\n" \
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165 "\tmovgs gr4,hsr0\n" \
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166 : \
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167 : "r"(mask) \
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168 : "gr4" /* Clobber list */ \
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169 ); \
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170 CYG_MACRO_END
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171
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172 // Disable the data cache (and invalidate it, required semanitcs)
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173 #define HAL_DCACHE_DISABLE() \
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174 CYG_MACRO_START \
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175 cyg_uint32 mask = ~_HSR0_DCE; \
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176 asm volatile ( \
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177 "movsg hsr0,gr4\n" \
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178 "\tand gr4,%0,gr4\n" \
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179 "\tmovgs gr4,hsr0\n" \
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180 : \
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181 : "r"(mask) \
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182 : "gr4" /* Clobber list */ \
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183 ); \
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184 CYG_MACRO_END
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185
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186 // Query the state of the data cache
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187 #define HAL_DCACHE_IS_ENABLED(_state_) \
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188 CYG_MACRO_START \
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189 register cyg_uint32 reg; \
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190 asm volatile ("movsg hsr0,%0" \
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191 : "=r"(reg) \
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192 : \
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193 ); \
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194 (_state_) = (0 != (_HSR0_DCE & reg)); \
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195 CYG_MACRO_END
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196
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197 // Flush (invalidate) the entire dcache
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198 #define HAL_DCACHE_INVALIDATE_ALL() \
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199 CYG_MACRO_START \
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200 asm volatile ("dcei @(gr4,gr0),1" \
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201 : \
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202 : \
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203 ); \
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204 CYG_MACRO_END
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205
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206 // Synchronize the contents of the cache with memory.
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207 #define HAL_DCACHE_SYNC() \
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208 CYG_MACRO_START \
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209 asm volatile ("dcef @(gr4,gr0),1" \
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210 : \
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211 : \
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212 ); \
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213 CYG_MACRO_END
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214
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215 // Set the data cache refill burst size
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216 //#define HAL_DCACHE_BURST_SIZE(_size_)
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217
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218 // Set the data cache write mode
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219 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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220
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221 #define HAL_DCACHE_WRITETHRU_MODE 0
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222 #define HAL_DCACHE_WRITEBACK_MODE 1
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223
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224 // Get the current writeback mode - or only writeback mode if fixed
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225 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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226 _mode_ = HAL_DCACHE_WRITETHRU_MODE; \
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227 CYG_MACRO_END
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228
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229 // Load the contents of the given address range into the data cache
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230 // and then lock the cache so that it stays there.
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231 //#define HAL_DCACHE_LOCK(_base_, _size_)
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232
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233 // Undo a previous lock operation
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234 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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235
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236 // Unlock entire cache
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237 //#define HAL_DCACHE_UNLOCK_ALL()
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238
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239 //-----------------------------------------------------------------------------
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240 // Data cache line control
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241
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242 // Allocate cache lines for the given address range without reading its
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243 // contents from memory.
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244 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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245
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246 // Write dirty cache lines to memory and invalidate the cache entries
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247 // for the given address range.
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248 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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249 CYG_MACRO_START \
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250 HAL_DCACHE_STORE( _base_ , _size_ ); \
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251 HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
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252 CYG_MACRO_END
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253
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254 // Invalidate cache lines in the given range without writing to memory.
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255 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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256 CYG_MACRO_START \
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257 cyg_uint32 _b = _base_; \
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258 cyg_uint32 _s = _size_; \
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259 while (_s > HAL_DCACHE_LINE_SIZE) { \
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260 asm volatile ("dci @(%0,gr0)" \
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261 : \
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262 : "r"(_b) \
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263 ); \
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264 _s -= HAL_DCACHE_LINE_SIZE; \
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265 _b += HAL_DCACHE_LINE_SIZE; \
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266 } \
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267 CYG_MACRO_END
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268
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269 // Write dirty cache lines to memory for the given address range.
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270 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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271 CYG_MACRO_START \
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272 cyg_uint32 _b = _base_; \
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273 cyg_uint32 _s = _size_; \
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274 while (_s > HAL_DCACHE_LINE_SIZE) { \
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275 asm volatile ("dcf @(%0,gr0)" \
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276 : \
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277 : "r"(_b) \
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278 ); \
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279 _s -= HAL_DCACHE_LINE_SIZE; \
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280 _b += HAL_DCACHE_LINE_SIZE; \
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281 } \
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282 CYG_MACRO_END
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283
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284 // Preread the given range into the cache with the intention of reading
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285 // from it later.
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286 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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287
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288 // Preread the given range into the cache with the intention of writing
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289 // to it later.
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290 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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291
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292 // Allocate and zero the cache lines associated with the given range.
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293 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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294
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295 //-----------------------------------------------------------------------------
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296
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297 #endif // ifndef CYGONCE_HAL_CACHE_H
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298 // End of hal_cache.h