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annotate packages/hal/frv/arch/current/src/frv_stub.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents
children d2c90368aeef
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1 //========================================================================
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2 //
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3 // frv_stub.c
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4 //
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5 // Helper functions for stub, generic to all FUJITSU processors
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6 //
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7 //========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): Red Hat, gthomas
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44 // Contributors: Red Hat, gthomas, jskov, msalter
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45 // Date: 2001-09-16
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46 // Purpose:
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47 // Description: Helper functions for stub, generic to all FUJITSU processors
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48 // Usage:
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //========================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #ifdef CYGPKG_REDBOOT
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57 #include <pkgconf/redboot.h>
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58 #endif
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59
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60 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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61
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62 #include <cyg/hal/hal_stub.h>
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63 #include <cyg/hal/hal_arch.h>
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64 #include <cyg/hal/hal_intr.h>
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65 #include <cyg/hal/hal_cache.h>
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66
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67 #ifndef FALSE
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68 #define FALSE 0
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69 #define TRUE 1
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70 #endif
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71
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72 #ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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73 #include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
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74 #endif
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75
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76 #if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
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77 cyg_uint32 __frv_breakinst = HAL_BREAKINST;
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78 #endif
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79
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80 // Sadly, this doesn't seem to work on the FRV400 either
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81 //#define USE_HW_STEP
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82
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83 #ifdef CYGSEM_HAL_FRV_HW_DEBUG
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84 static inline unsigned __get_dcr(void)
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85 {
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86 unsigned retval;
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87
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88 asm volatile (
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89 "movsg dcr,%0\n"
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90 : "=r" (retval)
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91 : /* no inputs */ );
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92
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93 return retval;
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94 }
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95
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96 static inline void __set_dcr(unsigned val)
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97 {
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98 asm volatile (
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99 "movgs %0,dcr\n"
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100 : /* no outputs */
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101 : "r" (val) );
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102 }
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103
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104 #endif
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105
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106 /* Given a trap value TRAP, return the corresponding signal. */
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107
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108 int __computeSignal (unsigned int trap_number)
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109 {
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110 // should also catch CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION here but we
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111 // can't tell the different between a real one and a breakpoint :-(
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112 switch (trap_number) {
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113 // Interrupts
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114 case CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1 ... CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15:
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115 return SIGINT;
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116 case CYGNUM_HAL_VECTOR_INSTR_ACCESS_MMU_MISS:
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117 case CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR:
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118 case CYGNUM_HAL_VECTOR_INSTR_ACCESS_EXCEPTION:
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119 case CYGNUM_HAL_VECTOR_MEMORY_ADDRESS_NOT_ALIGNED:
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120 case CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR:
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121 case CYGNUM_HAL_VECTOR_DATA_ACCESS_MMU_MISS:
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122 case CYGNUM_HAL_VECTOR_DATA_ACCESS_EXCEPTION:
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123 case CYGNUM_HAL_VECTOR_DATA_STORE_ERROR:
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124 return SIGBUS;
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125 case CYGNUM_HAL_VECTOR_PRIVELEDGED_INSTRUCTION:
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126 case CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION:
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127 case CYGNUM_HAL_VECTOR_REGISTER_EXCEPTION:
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128 case CYGNUM_HAL_VECTOR_FP_DISABLED:
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129 case CYGNUM_HAL_VECTOR_MP_DISABLED:
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130 case CYGNUM_HAL_VECTOR_FP_EXCEPTION:
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131 case CYGNUM_HAL_VECTOR_MP_EXCEPTION:
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132 case CYGNUM_HAL_VECTOR_DIVISION_EXCEPTION:
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133 case CYGNUM_HAL_VECTOR_COMMIT_EXCEPTION:
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134 case CYGNUM_HAL_VECTOR_COMPOUND_EXCEPTION:
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135 return SIGILL;
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136 default:
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137 return SIGTRAP;
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138 }
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139 }
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140
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141
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142 /* Return the trap number corresponding to the last-taken trap. */
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143 int __get_trap_number (void)
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144 {
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145 // The vector is not not part of the GDB register set so get it
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146 // directly from the save context.
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147 return _hal_registers->vector;
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148 }
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149
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150
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151 #if defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
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152 int __is_bsp_syscall(void)
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153 {
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154 // Might want to be more specific here
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155 return (_hal_registers->vector == CYGNUM_HAL_VECTOR_SYSCALL);
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156 }
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157 #endif // defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
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158
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159 /* Set the currently-saved pc register value to PC. */
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160
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161 void set_pc (target_register_t pc)
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162 {
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163 put_register (PC, pc);
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164 }
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165
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166
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167 /*----------------------------------------------------------------------
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168 * Single-step support
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169 */
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170
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171 /* Set things up so that the next user resume will execute one instruction.
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172 This may be done by setting breakpoints or setting a single step flag
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173 in the saved user registers, for example. */
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174
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175 #ifndef CYGSEM_HAL_FRV_HW_DEBUG
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176 #if CYGINT_HAL_FRV_ARCH_FR400 == 1
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177 #define VLIW_DEPTH 2
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178 #endif
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179 #if CYGINT_HAL_FRV_ARCH_FR500 == 1
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180 #define VLIW_DEPTH 4
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181 #endif
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182 /*
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183 * Structure to hold opcodes hoisted when breakpoints are
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184 * set for single-stepping or async interruption.
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185 */
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186 struct _bp_save {
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187 unsigned long *addr;
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188 unsigned long opcode;
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189 };
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190
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191 /*
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192 * We single-step by setting breakpoints.
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193 *
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194 * This is where we save the original instructions.
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195 */
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196 static struct _bp_save step_bp[VLIW_DEPTH+1];
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197
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198 //**************************************************************
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199 //************ CAUTION!! ***************************************
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200 //**************************************************************
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201 //
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202 // Attempt to analyze the current instruction. This code is not
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203 // perfect in the case of VLIW sequences, although it's close.
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204 // Consider these sequences:
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205 //
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206 // ldi.p @(gr5,0),gr4
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207 // jmpl @(gr4,gr0)
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208 // and
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209 //
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210 // ldi.p @(gr5,0),gr4
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211 // add.p gr6,gr7,gr8
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212 // jmpl @(gr4,gr0)
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213 //
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214 // In these cases, the only way to effectively calculate the
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215 // target address (of the jump) would be to simulate the actions
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216 // of the pipelined instructions which come beforehand.
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217 //
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218 // Of course, this only affects single stepping through a VLIW
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219 // sequence which contains such pipelined effects and a branch.
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220 // Hopefully this is rare.
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221 //
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222 // Note: testing of the above sequence on the FR400 yielded an
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223 // illegal instruction (invalid VLIW sequence), so this may not
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224 // turn out to be a problem in practice, just theory.
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225 //
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226 //**************************************************************
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227 //**************************************************************
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228
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229 static int
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230 _analyze_instr(unsigned long pc, unsigned long *targ,
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231 unsigned long *next, int *is_vliw)
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232 {
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233 unsigned long opcode;
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234 int n, is_branch = 0;
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235
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236 opcode = *(unsigned long *)pc;
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237 switch ((opcode >> 18) & 0x7f) {
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238 case 6:
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239 case 7:
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240 /* bcc, fbcc */
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241 is_branch = 1;
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242 n = (int)(opcode << 16);
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243 n >>= 16;
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244 *targ = pc + n*4;
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245 pc += 4;
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246 break;
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247 case 12:
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248 /* jmpl */
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249 n = (int)(get_register((opcode>>12)&63));
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250 n += (int)(get_register(opcode&63));
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251 pc = n;
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252 break;
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253 case 13:
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254 /* jmpil */
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255 n = (int)(get_register((opcode>>12)&63));
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256 n += (((int)(opcode << 20)) >> 20);
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257 pc = n;
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258 break;
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259 case 15:
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260 /* call */
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261 n = (opcode >> 25) << 18;
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262 n |= (opcode & 0x3ffff);
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263 n <<= 8;
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264 n >>= 8;
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265 pc += n*4;
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266 break;
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267 case 14:
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268 /* ret */
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269 is_branch = 1;
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270 *targ = get_register(LR);
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271 pc += 4;
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272 break;
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273 default:
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274 pc += 4;
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275 break;
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276 }
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277 *next = pc;
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278 *is_vliw = (opcode & 0x80000000) == 0;
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279 return is_branch;
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280 }
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281 #endif
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282
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283 void __single_step (void)
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284 {
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285 #ifdef CYGSEM_HAL_FRV_HW_DEBUG
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286 __set_dcr(__get_dcr() | _DCR_SE);
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287 diag_printf("Setting single step - DCR: %x\n", __get_dcr());
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288 #else
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289 unsigned long pc, targ, next_pc;
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290 int i, is_branch = 0;
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291 int is_vliw;
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292
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293 for (i = 0; i < VLIW_DEPTH+1; i++) {
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294 step_bp[i].addr = NULL;
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295 }
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296
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297 pc = get_register(PC);
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298 i = 1;
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299 while (i < (VLIW_DEPTH+1)) {
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300 is_branch = _analyze_instr(pc, &targ, &next_pc, &is_vliw);
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301 if (is_branch && next_pc != targ) {
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302 step_bp[i].addr = (unsigned long *)targ;
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303 step_bp[i].opcode = *(unsigned long *)targ;
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304 *(unsigned long *)targ = HAL_BREAKINST;
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305 HAL_DCACHE_STORE(targ, 4);
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306 HAL_ICACHE_INVALIDATE(targ, 4);
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307 }
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308 if (is_vliw) {
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309 pc += 4;
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310 i++;
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311 } else {
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312 break;
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313 }
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314 }
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315 step_bp[0].addr = (unsigned long *)next_pc;
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316 step_bp[0].opcode = *(unsigned long *)next_pc;
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317 *(unsigned long *)next_pc = HAL_BREAKINST;
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318 HAL_DCACHE_STORE(next_pc, 4);
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319 HAL_ICACHE_INVALIDATE(next_pc, 4);
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320 #endif
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321 }
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322
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323 /* Clear the single-step state. */
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324
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325 void __clear_single_step (void)
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326 {
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327 #ifdef CYGSEM_HAL_FRV_HW_DEBUG
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328 __set_dcr(__get_dcr() & ~_DCR_SE);
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329 #else
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330 struct _bp_save *p;
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331 int i;
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332
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333 for (i = 0; i < VLIW_DEPTH+1; i++) {
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334 p = &step_bp[i];
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335 if (p->addr) {
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336 *(p->addr) = p->opcode;
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337 HAL_DCACHE_STORE((cyg_uint32)p->addr, 4);
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338 HAL_ICACHE_INVALIDATE((cyg_uint32)p->addr, 4);
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339 p->addr = NULL;
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340 }
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341 }
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342 #endif
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343 }
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344
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345 void __install_breakpoints (void)
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346 {
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347 #if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
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348 /* Install the breakpoints in the breakpoint list */
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349 __install_breakpoint_list();
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350 #endif
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351 }
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352
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353 void __clear_breakpoints (void)
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354 {
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355 #if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
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356 __clear_breakpoint_list();
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357 #endif
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358 }
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359
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360 /* If the breakpoint we hit is in the breakpoint() instruction, return a
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361 non-zero value. */
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362
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363 int
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364 __is_breakpoint_function ()
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365 {
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366 return get_register (PC) == (target_register_t)&_breakinst;
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367 }
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368
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369
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370 /* Skip the current instruction. Since this is only called by the
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371 stub when the PC points to a breakpoint or trap instruction,
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372 we can safely just skip 4. */
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373
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374 void __skipinst (void)
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375 {
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376 unsigned long pc = get_register(PC);
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377
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378 pc += 4;
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379 put_register(PC, pc);
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380 }
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381
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382 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS