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annotate packages/hal/h8300/arch/current/include/hal_intr.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 #ifndef CYGONCE_HAL_HAL_INTR_H
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2 #define CYGONCE_HAL_HAL_INTR_H
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3 //==========================================================================
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4 //
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5 // hal_intr.h
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6 //
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7 // HAL Interrupt and clock support
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8 //
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9 //==========================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 // at http://sources.redhat.com/ecos/ecos-license
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): yoshinori sato
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46 // Contributors: yoshinori sato
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47 // Date: 2002-02-13
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48 // Purpose: Define Interrupt support
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // interrupts and the clock.
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51 // Usage:
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52 // #include <cyg/hal/hal_intr.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //==========================================================================
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59
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60 #include <pkgconf/hal.h>
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61
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62 #include <cyg/infra/cyg_type.h>
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63 #include <cyg/hal/hal_io.h>
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64
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65 #include <cyg/hal/var_intr.h>
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66
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67 //--------------------------------------------------------------------------
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68 // Static data used by HAL
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69
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70 // ISR tables
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71 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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72 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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73 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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74
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75 // VSR table
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76 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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77
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78 //--------------------------------------------------------------------------
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79 // Default ISR
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80 // The #define is used to test whether this routine exists, and to allow
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81 // us to call it.
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82
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83 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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84
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85 #define HAL_DEFAULT_ISR hal_default_isr
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86
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87 //--------------------------------------------------------------------------
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88 // Interrupt state storage
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89
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90 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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91
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92 //--------------------------------------------------------------------------
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93
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94 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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95
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96 // Routine to execute DSRs using separate interrupt stack
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97 externC void hal_interrupt_stack_call_pending_DSRs(void);
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98 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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99 hal_interrupt_stack_call_pending_DSRs()
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100
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101 // these are offered solely for stack usage testing
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102 // if they are not defined, then there is no interrupt stack.
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103 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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104 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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105 // use them to declare these extern however you want:
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106 // extern char HAL_INTERRUPT_STACK_BASE[];
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107 // extern char HAL_INTERRUPT_STACK_TOP[];
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108 // is recommended
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109
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110 #endif
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111
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112 //--------------------------------------------------------------------------
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113 // Interrupt control macros
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114
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115 #define HAL_DISABLE_INTERRUPTS(_old_) \
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116 asm volatile ( \
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117 "sub.l er0,er0\n\t" \
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118 "stc ccr,r0l\n\t" \
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119 "orc #0x80,ccr\n\t" \
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120 "and.b #0xc0,r0l\n\t" \
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121 "mov.l er0,%0" \
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122 : "=r"(_old_) \
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123 : \
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124 : "er0" \
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125 );
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126
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127 #define HAL_ENABLE_INTERRUPTS() \
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128 asm volatile ( \
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129 "andc #0x3f,ccr" \
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130 );
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131
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132 #define HAL_RESTORE_INTERRUPTS(_old_) \
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133 asm volatile ( \
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134 "mov.l %0,er0\n\t" \
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135 "and.b #0xc0,r0l\n\t" \
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136 "stc ccr,r0h\n\t" \
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137 "and.b #0x3f,r0h\n\t" \
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138 "or.b r0h,r0l\n\t" \
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139 "ldc r0l,ccr" \
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140 : \
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141 : "r"(_old_) \
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142 : "er0" \
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143 );
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144
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145 #define HAL_QUERY_INTERRUPTS(_old_) \
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146 asm volatile ( \
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147 "sub.l er0,er0\n\t" \
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148 "stc ccr,r0l\n\t" \
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149 "and.b #0xc0,r0l\n\t" \
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150 "mov.l er0,%0" \
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151 : "=r"(_old_) \
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152 );
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153
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154 #ifndef HAL_TRANSLATE_VECTOR
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155
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156 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
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157
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158 #endif
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159
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160 //--------------------------------------------------------------------------
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161 // Interrupt and VSR attachment macros
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162
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163 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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164 CYG_MACRO_START \
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165 cyg_uint32 _index_; \
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166 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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167 \
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168 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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169 (_state_) = 0; \
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170 else \
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171 (_state_) = 1; \
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172 CYG_MACRO_END
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173
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174 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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175 CYG_MACRO_START \
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176 cyg_uint32 _index_; \
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177 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
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178 \
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179 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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180 { \
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181 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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182 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
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183 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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184 } \
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185 CYG_MACRO_END
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186
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187 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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188 CYG_MACRO_START \
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189 cyg_uint32 _index_; \
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190 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
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191 \
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192 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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193 { \
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194 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
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195 hal_interrupt_data[_index_] = 0; \
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196 hal_interrupt_objects[_index_] = 0; \
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197 } \
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198 CYG_MACRO_END
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199
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200 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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201 *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
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202
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203
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204 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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205 if( _poldvsr_ != NULL ) \
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206 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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207 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;
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208
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209
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210 //--------------------------------------------------------------------------
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211 // Interrupt controller access
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212 // Read interrupt control registers back after writing to them. This
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213 // ensures that the written value is not sitting in the store buffers
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214 // when interrupts are re-enabled.
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215
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216 #define HAL_INTERRUPT_MASK( _vector_ ) \
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217 hal_interrupt_mask( _vector_ )
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218
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219 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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220 hal_interrupt_unmask( _vector_ )
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221
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222 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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223 hal_interrupt_acknowledge( _vector_ )
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224
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225 #if !defined(HAL_INTERRUPT_CONFIGURE)
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226
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227 #error HAL_INTERRUPT_CONFIGURE not defined by variant
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228
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229 #endif
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230
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231 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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232 hal_interrupt_set_level( _vector_, _level_ )
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233
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234
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235 externC void hal_interrupt_mask(int vector);
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236 externC void hal_interrupt_unmask(int vector);
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237 externC void hal_interrupt_acknowledge(int vector);
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238 externC void hal_interrupt_set_level(int vector,int level);
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239 //--------------------------------------------------------------------------
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240 // Clock control.
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241 // This is almost all handled in the var_intr.h.
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242
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243 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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244 #define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
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245 #endif
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246
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247 //--------------------------------------------------------------------------
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248 #endif // ifndef CYGONCE_HAL_HAL_INTR_H
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249 // EOF hal_intr.h