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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // var_misc.c
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4 //
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5 // HAL CPU variant miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): nickg
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44 // Contributors: nickg, jlarmour
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45 // Date: 1999-01-21
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46 // Purpose: HAL miscellaneous functions
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47 // Description: This file contains miscellaneous functions provided by the
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48 // HAL.
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //========================================================================*/
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/infra/cyg_type.h> // Base types
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57 #include <cyg/infra/cyg_trac.h> // tracing macros
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58 #include <cyg/infra/cyg_ass.h> // assertion macros
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59 #include <cyg/hal/var_arch.h>
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60 #include <cyg/hal/var_intr.h>
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61 #include <cyg/hal/hal_io.h>
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62
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63 /*------------------------------------------------------------------------*/
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64 /* Variant specific initialization routine. */
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65
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66 void hal_variant_init(void)
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67 {
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68 }
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69
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70 struct int_regs {
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71 CYG_BYTE *ier;
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72 CYG_BYTE *isr;
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73 CYG_BYTE mask;
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74 CYG_BYTE status;
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75 };
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76
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77 #define REGS_DEF(ier,isr,mask,status) \
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78 {(CYG_BYTE *)ier,(CYG_BYTE *)isr,mask,status}
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79
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80 struct int_regs interrupt_registers[]= {
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81 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x01,0x01),
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82 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x02,0x02),
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83 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x04,0x04),
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84 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x08,0x08),
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85 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x10,0x10),
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86 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x20,0x20),
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87 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x40,0x40),
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88 REGS_DEF(CYGARC_IER,CYGARC_ISR,0x80,0x80),
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89 REGS_DEF(CYGARC_TCSR,CYGARC_TCSR,0x20,0x80),
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90 REGS_DEF(CYGARC_RTMCSR,CYGARC_RTMCSR,0x40,0x80),
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91 REGS_DEF(NULL,NULL,0,0),
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92 REGS_DEF(CYGARC_ADCSR,CYGARC_ADCSR,0x40,0x80),
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93 REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x10,0x01),
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94 REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x10,0x01),
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95 REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x10,0x01),
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96 REGS_DEF(NULL,NULL,0,0),
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97 REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x20,0x02),
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98 REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x20,0x02),
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99 REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x20,0x02),
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100 REGS_DEF(NULL,NULL,0,0),
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101 REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x40,0x04),
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102 REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x40,0x04),
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103 REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x40,0x04),
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104 REGS_DEF(NULL,NULL,0,0),
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105 REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x40,0x40),
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106 REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x80,0x80),
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107 REGS_DEF(CYGARC_8TCR1,CYGARC_8TCSR1,0xC0,0xC0),
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108 REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x20,0x20),
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109 REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x40,0x40),
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110 REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x80,0x80),
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111 REGS_DEF(CYGARC_8TCR3,CYGARC_8TCSR3,0xC0,0xC0),
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112 REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x20,0x20),
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113 REGS_DEF(CYGARC_DTCR0A,CYGARC_DTCR0A,0x08,0x80),
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114 REGS_DEF(CYGARC_DTCR0B,CYGARC_DTCR0B,0x08,0x80),
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115 REGS_DEF(CYGARC_DTCR1A,CYGARC_DTCR1A,0x08,0x80),
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116 REGS_DEF(CYGARC_DTCR1B,CYGARC_DTCR1B,0x08,0x80),
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117 REGS_DEF(NULL,NULL,0,0),
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118 REGS_DEF(NULL,NULL,0,0),
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119 REGS_DEF(NULL,NULL,0,0),
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120 REGS_DEF(NULL,NULL,0,0),
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121 REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x30),
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122 REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x40),
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123 REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x80,0x80),
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124 REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x04,0x04),
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125 REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x30),
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126 REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x40),
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127 REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x80,0x80),
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128 REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x04,0x04),
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129 REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x30),
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130 REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x40),
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131 REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x80,0x80),
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132 REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x04,0x04)
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133 };
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134
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135 void
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136 hal_interrupt_mask(int vector)
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137 {
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138 CYG_BYTE ier;
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139 struct int_regs *regs=&interrupt_registers[vector-12];
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140 if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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141 HAL_READ_UINT8(CYGARC_TCSR,ier);
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142 ier &= ~0x20;
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143 HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
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144 } else {
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145 if ((vector > 12) && regs->ier) {
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146 HAL_READ_UINT8(regs->ier,ier);
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147 ier &= ~(regs->mask);
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148 HAL_WRITE_UINT8(regs->ier,ier);
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149 } else {
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150 CYG_FAIL("Unknown interrupt vector");
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151 }
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152 }
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153 }
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154
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155 void
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156 hal_interrupt_unmask(int vector)
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157 {
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158 CYG_BYTE ier;
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159 struct int_regs *regs=&interrupt_registers[vector-12];
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160 if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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161 HAL_READ_UINT8(CYGARC_TCSR,ier);
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162 ier |= 0x20;
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163 HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
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164 } else {
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165 if ((vector > 12) && regs->ier) {
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166 HAL_READ_UINT8(regs->ier,ier);
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167 ier |= regs->mask;
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168 HAL_WRITE_UINT8(regs->ier,ier);
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169 } else {
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170 CYG_FAIL("Unknown interrupt vector");
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171 }
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172 }
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173 }
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174
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175 void
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176 hal_interrupt_acknowledge(int vector)
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177 {
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178 CYG_BYTE isr;
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179 struct int_regs *regs=&interrupt_registers[vector-12];
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180 if (vector >= CYGNUM_HAL_INTERRUPT_DEND0A &&
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181 vector <= CYGNUM_HAL_INTERRUPT_DEND1B)
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182 return;
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183 if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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184 HAL_READ_UINT8(CYGARC_TCSR,isr);
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185 isr &= ~0x80;
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186 HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | isr);
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187 } else {
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188 if ((vector > 12) && regs->isr) {
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189 HAL_READ_UINT8(regs->isr,isr);
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190 isr &= ~(regs->status);
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191 HAL_WRITE_UINT8(regs->isr,isr);
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192 } else {
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193 CYG_FAIL("Unknown interrupt vector");
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194 }
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195 }
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196 }
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197
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198 const short priority_table[]={
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199 7, 6, 5, 5, 4, 4,-1,-1,
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200 3, 3,-1, 3, 2, 2, 2, 2,
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201 1, 1, 1, 1, 0, 0, 0, 0,
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202 15,15,15,15,14,14,14,14,
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203 13,13,13,13,-1,-1,-1,-1,
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204 11,11,11,11,10,10,10,10,
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205 9,9,9,9
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206 };
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207
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208 void
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209 hal_interrupt_set_level(int vector,int level)
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210 {
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211 CYG_BYTE *ipr;
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212 CYG_BYTE ipr_mask;
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213 int priority = priority_table[vector-12];
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214 ipr = (CYG_BYTE *)CYGARC_IPRA + ((priority & 0xf8) >> 3);
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215 if (priority>=0) {
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216 ipr_mask = 1 << (priority & 0x07);
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217 if (level == 0) {
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218 *ipr &= ~ipr_mask;
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219 } else {
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220 *ipr |= ipr_mask;
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221 }
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222 } else {
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223 CYG_FAIL("Unknown interrupt vector");
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224 }
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225 }
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226
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227 void
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228 hal_interrupt_configure(int vector,int level,int up)
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229 {
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230 cyg_uint8 iscr,mask;
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231 if (vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 &&
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232 vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_7) {
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233 mask = 1 << (vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0);
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234 HAL_READ_UINT8(CYGARC_ISCR,iscr);
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235 if (level) {
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236 iscr &= ~mask;
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237 }
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238 if (up) {
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239 iscr |= mask;
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240 }
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241 CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
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242 HAL_WRITE_UINT8(CYGARC_ISCR,iscr);
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243 } else {
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244 CYG_FAIL("Unhandled interrupt vector");
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245 }
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246 }
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247
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248 /*------------------------------------------------------------------------*/
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249 /* End of var_misc.c */