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annotate packages/hal/mips/atlas/current/include/plf_io.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents b939e9cada46
children d2c90368aeef
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1 #ifndef CYGONCE_PLF_IO_H
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2 #define CYGONCE_PLF_IO_H
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3
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4 //=============================================================================
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5 //
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6 // plf_io.h
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7 //
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8 // Platform specific IO support
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9 //
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10 //=============================================================================
208
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
156
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): dmoseley
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47 // Contributors: dmoseley
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48 // Date: 2000-06-06
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49 // Purpose: Atlas platform IO support
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50 // Description:
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51 // Usage: #include <cyg/hal/plf_io.h>
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52 //
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53 //####DESCRIPTIONEND####
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54 //
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55 //=============================================================================
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56
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57 #include <pkgconf/hal.h>
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58 #include <cyg/hal/hal_misc.h>
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59
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60 #ifdef __ASSEMBLER__
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61 #define HAL_REG(x) x
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62 #else
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63 #define HAL_REG(x) (volatile CYG_WORD *)(x)
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64 #endif
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65
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66 //-----------------------------------------------------------------------------
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67
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68 /* Atlas Memory Definitions */
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69 #define HAL_ATLAS_RAM_BASE 0x00000000
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70 #define HAL_ATLAS_PCI_MEM0_BASE 0x08000000
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71 #define HAL_ATLAS_PCI_MEM0_SIZE 0x08000000 // 128 MB
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72 #define HAL_ATLAS_PCI_MEM1_BASE 0x10000000
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73 #define HAL_ATLAS_PCI_MEM1_SIZE 0x08000000 // 128 MB
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74 #define HAL_ATLAS_PCI_IO_BASE 0x18000000
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75 #define HAL_ATLAS_PCI_IO_SIZE 0x03E00000 // 62 MB
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76 #define HAL_ATLAS_CONTROLLER_BASE 0x1BE00000
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77 #define HAL_ATLAS_CONTROLLER_BASE_ISD_CONFIG (HAL_ATLAS_CONTROLLER_BASE >> 21)
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78 #define HAL_ATLAS_FLASH_BASE 0x1C000000
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79 #define HAL_ATLAS_FLASH_SIZE SZ_32M
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80 #define HAL_ATLAS_MAX_BANKSIZE SZ_512M
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81
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82 #define HAL_ATLAS_NULL_DEVNUM 0x0
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83 #define HAL_ATLAS_SAA9730_DEVNUM 0x9800
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84 #define HAL_ATLAS_MEMERROR 1
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85
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86 /* Atlas Registers */
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87 #define HAL_ATLAS_REGISTER_BASE 0xBF000000
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88
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89 #define HAL_ATLAS_INTBASE HAL_ATLAS_REGISTER_BASE
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90
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91 #define HAL_ATLAS_INTRAW_OFFSET 0x00000000
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92 #define HAL_ATLAS_INTSETEN_OFFSET 0x00000008
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93 #define HAL_ATLAS_INTRSTEN_OFFSET 0x00000010
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94 #define HAL_ATLAS_INTENABLE_OFFSET 0x00000018
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95 #define HAL_ATLAS_INTSTATUS_OFFSET 0x00000020
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96
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97 #define HAL_ATLAS_INTRAW HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTRAW_OFFSET)
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98 #define HAL_ATLAS_INTSETEN HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTSETEN_OFFSET)
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99 #define HAL_ATLAS_INTRSTEN HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTRSTEN_OFFSET)
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100 #define HAL_ATLAS_INTENABLE HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTENABLE_OFFSET)
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101 #define HAL_ATLAS_INTSTATUS HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTSTATUS_OFFSET)
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102
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103
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104 #define HAL_ATLAS_NMISTATUS_OFFSET 0x00000024
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105 #define HAL_ATLAS_NMIACK_OFFSET 0x00000104
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106 #define HAL_ATLAS_SOFTRES_OFFSET 0x00000500
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107 #define HAL_ATLAS_BRKRES_OFFSET 0x00000508
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108 #define HAL_ATLAS_REVISION_OFFSET 0x00C00010
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109
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110 #define HAL_ATLAS_NMISTATUS HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_NMISTATUS_OFFSET)
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111 #define HAL_ATLAS_NMIACK HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_NMIACK_OFFSET)
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112 #define HAL_ATLAS_SOFTRES HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_SOFTRES_OFFSET)
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113 #define HAL_ATLAS_BRKRES HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_BRKRES_OFFSET)
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114 #define HAL_ATLAS_REVISION HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_REVISION_OFFSET)
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115
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116 /* Atlas NMI controller fields */
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117 #define HAL_ATLAS_NMISTATUS_FLAG 0x00000001
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118 #define HAL_ATLAS_NMIACK_FLAG 0x00000001
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119
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120 /* Atlas softreset fields */
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121 #define HAL_ATLAS_GORESET 0x42
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122
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123 /* Atlas brkreset fields */
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124 #define HAL_ATLAS_BRKRES_DEFAULT_VALUE 0xA
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125
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126 /* Galileo Registers */
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127 #define HAL_GALILEO_REGISTER_BASE 0xB4000000
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128 #define HAL_GALILEO_PCI0_MEM0_BASE 0xB2000000
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129
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130 #define HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET 0x0
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131 #define HAL_GALILEO_INT_SPACE_DECODE_OFFSET 0x68
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132 #define HAL_GALILEO_CS3_HIGH_DECODE_OFFSET 0x43c
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133 #define HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET 0x440
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134 #define HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET 0x444
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135
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136 /* Galileo CPU Interface config fields */
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137 #define HAL_GALILEO_BYTE_SWAP (BIT16 | BIT0)
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138
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139 #define HAL_GALILEO_CACHEOPMAP_MASK 0x000001FF
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140 #define HAL_GALILEO_CACHEPRES_MASK 0x00000200
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141 #define HAL_GALILEO_WRITEMODE_MASK 0x00000800
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142 #define HAL_GALILEO_ENDIAN_MASK 0x00001000
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143 #define HAL_GALILEO_R5KL2_MASK 0x00004000
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144 #define HAL_GALILEO_EXT_HIT_DELAY_MASK 0x00008000
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145 #define HAL_GALILEO_CPU_WRITERATE_MASK 0x00010000
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146 #define HAL_GALILEO_STOP_RETRY_MASK 0x00020000
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147 #define HAL_GALILEO_MULTI_GT_MASK 0x00040000
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148 #define HAL_GALILEO_SYSADCVALID_MASK 0x00080000
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149
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150 /* Galileo Memory Controller registers */
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151 #define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20
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152 #define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14
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153 #define HAL_GALILEO_CPU_DECODE_SHIFT 21
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154 #define HAL_GALILEO_DEV_DECODE_SHIFT 20
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155 #define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10
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156 #define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6
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157 #define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3
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158 #define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0
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159 #define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11
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160 #define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5
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161 #define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8
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162 #define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15
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163 #define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31
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164 #define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04
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165 #define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C
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166 #define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14
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167 #define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2
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168 #define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4
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169 #define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100
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170 #define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800
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171 #define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff
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172
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173 #define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c
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174 #define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454
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175 #define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448
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176
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177 #define HAL_GALILEO_SCS10_LD_OFFSET 0x008
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178 #define HAL_GALILEO_SCS10_HD_OFFSET 0x010
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179 #define HAL_GALILEO_SCS32_LD_OFFSET 0x018
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180 #define HAL_GALILEO_SCS32_HD_OFFSET 0x020
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181 #define HAL_GALILEO_CS20_LD_OFFSET 0x028
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182 #define HAL_GALILEO_CS20_HD_OFFSET 0x030
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183 #define HAL_GALILEO_PCIIO_LD_OFFSET 0x048
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184 #define HAL_GALILEO_PCIIO_HD_OFFSET 0x050
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185 #define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058
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186 #define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060
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187 #define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080
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188 #define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088
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189 #define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090
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190 #define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098
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191 #define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0
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192 #define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8
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193 #define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0
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194 #define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8
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195 #define HAL_GALILEO_SCS0_LD_OFFSET 0x400
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196 #define HAL_GALILEO_SCS0_HD_OFFSET 0x404
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197 #define HAL_GALILEO_SCS1_LD_OFFSET 0x408
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198 #define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
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199 #define HAL_GALILEO_SCS2_LD_OFFSET 0x410
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200 #define HAL_GALILEO_SCS2_HD_OFFSET 0x414
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201 #define HAL_GALILEO_SCS3_LD_OFFSET 0x418
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202 #define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
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203 #define HAL_GALILEO_CS0_LD_OFFSET 0x420
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204 #define HAL_GALILEO_CS0_HD_OFFSET 0x424
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205 #define HAL_GALILEO_CS1_LD_OFFSET 0x428
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206 #define HAL_GALILEO_CS1_HD_OFFSET 0x42c
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207 #define HAL_GALILEO_CS2_LD_OFFSET 0x430
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208 #define HAL_GALILEO_CS2_HD_OFFSET 0x434
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209
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210 // GALILEO PCI Internal
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211 #define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00
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212 #define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04
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213 #define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08
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214 #define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c
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215 #define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10
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216 #define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14
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217 #define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c
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218 # define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0)
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219 # define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1)
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220 # define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2)
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221 # define HAL_GALILEO_BAR_ENA_IO (1 << 3)
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222 # define HAL_GALILEO_BAR_ENA_MEM (1 << 4)
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223 # define HAL_GALILEO_BAR_ENA_CS3 (1 << 5)
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224 # define HAL_GALILEO_BAR_ENA_CS20 (1 << 6)
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225 # define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7)
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226 # define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8)
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227 #define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8
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228 # define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31)
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229 #define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc
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230
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231 // GALILEO Interrupts
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232 #define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18
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233 # define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0)
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234 # define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1)
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235 # define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2)
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236 # define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3)
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237 # define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4)
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238 # define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5)
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239 # define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6)
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240 # define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7)
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241 # define HAL_GALILEO_IRQCAUSE_T0 (1 << 8)
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242 # define HAL_GALILEO_IRQCAUSE_T1 (1 << 9)
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243 # define HAL_GALILEO_IRQCAUSE_T2 (1 << 10)
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244 # define HAL_GALILEO_IRQCAUSE_T3 (1 << 11)
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245 # define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12)
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246 # define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13)
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247 # define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14)
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248 # define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)
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249 # define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)
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250 # define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)
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251 # define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)
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252 # define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)
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253 # define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)
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254 # define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)
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255 # define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)
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256 #define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98
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257 #define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c
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258 #define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c
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259
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260 #define HAL_SAA9730_I2CSC_I2CCC_6400 0x500
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261 #define HAL_SAA9730_I2CTFR_ATTR0_START 0xC
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262 #define HAL_SAA9730_I2CTFR_ATTR2_START 0xC0
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263 #define HAL_SAA9730_I2CTFR_ATTR2_STOP 0x40
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264 #define HAL_SAA9730_I2CTFR_ATTR1_CONT 0x20
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265 #define HAL_SAA9730_I2CTFR_OFFSET 0x2400
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266 #define HAL_SAA9730_I2CSC_OFFSET 0x2404
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267 #define HAL_SAA9730_SYSRESET_OFFSET 0x4020
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268 #define HAL_SAA9730_SYSRESET_ALL 0xdeae
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269
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270 #define HAL_SPD_GET_NUM_ROW_BITS 3
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271 #define HAL_SPD_GET_NUM_COL_BITS 4
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272 #define HAL_SPD_GET_NUM_MODULE_BANKS 5
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273 #define HAL_SPD_GET_CONFIG_TYPE 11
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274 #define HAL_SPD_GET_REFRESH_RATE 12
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275 #define HAL_SPD_GET_SDRAM_WIDTH 13
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276 #define HAL_SPD_GET_ERROR_CHECK_WIDTH 14
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277 #define HAL_SPD_GET_BURST_LENGTH 16
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278 #define HAL_SPD_GET_NUM_DEVICE_BANKS 17
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279 #define HAL_SPD_GET_CAS_LAT 18
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280 #define HAL_SPD_GET_ROW_DENSITY 31
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281 #define HAL_SPD_CONFIG_TYPE_PARITY BIT0
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282 #define HAL_SPD_CONFIG_TYPE_ECC BIT1
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283 #define HAL_SPD_REFRESH_RATE_125 5
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284 #define HAL_SPD_REFRESH_RATE_62_5 4
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285 #define HAL_SPD_REFRESH_RATE_31_3 3
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286 #define HAL_SPD_REFRESH_RATE_15_625 0
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287 #define HAL_SPD_REFRESH_RATE_7_8 2
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288 #define HAL_SPD_REFRESH_RATE_3_9 1
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289
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290 #define HAL_SPD_REFRESH_COUNTER_125 (125*2)
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291 #define HAL_SPD_REFRESH_COUNTER_62_5 (62*2)
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292 #define HAL_SPD_REFRESH_COUNTER_31_3 (31*2)
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293 #define HAL_SPD_REFRESH_COUNTER_15_625 (15*2)
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294 #define HAL_SPD_REFRESH_COUNTER_7_8 (7*2)
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295 #define HAL_SPD_REFRESH_COUNTER_3_9 (3*2)
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296
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297 /* Atlas Display Registers */
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298 #define HAL_DISPLAY_BASE (HAL_ATLAS_REGISTER_BASE + 0x400)
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299
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300 #define HAL_DISPLAY_LEDGREEN_OFFSET 0x00
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301 #define HAL_DISPLAY_LEDBAR_OFFSET 0x08
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302 #define HAL_DISPLAY_ASCIIWORD_OFFSET 0x10
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303 #define HAL_DISPLAY_ASCIIPOS0_OFFSET 0x18
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304 #define HAL_DISPLAY_ASCIIPOS1_OFFSET 0x20
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305 #define HAL_DISPLAY_ASCIIPOS2_OFFSET 0x28
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306 #define HAL_DISPLAY_ASCIIPOS3_OFFSET 0x30
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307 #define HAL_DISPLAY_ASCIIPOS4_OFFSET 0x38
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308 #define HAL_DISPLAY_ASCIIPOS5_OFFSET 0x40
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309 #define HAL_DISPLAY_ASCIIPOS6_OFFSET 0x48
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310 #define HAL_DISPLAY_ASCIIPOS7_OFFSET 0x50
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311
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312 #define HAL_DISPLAY_LEDGREEN HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDGREEN_OFFSET)
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313 #define HAL_DISPLAY_LEDBAR HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDBAR_OFFSET)
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314 #define HAL_DISPLAY_ASCIIWORD HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIWORD_OFFSET)
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315 #define HAL_DISPLAY_ASCIIPOS0 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS0_OFFSET)
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316 #define HAL_DISPLAY_ASCIIPOS1 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS1_OFFSET)
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317 #define HAL_DISPLAY_ASCIIPOS2 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS2_OFFSET)
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318 #define HAL_DISPLAY_ASCIIPOS3 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS3_OFFSET)
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319 #define HAL_DISPLAY_ASCIIPOS4 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS4_OFFSET)
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320 #define HAL_DISPLAY_ASCIIPOS5 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS5_OFFSET)
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321 #define HAL_DISPLAY_ASCIIPOS6 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS6_OFFSET)
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322 #define HAL_DISPLAY_ASCIIPOS7 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS7_OFFSET)
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323
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324 #ifdef __ASSEMBLER__
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325
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326 # define DEBUG_ASCII_DISPLAY(register, character) \
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327 li k0, CYGARC_UNCACHED_ADDRESS(register); \
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328 li k1, character; \
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329 sw k1, 0(k0); \
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330 nop; \
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331 nop; \
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332 nop
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333
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334 # define DEBUG_LED_IMM(val) \
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335 li k0, HAL_DISPLAY_LEDBAR; \
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336 li k1, val; \
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337 sw k1, 0(k0)
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338
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339 # define DEBUG_LED_REG(reg) \
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340 li k0, HAL_DISPLAY_LEDBAR; \
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341 sw reg, 0(k0)
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342
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343 # define DEBUG_HEX_DISPLAY_IMM(val) \
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344 li k0, HAL_DISPLAY_ASCIIWORD; \
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345 li k1, val; \
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346 sw k1, 0(k0)
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347
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348 # define DEBUG_HEX_DISPLAY_REG(reg) \
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349 li k0, HAL_DISPLAY_ASCIIWORD; \
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350 sw reg, 0(k0)
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351
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352 # define DEBUG_DELAY() \
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353 li k0, 0x20000; \
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354 0: sub k0, k0, 1; \
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355 bnez k0, 0b; \
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356 nop
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357
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358 #else
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359
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360 # define DEBUG_ASCII_DISPLAY(register, character) \
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361 *(register) = character
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362
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363 # define DEBUG_LED_IMM(val) \
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364 *HAL_DISPLAY_LEDBAR = val
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365
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366 # define DEBUG_HEX_DISPLAY_IMM(val) \
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367 *HAL_DISPLAY_ASCIIWORD = val
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368
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369 # define DEBUG_DELAY() \
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370 { \
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371 volatile int i = 0x20000; \
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372 while (--i) ; \
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373 }
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374
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375 # define DEBUG_DISPLAY(str) \
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376 { \
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377 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, str[0]); \
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378 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, str[1]); \
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379 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, str[2]); \
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380 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, str[3]); \
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381 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, str[4]); \
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382 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, str[5]); \
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383 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, str[6]); \
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384 DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, str[7]); \
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385 }
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386
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387
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388 #define HAL_GALILEO_PUTREG(x,y) \
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389 (*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x))) = (y))
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390 #define HAL_GALILEO_GETREG(x) \
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391 (*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x))))
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392
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393
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394 extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
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395 cyg_uint32 devfn,
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396 cyg_uint32 offset);
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397 extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
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398 cyg_uint32 devfn,
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399 cyg_uint32 offset);
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400 extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
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401 cyg_uint32 devfn,
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402 cyg_uint32 offset);
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403 extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
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404 cyg_uint32 devfn,
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405 cyg_uint32 offset,
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406 cyg_uint32 val);
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407 extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
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408 cyg_uint32 devfn,
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409 cyg_uint32 offset,
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410 cyg_uint16 val);
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411 extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
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412 cyg_uint32 devfn,
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413 cyg_uint32 offset,
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414 cyg_uint8 val);
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415
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416 // Initialize the PCI bus.
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417 externC void cyg_hal_plf_pci_init(void);
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418 #define HAL_PCI_INIT() cyg_hal_plf_pci_init()
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419
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420 // Map PCI device resources starting from these addresses in PCI space.
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421 #define HAL_PCI_ALLOC_BASE_MEMORY 0x08000000
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422 #define HAL_PCI_ALLOC_BASE_IO 0x18000000
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423
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424 // This is where the PCI spaces are mapped in the CPU's address space.
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425 //
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426 #define HAL_PCI_PHYSICAL_MEMORY_BASE 0xA0000000
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427 #define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000
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428
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429 // Read a value from the PCI configuration space of the appropriate
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430 // size at an address composed from the bus, devfn and offset.
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431 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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432 __val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
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433
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434 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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435 __val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
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436
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437 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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438 __val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
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439
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440 // Write a value to the PCI configuration space of the appropriate
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441 // size at an address composed from the bus, devfn and offset.
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442 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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443 cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
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444
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445 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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446 cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
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447
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448 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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449 cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
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450
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451
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452 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
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453 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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454 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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455 CYG_MACRO_START \
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456 __valid = false; \
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457 CYG_MACRO_END
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458
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459
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460 // Galileo GT64120 on MIPS ATLAS requires special processing.
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461 // First, it will hang when accessing device 31 on the local bus.
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462 // Second, we need to ignore the GT64120 so we can set it up
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463 // outside the generic PCI library.
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464 #define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
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465 ((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))
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466
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467 #endif
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468
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469
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470 //-----------------------------------------------------------------------------
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471 // end of plf_io.h
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472 #endif // CYGONCE_PLF_IO_H