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annotate packages/hal/powerpc/arch/current/include/hal_io.h @ 208:e0c0827131d1 ecos
Merge from eCos master repository on 2002-05-20-20:11:54-BST
| author | jlarmour |
|---|---|
| date | Mon, 20 May 2002 22:19:26 +0000 |
| parents | bf00f99aec69 |
| children | d2c90368aeef |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_IO_H |
| 2 #define CYGONCE_HAL_IO_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_io.h | |
| 7 // | |
| 8 // HAL device IO register support. | |
| 9 // | |
| 10 //============================================================================= | |
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11 //####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License along |
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26 // with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use macros |
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30 // or inline functions from this file, or you compile this file and link it |
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31 // with other works to produce a work based on this file, this file does not |
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32 // by itself cause the resulting work to be covered by the GNU General Public |
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33 // License. However the source code for this file must still be made available |
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34 // in accordance with section (3) of the GNU General Public License. |
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35 // |
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36 // This exception does not invalidate any other reasons why a work based on |
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37 // this file might be covered by the GNU General Public License. |
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38 // |
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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40 // at http://sources.redhat.com/ecos/ecos-license |
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41 // ------------------------------------------- |
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42 //####ECOSGPLCOPYRIGHTEND#### |
| 0 | 43 //============================================================================= |
| 44 //#####DESCRIPTIONBEGIN#### | |
| 45 // | |
| 46 // Author(s): nickg | |
| 47 // Contributors: nickg | |
| 48 // Date: 1998-02-17 | |
| 49 // Purpose: Define IO register support | |
| 50 // Description: The macros defined here provide the HAL APIs for handling | |
| 51 // device IO control registers. | |
| 52 // | |
| 53 // Usage: | |
| 54 // #include <cyg/hal/hal_io.h> | |
| 55 // ... | |
| 56 // | |
| 57 // | |
| 58 //####DESCRIPTIONEND#### | |
| 59 // | |
| 60 //============================================================================= | |
| 61 | |
| 62 #include <cyg/infra/cyg_type.h> | |
| 63 | |
| 64 //----------------------------------------------------------------------------- | |
| 65 // Enforce in-order IO for all HAL reads/writes using this macro. | |
| 66 #define HAL_IO_BARRIER() \ | |
| 2 | 67 asm volatile ( "eieio" : : : "memory" ) |
| 0 | 68 |
| 69 //----------------------------------------------------------------------------- | |
| 70 // IO Register address. | |
| 71 // This type is for recording the address of an IO register. | |
| 72 | |
| 73 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; | |
| 74 | |
| 75 //----------------------------------------------------------------------------- | |
| 76 // BYTE Register access. | |
| 77 // Individual and vectorized access to 8 bit registers. | |
| 78 | |
| 2 | 79 #define HAL_READ_UINT8( _register_, _value_ ) \ |
| 80 CYG_MACRO_START \ | |
| 81 ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ | |
| 82 HAL_IO_BARRIER (); \ | |
| 83 CYG_MACRO_END | |
| 0 | 84 |
| 2 | 85 #define HAL_WRITE_UINT8( _register_, _value_ ) \ |
| 86 CYG_MACRO_START \ | |
| 87 (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ | |
| 88 HAL_IO_BARRIER (); \ | |
| 89 CYG_MACRO_END | |
| 0 | 90 |
| 91 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 92 CYG_MACRO_START \ | |
| 93 cyg_count32 _i_,_j_; \ | |
| 94 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 95 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ | |
| 96 HAL_IO_BARRIER (); \ | |
| 97 } \ | |
| 98 CYG_MACRO_END | |
| 99 | |
| 100 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 101 CYG_MACRO_START \ | |
| 102 cyg_count32 _i_,_j_; \ | |
| 103 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 104 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 105 HAL_IO_BARRIER (); \ | |
| 106 } \ | |
| 107 CYG_MACRO_END | |
| 108 | |
| 109 | |
| 110 //----------------------------------------------------------------------------- | |
| 111 // 16 bit access. | |
| 112 // Individual and vectorized access to 16 bit registers. | |
| 113 | |
| 114 #define HAL_READ_UINT16( _register_, _value_ ) \ | |
| 2 | 115 CYG_MACRO_START \ |
| 116 ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ | |
| 117 HAL_IO_BARRIER (); \ | |
| 118 CYG_MACRO_END | |
| 0 | 119 |
| 120 #define HAL_WRITE_UINT16( _register_, _value_ ) \ | |
| 2 | 121 CYG_MACRO_START \ |
| 122 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ | |
| 123 HAL_IO_BARRIER (); \ | |
| 124 CYG_MACRO_END | |
| 0 | 125 |
| 126 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 127 CYG_MACRO_START \ | |
| 128 cyg_count32 _i_,_j_; \ | |
| 129 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 130 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ | |
| 131 HAL_IO_BARRIER (); \ | |
| 132 } \ | |
| 133 CYG_MACRO_END | |
| 134 | |
| 135 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 136 CYG_MACRO_START \ | |
| 137 cyg_count32 _i_,_j_; \ | |
| 138 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 139 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 140 HAL_IO_BARRIER (); \ | |
| 141 } \ | |
| 142 CYG_MACRO_END | |
| 143 | |
| 144 //----------------------------------------------------------------------------- | |
| 145 // 32 bit access. | |
| 146 // Individual and vectorized access to 32 bit registers. | |
| 147 | |
| 148 #define HAL_READ_UINT32( _register_, _value_ ) \ | |
| 2 | 149 CYG_MACRO_START \ |
| 150 ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ | |
| 151 HAL_IO_BARRIER (); \ | |
| 152 CYG_MACRO_END | |
| 0 | 153 |
| 154 #define HAL_WRITE_UINT32( _register_, _value_ ) \ | |
| 2 | 155 CYG_MACRO_START \ |
| 156 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ | |
| 157 HAL_IO_BARRIER (); \ | |
| 158 CYG_MACRO_END | |
| 0 | 159 |
| 160 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 161 CYG_MACRO_START \ | |
| 162 cyg_count32 _i_,_j_; \ | |
| 163 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 164 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ | |
| 165 HAL_IO_BARRIER (); \ | |
| 166 } \ | |
| 167 CYG_MACRO_END | |
| 168 | |
| 169 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 170 CYG_MACRO_START \ | |
| 171 cyg_count32 _i_,_j_; \ | |
| 172 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 173 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 174 HAL_IO_BARRIER (); \ | |
| 175 } \ | |
| 176 CYG_MACRO_END | |
| 177 | |
| 178 //----------------------------------------------------------------------------- | |
| 179 #endif // ifndef CYGONCE_HAL_IO_H | |
| 180 // End of hal_io.h |
