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annotate packages/hal/powerpc/cme555/current/src/cme555.S @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 ##=============================================================================
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2 ##
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3 ## cme555.S
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4 ##
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5 ## CME555 board hardware setup
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6 ##
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7 ##=============================================================================
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8 #####ECOSGPLCOPYRIGHTBEGIN####
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9 # -------------------------------------------
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10 # This file is part of eCos, the Embedded Configurable Operating System.
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11 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 #
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13 # eCos is free software; you can redistribute it and/or modify it under
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14 # the terms of the GNU General Public License as published by the Free
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15 # Software Foundation; either version 2 or (at your option) any later version.
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16 #
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17 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 # for more details.
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21 #
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22 # You should have received a copy of the GNU General Public License along
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23 # with eCos; if not, write to the Free Software Foundation, Inc.,
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24 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 #
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26 # As a special exception, if other files instantiate templates or use macros
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27 # or inline functions from this file, or you compile this file and link it
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28 # with other works to produce a work based on this file, this file does not
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29 # by itself cause the resulting work to be covered by the GNU General Public
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30 # License. However the source code for this file must still be made available
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31 # in accordance with section (3) of the GNU General Public License.
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32 #
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33 # This exception does not invalidate any other reasons why a work based on
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34 # this file might be covered by the GNU General Public License.
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35 #
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36 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 # at http://sources.redhat.com/ecos/ecos-license
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38 # -------------------------------------------
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39 #####ECOSGPLCOPYRIGHTEND####
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40 ##=============================================================================
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41 #######DESCRIPTIONBEGIN####
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42 ##
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43 ## Author(s): Bob Koninckx
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44 ## Contributors:Bob Koninckx
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45 ## Date: 2001-12-15
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46 ## Purpose: cme555 board hardware setup
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47 ## Description: This file contains any code needed to initialize the
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48 ## hardware on a cme555 mpc555 board.
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49 ##
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50 ######DESCRIPTIONEND####
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51 ##
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52 ##=============================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/hal/ppc_regs.h>
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57 #include <cyg/hal/arch.inc>
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58
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59 #------------------------------------------------------------------------------
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60
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61 .globl hal_hardware_init
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62 hal_hardware_init:
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63
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64 #if defined(CYGPKG_HAL_POWERPC_CME555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
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65 lwi r3, CYGARC_REG_IMM_BASE # Base address of control registers
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66
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67 // Configure external interrupt pins as General purpose I/O. They do not
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68 // have pull-up resistors on the CME555. Add to that that IRQ0 triggers
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69 // a non-maskable reset of the board ... This one gave me nightmares ...
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70 lwi r4, 0x00000800
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71 stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
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72 lwi r4, 0xff88
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73 stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
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74
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75 // Memory map
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76 // CS0 configuration
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77 // Base address 0x400000, no burst support, 32 bit wide data port
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78 // Valid addresses till 0x43FFFF, no wait states
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79 lwi r4, 0x00400003
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80 stw r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3)
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81 lwi r4, 0xfff80002
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82 stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
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83
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84 // CS1 configuration
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85 // Base address 0x800000, no burst support, 32 bit wide data port
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86 // Valid adresses till 0x87FFFF, three wait states for access time 70ns
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87 lwi r4, 0x00800003
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88 stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
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89 lwi r4, 0xfff80032
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90 stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
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91
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92 // CS2 configuration
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93 // Base address 0xc00000, no burst support, 32 bit wide data port
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94 // Valid adresses till 0xc7FFFF, maximum wait states
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95 lwi r4, 0x00c00003
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96 stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
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97 lwi r4, 0xfff800f2
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98 stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
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99
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100 // CS3 configuration
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101 // works for keypad/LCD
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102 // maximum wait states
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103 lwi r4, 0x01000403
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104 stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
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105 lwi r4, 0xfffe0ff1
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106 stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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107
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108 // And some other configuration registers
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109 #if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
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110 lwi r4, 1
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111 #else
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112 lwi r4, 0
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113 #endif
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114 stw r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3)
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115 lwi r4, 0
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116 stw r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3)
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117
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118 // Limb mode enable, TMBCLK = BUS/16, RTCCLK = Crystal / 16
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119 // generate 40 MHz bus clock
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120 lwi r4, 0x3010000
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121 stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
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122 lwi r4, 0x900000
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123 stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
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124
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125 // Enable the time base and set the freeze flag
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126 lwi r4, 0x03
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127 sth r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3)
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128
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129 // Unlock the RTC register set
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130 lwi r4, 0x55ccaa33
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131 stw r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3)
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132 // RTC is clocked by 4MHz crystal, set the freeze flag
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133 lwi r4, 0x12
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134 sth r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3)
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135 // Set the freeze flag for the Periodic interrupt timer
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136 lwi r4, 0x02
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137 sth r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3)
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138
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139 lwi r4, 0x00
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140 lwi r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE)
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141 sthx r4, r3, r5
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142
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143 lwi r4, 0xffa0
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144 lwi r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE)
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145 sthx r4, r3, r5
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146
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147 lwi r4, 0x00
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148 lwi r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE)
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149 sthx r4, r3, r5
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150
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151 lwi r4, 0x00
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152 lwi r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE)
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153 sthx r4, r3, r5
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154 lwi r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE)
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155 sthx r4, r3, r5
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156 lwi r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE)
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157 sthx r4, r3, r5
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158 lwi r5, (CYGARC_REG_IMM_MIOS1TPCR-CYGARC_REG_IMM_BASE)
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159 sthx r4, r3, r5
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160 lwi r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE)
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161 sthx r4, r3, r5
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162
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163 lwi r4, 0x00000000
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164 lwi r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE)
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165 stwx r4, r3, r5
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166 lwi r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE)
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167 stwx r4, r3, r5
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168 lwi r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE)
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169 stwx r4, r3, r5
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170 lwi r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE)
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171 stwx r4, r3, r5
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172
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173 // Enable 32 interrupt priorities on the IMB3 unit
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174 lwi r4, 0x60000000
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175 lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
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176 stwx r4, r3, r5
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177 #endif
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178
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179 sync
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180 blr
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181
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182 #------------------------------------------------------------------------------
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183 # end of cme555.S