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annotate packages/hal/sh/se7751/current/cdl/hal_sh_sh7751_se7751.cdl @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents
children d2c90368aeef
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1 # ====================================================================
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2 #
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3 # hal_sh_sh7751_se7751.cdl
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4 #
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5 # Hitachi SE7751 board HAL package configuration data
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6 #
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7 # ====================================================================
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8 #####ECOSGPLCOPYRIGHTBEGIN####
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9 # -------------------------------------------
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10 # This file is part of eCos, the Embedded Configurable Operating System.
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11 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 #
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13 # eCos is free software; you can redistribute it and/or modify it under
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14 # the terms of the GNU General Public License as published by the Free
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15 # Software Foundation; either version 2 or (at your option) any later version.
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16 #
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17 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 # for more details.
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21 #
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22 # You should have received a copy of the GNU General Public License along
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23 # with eCos; if not, write to the Free Software Foundation, Inc.,
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24 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 #
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26 # As a special exception, if other files instantiate templates or use macros
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27 # or inline functions from this file, or you compile this file and link it
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28 # with other works to produce a work based on this file, this file does not
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29 # by itself cause the resulting work to be covered by the GNU General Public
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30 # License. However the source code for this file must still be made available
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31 # in accordance with section (3) of the GNU General Public License.
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32 #
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33 # This exception does not invalidate any other reasons why a work based on
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34 # this file might be covered by the GNU General Public License.
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35 #
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36 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 # at http://sources.redhat.com/ecos/ecos-license
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38 # -------------------------------------------
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39 #####ECOSGPLCOPYRIGHTEND####
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40 # ====================================================================
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41 ######DESCRIPTIONBEGIN####
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42 #
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43 # Author(s): jskov
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44 # Original data: jskov
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45 # Contributors:
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46 # Date: 2001-07-09
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47 #
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48 #####DESCRIPTIONEND####
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49 #
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50 # ====================================================================
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51
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52 cdl_package CYGPKG_HAL_SH_SH7751_SE7751 {
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53 display "Hitachi/SH7751 SE7751 board"
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54 parent CYGPKG_HAL_SH
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55 requires CYGPKG_HAL_SH_7751
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56 requires ! CYGHWR_HAL_SH_BIGENDIAN
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57 requires CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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58 define_header hal_sh_sh7751_se7751.h
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59 include_dir cyg/hal
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60 description "
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61 The SE7751 HAL package provides the support needed to run
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62 eCos on a Hitachi/SH SE7751 board."
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63
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64 compile hal_diag.c plf_misc.c ser16c550c.c m1543c.c
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65
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66 implements CYGINT_HAL_DEBUG_GDB_STUBS
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67 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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68 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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69 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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70
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71 define_proc {
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72 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
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73 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7751_se7751.h>"
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74
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75 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
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76 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c000000"
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77 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c000100"
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78
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79 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH 7751\""
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80 puts $::cdl_header "#define HAL_PLATFORM_BOARD \"SE7751\""
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81 puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
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82 }
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83
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84 cdl_component CYG_HAL_STARTUP {
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85 display "Startup type"
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86 flavor data
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87 legal_values {"RAM" "ROM" "ROMRAM" }
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88 default_value {"RAM"}
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89 no_define
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90 define -file system.h CYG_HAL_STARTUP
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91 description "
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92 When targetting the SE7751 board it is possible to build
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93 the system for either RAM bootstrap or ROM bootstrap.
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94 RAM bootstrap generally requires that the board
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95 is equipped with ROMs containing a suitable ROM monitor or
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96 equivalent software that allows GDB to download the eCos
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97 application on to the board. The ROM bootstrap typically
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98 requires that the eCos application be blown into EPROMs or
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99 equivalent technology. ROMRAM bootstrap is similar to ROM
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100 bootstrap, but everything is copied to RAM before execution
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101 starts thus improving performance, but at the cost of an
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102 increased RAM footprint."
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103 }
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104
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105 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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106 display "Number of communication channels on the board"
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107 flavor data
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108 calculated 2
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109 }
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110
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111 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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112 display "Debug serial port"
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113 flavor data
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114 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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115 default_value 0
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116 description "
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117 The SE7751 board has one serial port. This option
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118 chooses which port will be used to connect to a host
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119 running GDB."
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120 }
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121
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122 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
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123 display "Default console channel."
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124 flavor data
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125 calculated 0
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126 }
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127
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128 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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129 display "Diagnostic serial port"
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130 flavor data
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131 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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132 default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
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133 description "
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134 The SE7751 board has two serial ports. This option
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135 chooses which port will be used for diagnostic output."
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136 }
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137
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138 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
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139 display "Console/GDB serial port baud rate"
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140 flavor data
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141 legal_values 9600 19200 38400 57600 115200
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142 default_value 38400
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143 define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
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144 description "
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145 This option controls the default baud rate used for the
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146 Console/GDB connection."
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147 }
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148
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149 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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150 display "SH on-chip platform clock controls"
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151 description "
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152 The various clocks used by the system are derived from
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153 these options."
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154 flavor none
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155 no_define
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156
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157 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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158 display "SH clock crystal"
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159 flavor data
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160 legal_values 8000000 to 50000000
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161 default_value 27000000
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162 no_define
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163 description "
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164 This option specifies the frequency of the crystal all
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165 other clocks are derived from."
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166 }
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167
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168 cdl_option CYGHWR_HAL_SH_OOC_CKIO {
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169 display "SH clock CKIO output enable"
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170 default_value 1
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171 description "
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172 This selects whether CKIO output is enabled."
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173 }
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174
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175 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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176 display "SH clock PLL circuit 1"
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177 flavor data
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178 default_value 6
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179 legal_values { 0 6 }
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180 description "
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181 This selects the multiplication factor provided by
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182 PLL1."
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183 }
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184
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185 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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186 display "SH clock PLL circuit 2"
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187 flavor data
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188 default_value 1
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189 legal_values { 0 1 }
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190 description "
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191 This selects the multiplication factor provided by
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192 PLL2. If PLL2 is disabled this option should
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193 be set to zero."
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194 }
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195
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196 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
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197 display "SH clock divider 1"
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198 flavor data
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199 default_value 1
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200 legal_values { 1 2 }
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201 description "
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202 This divider option affects all clocks."
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203 }
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204
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205 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
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206 display "SH CPU clock divider"
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207 flavor data
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208 default_value 1
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209 legal_values { 1 2 3 4 6 8 }
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210 description "
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211 This divider option affects the CPU clock."
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212 }
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213
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214 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
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215 display "SH bus clock divider"
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216 flavor data
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217 default_value 3
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218 legal_values { 1 2 3 4 6 8 }
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219 description "
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220 This divider option affects the bus clock."
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221 }
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222
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223 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
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224 display "SH peripheral clock divider"
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225 flavor data
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226 default_value 6
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227 legal_values { 1 2 3 4 6 8 }
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228 description "
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229 This divider option affects the peripheral clock."
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230 }
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231
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232 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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233 display "SH clock mode"
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234 flavor data
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235 default_value 3
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236 legal_values { 0 1 2 3 4 5 }
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237 description "
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238 This option must mirror the clock mode hardwired on
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239 the MD0-MD2 pins of the CPU in order to correctly
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240 initialize the FRQCR register."
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241 }
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242 }
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243
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244 cdl_component CYGBLD_GLOBAL_OPTIONS {
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245 display "Global build options"
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246 flavor none
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247 parent CYGPKG_NONE
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248 no_define
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249 description "
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250 Global build options including control over
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251 compiler flags, linker flags and choice of toolchain."
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252
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253
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254 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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255 display "Global command prefix"
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256 flavor data
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257 no_define
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258 default_value { "sh-elf" }
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259 description "
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260 This option specifies the command prefix used when
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261 invoking the build tools."
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262 }
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263
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264 cdl_option CYGBLD_GLOBAL_CFLAGS {
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265 display "Global compiler flags"
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266 flavor data
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267 no_define
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268 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
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269 description "
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270 This option controls the global compiler flags which
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271 are used to compile all packages by
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272 default. Individual packages may define
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273 options which override these global flags."
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274 }
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275
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276 cdl_option CYGBLD_GLOBAL_LDFLAGS {
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277 display "Global linker flags"
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278 flavor data
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279 no_define
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280 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
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281 description "
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282 This option controls the global linker flags. Individual
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283 packages may define options which override these global flags."
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284 }
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285
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286 cdl_option CYGBLD_BUILD_GDB_STUBS {
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287 display "Build GDB stub ROM image"
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288 default_value 0
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289 requires { CYG_HAL_STARTUP == "ROM" }
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290 requires CYGSEM_HAL_ROM_MONITOR
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291 requires CYGBLD_BUILD_COMMON_GDB_STUBS
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292 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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293 requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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294 requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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295 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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296 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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297 no_define
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298 description "
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299 This option enables the building of the GDB stubs for the
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300 board. The common HAL controls takes care of most of the
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301 build process, but the final conversion from ELF image to
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302 binary data is handled by the platform CDL, allowing
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303 relocation of the data if necessary."
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304
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305 make -priority 320 {
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306 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
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307 $(OBJCOPY) -O binary $< $@
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308 }
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309 }
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310 }
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311
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312 cdl_component CYGHWR_MEMORY_LAYOUT {
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313 display "Memory layout"
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314 flavor data
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315 no_define
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316 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7751_se7751_ram" : \
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317 CYG_HAL_STARTUP == "ROM" ? "sh_sh7751_se7751_rom" : \
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318 "sh_sh7751_se7751_romram" }
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319
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320 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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321 display "Memory layout linker script fragment"
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322 flavor data
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323 no_define
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324 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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325 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7751_se7751_ram.ldi>" : \
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326 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh7751_se7751_rom.ldi>" : \
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327 "<pkgconf/mlt_sh_sh7751_se7751_romram.ldi>" }
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328 }
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329
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330 cdl_option CYGHWR_MEMORY_LAYOUT_H {
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331 display "Memory layout header file"
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332 flavor data
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333 no_define
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334 define -file system.h CYGHWR_MEMORY_LAYOUT_H
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335 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7751_se7751_ram.h>" : \
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336 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh7751_se7751_rom.h>" : \
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337 "<pkgconf/mlt_sh_sh7751_se7751_romram.h>" }
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338 }
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339 }
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340
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341 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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342 display "Work with a ROM monitor"
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343 flavor booldata
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344 legal_values { "GDB_stubs" }
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345 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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346 requires { CYG_HAL_STARTUP == "RAM" }
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347 parent CYGPKG_HAL_ROM_MONITOR
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348 description "
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349 Support can be enabled for boot ROMs or ROM monitors which contain
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350 GDB stubs. This support changes various eCos semantics such as
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351 the encoding of diagnostic output, and the overriding of hardware
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352 interrupt vectors."
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353 }
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354
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355 cdl_option CYGSEM_HAL_ROM_MONITOR {
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356 display "Behave as a ROM monitor"
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357 flavor bool
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358 default_value 0
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359 parent CYGPKG_HAL_ROM_MONITOR
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360 requires { CYG_HAL_STARTUP == "ROM" }
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361 description "
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362 Enable this option if this program is to be used as a ROM monitor,
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363 i.e. applications will be loaded into RAM on the board, and this
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364 ROM monitor may process exceptions or interrupts generated from the
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365 application. This enables features such as utilizing a separate
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366 interrupt stack when exceptions are generated."
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367 }
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368
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369 cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
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370 display "Redboot HAL options"
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371 flavor none
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372 no_define
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373 parent CYGPKG_REDBOOT
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374 active_if CYGPKG_REDBOOT
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375 description "
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376 This option lists the target's requirements for a valid Redboot
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377 configuration."
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378
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379 cdl_option CYGBLD_BUILD_REDBOOT_BIN {
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380 display "Build Redboot ROM binary image"
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381 active_if CYGBLD_BUILD_REDBOOT
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382 default_value 1
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383 no_define
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384 description "This option enables the conversion of the Redboot ELF
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385 image to a binary image suitable for ROM programming."
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386
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387 make -priority 325 {
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388 <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
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389 $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
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390 $(OBJCOPY) -O srec $< $(@:.bin=.srec)
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391 $(OBJCOPY) --change-address 0x21000000 -O srec $< $(@:.bin=.eprom.srec)
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392 $(OBJCOPY) -O binary $< $@
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393 }
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394 }
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395 }
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396 }