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annotate packages/hal/sh/sh3/current/include/sd0001.h @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
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children d2c90368aeef
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1 #ifndef CYGONCE_HAL_SD0001_H
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2 #define CYGONCE_HAL_SD0001_H
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3
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4 //=============================================================================
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5 //
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6 // sd0001.h
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7 //
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8 // SD0001 support chip - used with SH/7729
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): jskov
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47 // Contributors:jskov
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48 // Date: 2001-05-25
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49 // Purpose: Support chip
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50 // Usage: Included from <cyg/hal/sh_regs.h>
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51 //
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52 //
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53 //####DESCRIPTIONEND####
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54 //
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55 //=============================================================================
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56 #ifndef _SD0001_BASE
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57 # define _SD0001_BASE 0xb0000000
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58 #endif
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59
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60 //-----------------------------------------------------------------------------
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61 // System configuration
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62 #define CYGARC_REG_SD0001_RESET (_SD0001_BASE + 0x08)
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63 #define CYGARC_REG_SD0001_SDRAM (_SD0001_BASE + 0x10)
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64 #define CYGARC_REG_SD0001_INT_STS1 (_SD0001_BASE + 0x20)
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65 #define CYGARC_REG_SD0001_INT_ENABLE (_SD0001_BASE + 0x24)
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66 #define CYGARC_REG_SD0001_INT_STS2 (_SD0001_BASE + 0x28)
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67 #define CYGARC_REG_SD0001_PCI_CTL (_SD0001_BASE + 0x50)
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68
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69 #define CYGARC_REG_PCI_IO_MEMOFFSET (_SD0001_BASE + 0x58)
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70 #define CYGARC_REG_PCI_MEM_MEMOFFSET (_SD0001_BASE + 0x5c)
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71
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72
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73 #define CYGARC_REG_PCI_CFG_ADDR (_SD0001_BASE + 0x60)
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74 #define CYGARC_REG_PCI_CFG_DATA (_SD0001_BASE + 0x64)
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75 #define CYGARC_REG_PCI_CFG_CMD (_SD0001_BASE + 0x68)
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76 #define CYGARC_REG_PCI_CFG_FLG (_SD0001_BASE + 0x6c)
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77
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78 #define CYGARC_REG_PCI_CFG_ADDR_ENABLE 0x80000000
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79 #define CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift 16
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80 #define CYGARC_REG_PCI_CFG_ADDR_FUNC_shift 8
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81
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82 #define CYGARC_REG_PCI_CFG_CMD_BE3 0x00080000
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83 #define CYGARC_REG_PCI_CFG_CMD_BE2 0x00040000
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84 #define CYGARC_REG_PCI_CFG_CMD_BE1 0x00020000
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85 #define CYGARC_REG_PCI_CFG_CMD_BE0 0x00010000
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86
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87 #define CYGARC_REG_PCI_CFG_CMD_CMDEN 0x00008000
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88
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89 #define CYGARC_REG_PCI_CFG_CMD_IO_WRITE 0x00000300
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90 #define CYGARC_REG_PCI_CFG_CMD_IO_READ 0x00000200
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91
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92 #define CYGARC_REG_PCI_CFG_CMD_WT 0x00000008
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93 #define CYGARC_REG_PCI_CFG_CMD_RD 0x00000004
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94 #define CYGARC_REG_PCI_CFG_CMD_CFWT 0x00000002
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95 #define CYGARC_REG_PCI_CFG_CMD_CFRD 0x00000001
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96
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97
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98 #define CYGARC_REG_PCI_CFG_CMD_WCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFWT)
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99 #define CYGARC_REG_PCI_CFG_CMD_RCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFRD)
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100
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101
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102
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103 #define CYGARC_REG_SD0001_PCI_CTL_ENDIAN2 0x40000000
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104 #define CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT 0x0000ff00
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105 #define CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT 0x000000f0
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106
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107
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108 #define CYGARC_REG_PCI_CFG_FLG_ACTIVE 0x00000001
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109
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110
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111 #define CYGARC_REG_SD0001_RESET_SWRST 0x80000000
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112 #define CYGARC_REG_SD0001_RESET_PCIRST 0x40000000
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113
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114
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115 #define CYGARC_REG_SD0001_SDRAM_SDKIND_128M 0x80000000
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116 #define CYGARC_REG_SD0001_SDRAM_SDSIZE_8 0x10000000
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117 #define CYGARC_REG_SD0001_SDRAM_REF_MUMBLE 0x00008000
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118 #define CYGARC_REG_SD0001_SDRAM_LMODE_CAS2 0x00000010
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119
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120 #define CYGARC_REG_SD0001_SDRAM_INIT (CYGARC_REG_SD0001_SDRAM_SDKIND_128M\
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121 |CYGARC_REG_SD0001_SDRAM_SDSIZE_8\
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122 |CYGARC_REG_SD0001_SDRAM_REF_MUMBLE\
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123 |CYGARC_REG_SD0001_SDRAM_LMODE_CAS2)
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124
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125
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126 #define CYGARC_REG_SD0001_INT_EN 0x80000000
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127 #define CYGARC_REG_SD0001_INT_INTD 0x00000008
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128 #define CYGARC_REG_SD0001_INT_INTC 0x00000004
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129 #define CYGARC_REG_SD0001_INT_INTB 0x00000002
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130 #define CYGARC_REG_SD0001_INT_INTA 0x00000001
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131
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132
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133 #endif // CYGONCE_HAL_SD0001_H