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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents f62680ef1804
children d2c90368aeef
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1 #ifndef CYGONCE_KERNEL_SMP_HXX
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2 #define CYGONCE_KERNEL_SMP_HXX
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3
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4 //==========================================================================
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5 //
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6 // smp.hxx
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7 //
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8 // SMP kernel support
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9 //
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10 //==========================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //==========================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors:nickg
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48 // Date: 2001-02-10
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49 // Purpose: Kernel SMP support
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50 // Description: If SMP support is configured into the kernel, then this file
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51 // translates HAL defined macros into C and C++ classes and methods
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52 // that can be called from the rest of the kernel. If SMP is not
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53 // configured in, then the same classes and methods are defined here
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54 // to operate correctly in a single CPU configuration.
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55 //
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56 // Usage: #include <cyg/kernel/smp.hxx>
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57 //
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58 //####DESCRIPTIONEND####
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59 //
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60 //==========================================================================
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61
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62 #include <cyg/kernel/ktypes.h>
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63 #include <cyg/infra/cyg_ass.h> // assertion macros
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64
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65 #include <cyg/hal/hal_intr.h> // HAL_DISABLE_INTERRUPTS() etc.
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66
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67 #include <cyg/kernel/instrmnt.h>
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68
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69 //==========================================================================
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70
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71 #if defined(CYGPKG_KERNEL_SMP_SUPPORT) && (CYGPKG_HAL_SMP_SUPPORT)
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72
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73 //==========================================================================
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74 // SMP support is included
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75
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76 #define CYG_KERNEL_SMP_ENABLED
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77
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78 // -------------------------------------------------------------------------
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79 // Get HAL support
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80
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81 #include <cyg/hal/hal_smp.h>
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82
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83 // -------------------------------------------------------------------------
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84 // Defined values
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85 // These all just map straight through to the HAL.
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86
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87 #define CYGNUM_KERNEL_CPU_MAX HAL_SMP_CPU_MAX
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88
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89 #define CYG_KERNEL_CPU_COUNT() HAL_SMP_CPU_COUNT()
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90
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91 #define CYG_KERNEL_CPU_THIS() HAL_SMP_CPU_THIS()
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92
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93 #define CYG_KERNEL_CPU_NONE HAL_SMP_CPU_NONE
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94
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95 // -------------------------------------------------------------------------
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96 // CPU control
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97
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98 #define CYG_KERNEL_CPU_START( __cpu ) HAL_SMP_CPU_START( __cpu )
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99
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100 #define CYG_KERNEL_CPU_RESCHEDULE_INTERRUPT( __cpu, __wait ) \
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101 HAL_SMP_CPU_RESCHEDULE_INTERRUPT( __cpu, __wait )
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102
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103 #define CYG_KERNEL_CPU_TIMESLICE_INTERRUPT( __cpu, __wait ) \
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104 HAL_SMP_CPU_TIMESLICE_INTERRUPT( __cpu, __wait )
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105
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106 // -------------------------------------------------------------------------
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107 // Scheduler lock default implementation.
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108
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109 // This implementation should serve for most targets. However, some
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110 // targets may have hardware or other features that make simple
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111 // spinlocks impossible, or allow us to implement the scheduler lock
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112 // in a more efficient manner. If that is the case then the HAL will
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113 // implement these macros itself.
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114
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115 #ifndef HAL_SMP_SCHEDLOCK_DATA_TYPE
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116
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117 #define HAL_SMP_SCHEDLOCK_DATA_TYPE struct hal_smp_schedlock_data_type
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118
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119 struct hal_smp_schedlock_data_type {
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120 HAL_SPINLOCK_TYPE spinlock;
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121 volatile HAL_SMP_CPU_TYPE holder;
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122 };
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123
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124 #define HAL_SMP_SCHEDLOCK_INIT( __lock, __data ) \
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125 CYG_MACRO_START \
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126 { \
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127 __lock = 1; \
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128 HAL_SPINLOCK_CLEAR(__data.spinlock); \
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129 HAL_SPINLOCK_SPIN(__data.spinlock); \
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130 __data.holder = HAL_SMP_CPU_THIS(); \
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131 } \
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132 CYG_MACRO_END
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133
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134
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135 #define HAL_SMP_SCHEDLOCK_INC( __lock, __data ) \
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136 CYG_MACRO_START \
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137 { \
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138 CYG_INTERRUPT_STATE __state; \
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139 HAL_DISABLE_INTERRUPTS(__state); \
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140 if( __data.holder == HAL_SMP_CPU_THIS() ) \
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141 __lock++; \
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142 else \
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143 { \
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144 CYG_INSTRUMENT_SMP(LOCK_WAIT,CYG_KERNEL_CPU_THIS(),0); \
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145 HAL_SPINLOCK_SPIN(__data.spinlock); \
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146 __data.holder = HAL_SMP_CPU_THIS(); \
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147 __lock++; \
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148 CYG_INSTRUMENT_SMP(LOCK_GOT,CYG_KERNEL_CPU_THIS(),0); \
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149 } \
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150 HAL_RESTORE_INTERRUPTS(__state); \
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151 } \
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152 CYG_MACRO_END
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153
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154 #define HAL_SMP_SCHEDLOCK_ZERO( __lock, __data ) \
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155 CYG_MACRO_START \
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156 { \
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157 CYG_INTERRUPT_STATE __state; \
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158 HAL_DISABLE_INTERRUPTS(__state); \
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159 CYG_ASSERT( __data.holder == HAL_SMP_CPU_THIS(), "Zeroing schedlock not owned by me!"); \
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160 __lock = 0; \
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161 __data.holder = HAL_SMP_CPU_NONE; \
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162 HAL_SPINLOCK_CLEAR(__data.spinlock); \
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163 HAL_RESTORE_INTERRUPTS(__state); \
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164 } \
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165 CYG_MACRO_END
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166
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167 #define HAL_SMP_SCHEDLOCK_SET( __lock, __data, __new ) \
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168 CYG_MACRO_START \
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169 { \
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170 CYG_ASSERT( __data.holder == HAL_SMP_CPU_THIS(), "Setting schedlock not owned by me!"); \
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171 __lock = __new; \
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172 } \
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173 CYG_MACRO_END
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174
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175 #endif
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176
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177 // -------------------------------------------------------------------------
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178 // SpinLock class
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179 // This class supplies a C++ wrapper for the HAL spinlock API.
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180
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181 #ifdef __cplusplus
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182
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183 #ifdef HAL_SPINLOCK_SPIN
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184
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185 class Cyg_SpinLock
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186 {
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187 HAL_SPINLOCK_TYPE lock;
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188
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189 public:
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190
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191 // Constructor, initialize the lock to clear
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192 Cyg_SpinLock() { lock = HAL_SPINLOCK_INIT_CLEAR; };
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193
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194 ~Cyg_SpinLock()
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195 {
178
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196 // CYG_ASSERT( !test(), "spinlock still claimed");
177
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197 };
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198
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199 // Spin on the lock.
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200 void spin()
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201 {
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202 HAL_SPINLOCK_SPIN(lock);
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203 };
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204
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205 // Clear the lock.
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206 void clear()
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207 {
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208 HAL_SPINLOCK_CLEAR(lock);
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209 };
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210
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211 // Try to claim the lock. Return true if successful, false if not.
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212 cyg_bool trylock()
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213 {
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214 cyg_bool testval;
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215 HAL_SPINLOCK_TRY(lock,testval);
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216 return testval;
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217 };
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218
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219 // Test the current value of the lock
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220 cyg_bool test()
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221 {
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222 cyg_bool testval;
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223 HAL_SPINLOCK_TEST(lock, testval);
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224 return testval;
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225 };
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226
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227
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228 // The following two member functions are only necessary if the
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229 // spinlock is to be used in an ISR.
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230
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231 // Claim the spinlock, but also mask this CPU's interrupts while
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232 // we have it.
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233 void spin_intsave(CYG_INTERRUPT_STATE *state)
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234 {
178
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235 CYG_INTERRUPT_STATE s;
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236 HAL_DISABLE_INTERRUPTS(s);
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237 *state = s;
177
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238 spin();
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239 };
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240
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241 // Clear the lock, and restore the interrupt state saved in
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242 // spin_intsave().
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243 void clear_intsave(CYG_INTERRUPT_STATE state)
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244 {
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245 clear();
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246 HAL_RESTORE_INTERRUPTS(state);
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247 };
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248 };
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249
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250 #endif
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251
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252 // -------------------------------------------------------------------------
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253 // Scheduler lock class
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254 // This uses the scheduler lock API defined by the HAL, or the defaults
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255 // defined above.
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256
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257 class Cyg_Scheduler_SchedLock
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258 {
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259 static volatile cyg_ucount32 sched_lock // lock counter
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260 CYGBLD_ATTRIB_ASM_ALIAS( cyg_scheduler_sched_lock )
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261 CYGBLD_ANNOTATE_VARIABLE_SCHED
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262 ;
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263
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264 static HAL_SMP_SCHEDLOCK_DATA_TYPE lock_data
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265 CYGBLD_ANNOTATE_VARIABLE_SCHED;
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266
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267 protected:
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268
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269 Cyg_Scheduler_SchedLock()
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270 {
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271 HAL_SMP_SCHEDLOCK_INIT( sched_lock, lock_data );
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272 };
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273
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274 // Increment the scheduler lock. If this takes the lock from zero
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275 // to one then this code must also do whatever is necessary to
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276 // serialize CPUs through the scheduler.
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277 static void inc_sched_lock()
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278 {
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279 CYG_INSTRUMENT_SMP(LOCK_INC,CYG_KERNEL_CPU_THIS(),0);
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280 HAL_SMP_SCHEDLOCK_INC( sched_lock, lock_data );
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281 };
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282
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283 // Zero the scheduler lock. This will release the CPU serializing
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284 // lock and allow another CPU in.
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285 static void zero_sched_lock()
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286 {
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287 CYG_INSTRUMENT_SMP(LOCK_ZERO,CYG_KERNEL_CPU_THIS(),0);
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288 CYG_ASSERT( sched_lock != 0, "Scheduler lock already zero");
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289 HAL_SMP_SCHEDLOCK_ZERO( sched_lock, lock_data );
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290 };
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291
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292 // Set the scheduler lock to a non-zero value. Both the scheduler
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293 // lock and the new value must be non-zero.
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294 static void set_sched_lock(cyg_uint32 new_lock)
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295 {
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296 CYG_INSTRUMENT_SMP(LOCK_SET,CYG_KERNEL_CPU_THIS(),new_lock);
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297 CYG_ASSERT( new_lock > 0, "New scheduler lock value == 0");
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298 CYG_ASSERT( sched_lock > 0, "Scheduler lock == 0");
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299 HAL_SMP_SCHEDLOCK_SET( sched_lock, lock_data, new_lock );
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300 };
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301
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302 static cyg_ucount32 get_sched_lock()
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303 {
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304 return sched_lock;
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305 };
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306 };
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307
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308 #define CYGIMP_KERNEL_SCHED_LOCK_DEFINITIONS \
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309 volatile cyg_ucount32 Cyg_Scheduler_SchedLock::sched_lock = 1; \
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310 HAL_SMP_SCHEDLOCK_DATA_TYPE Cyg_Scheduler_SchedLock::lock_data;
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311
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312 #endif // __cplusplus
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313
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314 // -------------------------------------------------------------------------
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315
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316 #else // defined(CYGSEM_KERNEL_SMP_SUPPORT) && (CYGSEM_HAL_SMP_SUPPORT)
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317
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318 //==========================================================================
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319 // SMP support is NOT included.
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320
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321 #undef CYG_KERNEL_SMP_ENABLED
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322
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323 // -------------------------------------------------------------------------
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324 // Defined values
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325 // Supply a set of values that describe a single CPU system.
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326
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327 #ifndef HAL_SMP_CPU_TYPE
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328 #define HAL_SMP_CPU_TYPE cyg_uint32
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329 #endif
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330
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331 #define CYGNUM_KERNEL_CPU_MAX 1
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332
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333 #define CYG_KERNEL_CPU_COUNT() 1
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334
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335 #define CYG_KERNEL_CPU_THIS() 0
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336
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337 #define CYG_KERNEL_CPU_NONE -1
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338
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339 #define CYG_KERNEL_CPU_LOWPRI() CYG_KERNEL_CPU_THIS()
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340
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341 // -------------------------------------------------------------------------
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342 // SpinLock class
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343 // This single CPU version simply goes through the motions of setting
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344 // and clearing the lock variable for debugging purposes.
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345
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346 #ifdef __cplusplus
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347
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348 class Cyg_SpinLock
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349 {
182
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350 volatile cyg_uint32 lock;
177
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351
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352 public:
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353
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354 // Constructor, initialize the lock to clear
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355 Cyg_SpinLock() { lock = 0; };
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356
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357 ~Cyg_SpinLock()
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358 {
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359 CYG_ASSERT( lock == 0, "spinlock still claimed");
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360 };
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361
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362 // Spin on the lock. In this case we just set it to 1 and proceed.
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363 void spin()
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364 {
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365 CYG_ASSERT( lock == 0, "spinlock already claimed!");
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366 lock = 1;
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367 };
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368
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369 // Clear the lock. Again, just set the value.
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370 void clear()
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371 {
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372 CYG_ASSERT( lock != 0, "spinlock already cleared!");
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373 lock = 0;
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374 };
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375
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376 // Try to claim the lock. Return true if successful, false if not.
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377 cyg_bool trylock()
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378 {
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379 if( lock ) return false;
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380 else { lock = 1; return true; }
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381 };
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382
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383 // Test the current value of the lock
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384 cyg_bool test() { return lock; };
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385
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386
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387 // The following two member functions are only necessary if the
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388 // spinlock is to be used in an ISR.
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389
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390 // Claim the spinlock, but also mask this CPU's interrupts while
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391 // we have it.
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392 void spin_intsave(CYG_INTERRUPT_STATE *state)
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393 {
178
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394 CYG_INTERRUPT_STATE s;
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395 HAL_DISABLE_INTERRUPTS(s);
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396 *state = s;
177
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397 spin();
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398 };
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399
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400 // Clear the lock, and restore the interrupt state saved in
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401 // spin_intsave().
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402 void clear_intsave(CYG_INTERRUPT_STATE state)
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403 {
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404 clear();
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405 HAL_RESTORE_INTERRUPTS(state);
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406 };
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407
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408 };
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409
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410 // -------------------------------------------------------------------------
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411 // Scheduler lock class
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412
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413 class Cyg_Scheduler_SchedLock
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414 {
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415 static volatile cyg_ucount32 sched_lock // lock counter
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416 CYGBLD_ATTRIB_ASM_ALIAS( cyg_scheduler_sched_lock )
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417 CYGBLD_ANNOTATE_VARIABLE_SCHED
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418 ;
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419
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420 // For non-SMP versions, the code here does the basic and obvious things.
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421 protected:
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422
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423 Cyg_Scheduler_SchedLock()
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424 {
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425 sched_lock = 1;
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426 };
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427
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428 // Increment the scheduler lock, possibly taking it from zero to
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429 // one.
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430 static void inc_sched_lock()
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431 {
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432 sched_lock++;
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433 };
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434
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435 static void zero_sched_lock()
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436 {
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437 CYG_ASSERT( sched_lock != 0, "Scheduler lock already zero");
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438 sched_lock = 0;
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439 };
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440
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441 // Set the scheduler lock to a non-zero value. Both the scheduler
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442 // lock and the new value must be non-zero.
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443 static void set_sched_lock(cyg_uint32 new_lock)
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444 {
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445 CYG_ASSERT( new_lock > 0, "New scheduler lock value == 0");
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446 CYG_ASSERT( sched_lock > 0, "Scheduler lock == 0");
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447 sched_lock = new_lock;
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448 };
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449
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450 static cyg_ucount32 get_sched_lock()
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451 {
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452 return sched_lock;
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453 };
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454 };
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455
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456 #define CYGIMP_KERNEL_SCHED_LOCK_DEFINITIONS \
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457 volatile cyg_ucount32 Cyg_Scheduler_SchedLock::sched_lock = 1;
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458
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459 #endif // __cplusplus
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460
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461 #endif // defined(CYGSEM_KERNEL_SMP_SUPPORT) && (CYGSEM_HAL_SMP_SUPPORT)
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462
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463 // -------------------------------------------------------------------------
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464 #endif // ifndef CYGONCE_KERNEL_SMP_HXX
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465
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466 // EOF smp.hxx