Mercurial > ecos
annotate packages/kernel/current/src/intr/intr.cxx @ 38:e7ba79f6d3a8 ecos-sw-1999-09-23
Merge from eCos master repository on 1999-09-23-20:10:25-BST
| author | jlarmour |
|---|---|
| date | Thu, 23 Sep 1999 19:52:27 +0000 |
| parents | 7253dcc42a09 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 26 // ------------------------------------------- |
| 27 // | |
| 28 //####COPYRIGHTEND#### | |
| 29 //========================================================================== | |
| 30 //#####DESCRIPTIONBEGIN#### | |
| 31 // | |
| 2 | 32 // Author(s): nickg |
| 33 // Contributors: nickg | |
| 34 // Date: 1999-02-17 | |
| 35 // Purpose: Interrupt class implementation | |
| 36 // Description: This file contains the definitions of the interrupt | |
| 37 // class. | |
| 0 | 38 // |
| 39 //####DESCRIPTIONEND#### | |
| 40 // | |
| 41 //========================================================================== | |
| 42 | |
| 43 #include <pkgconf/kernel.h> | |
| 44 | |
| 45 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 46 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 47 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 48 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 49 | |
| 50 #include <cyg/kernel/intr.hxx> // our header | |
| 51 | |
| 52 #include <cyg/kernel/sched.hxx> // scheduler | |
| 53 | |
| 54 #include <cyg/kernel/sched.inl> | |
| 55 | |
| 56 // ------------------------------------------------------------------------- | |
| 2 | 57 // Statics |
| 58 | |
| 59 // Interrupt disable counter. Note that this is initialized to 1 since | |
| 60 // enable_interrupts() is called in Cyg_Scheduler::start(). | |
| 61 | |
| 62 cyg_int32 Cyg_Interrupt::disable_counter = 1; | |
| 63 | |
| 64 // ------------------------------------------------------------------------- | |
| 0 | 65 |
| 66 Cyg_Interrupt::Cyg_Interrupt( | |
| 67 cyg_vector vec, // Vector to attach to | |
| 68 cyg_priority pri, // Queue priority | |
| 69 CYG_ADDRWORD d, // Data pointer | |
| 70 cyg_ISR *ir, // Interrupt Service Routine | |
| 71 cyg_DSR *dr // Deferred Service Routine | |
| 72 ) | |
| 73 { | |
| 2 | 74 CYG_REPORT_FUNCTION(); |
| 75 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 76 "dsr=%08x", vec, pri, d, ir, dr); | |
| 77 | |
| 0 | 78 vector = vec; |
| 79 priority = pri; | |
| 80 isr = ir; | |
| 81 dsr = dr; | |
| 82 data = d; | |
| 83 | |
| 84 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 85 | |
| 86 dsr_count = 0; | |
| 87 next_dsr = NULL; | |
| 88 | |
| 89 #endif | |
| 90 | |
| 91 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 92 | |
| 93 next = NULL; | |
| 94 | |
| 95 #endif | |
| 2 | 96 |
| 97 CYG_REPORT_RETURN(); | |
| 0 | 98 |
| 99 }; | |
| 100 | |
| 101 // ------------------------------------------------------------------------- | |
| 102 | |
| 103 Cyg_Interrupt::~Cyg_Interrupt() | |
| 104 { | |
| 2 | 105 CYG_REPORT_FUNCTION(); |
| 0 | 106 detach(); |
| 2 | 107 CYG_REPORT_RETURN(); |
| 0 | 108 }; |
| 109 | |
| 110 // ------------------------------------------------------------------------- | |
| 111 // DSR handling statics: | |
| 112 | |
| 113 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 114 | |
| 2 | 115 Cyg_Interrupt * |
| 116 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; | |
| 0 | 117 |
| 118 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; | |
| 119 | |
| 120 cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; | |
| 121 | |
| 122 #endif | |
| 123 | |
| 124 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 125 | |
| 126 Cyg_Interrupt *Cyg_Interrupt::dsr_list = NULL; | |
| 127 | |
| 128 #endif | |
| 129 | |
| 130 // ------------------------------------------------------------------------- | |
| 131 // Call any pending DSRs | |
| 132 | |
| 2 | 133 void |
| 134 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 135 { |
| 136 // CYG_REPORT_FUNCTION(); | |
| 137 | |
| 138 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 139 | |
| 140 while( dsr_table_head != dsr_table_tail ) | |
| 141 { | |
| 142 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; | |
| 143 | |
| 144 dsr_table_head++; | |
| 145 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 146 dsr_table_head = 0; | |
| 147 | |
| 148 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 149 | |
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150 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
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151 |
| 0 | 152 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 153 } | |
| 154 | |
| 155 #endif | |
| 156 | |
| 157 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 158 | |
| 159 while( dsr_list != NULL ) | |
| 160 { | |
| 161 Cyg_Interrupt *intr; | |
| 162 cyg_uint32 old_intr; | |
| 163 cyg_count32 count; | |
| 164 | |
| 165 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 166 | |
| 167 intr = dsr_list; | |
| 168 dsr_list = intr->next_dsr; | |
| 169 count = intr->dsr_count; | |
| 170 intr->dsr_count = 0; | |
| 171 | |
| 172 HAL_RESTORE_INTERRUPTS(old_intr); | |
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173 |
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174 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 175 |
| 176 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 177 | |
| 178 } | |
| 179 | |
| 180 #endif | |
| 181 | |
| 182 }; | |
| 183 | |
| 2 | 184 externC void |
| 185 cyg_interrupt_call_pending_DSRs(void) | |
| 186 { | |
| 187 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 188 } | |
| 189 | |
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190 // |
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191 // Use HAL supported function to run through the DSRs, but executing using |
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192 // the separate interrupt stack if available. This function calls back |
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193 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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194 // the whole process as general as possible. |
| 2 | 195 |
| 196 void | |
| 197 Cyg_Interrupt::call_pending_DSRs(void) | |
| 198 { | |
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199 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 200 } |
| 201 | |
| 202 | |
| 0 | 203 // ------------------------------------------------------------------------- |
| 204 | |
| 2 | 205 void |
| 206 Cyg_Interrupt::post_dsr(void) | |
| 0 | 207 { |
| 208 // CYG_REPORT_FUNCTION(); | |
| 209 | |
| 210 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); | |
| 211 | |
| 212 cyg_uint32 old_intr; | |
| 213 | |
| 214 // We need to disable interrupts during this part to | |
| 215 // guard against nested interrupts. | |
| 216 | |
| 217 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 218 | |
| 219 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 220 | |
| 221 dsr_table[dsr_table_tail++] = this; | |
| 222 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 223 dsr_table_tail = 0; | |
| 224 | |
| 225 #endif | |
| 226 | |
| 227 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 228 | |
| 229 // Only add the interrupt to the dsr list if this is | |
| 230 // the first DSR call. | |
| 231 // At present DSRs are pushed onto the list and will be | |
| 232 // called in reverse order. We do not define the order | |
| 233 // in which DSRs are called, so this is acceptable. | |
| 234 | |
| 235 if( dsr_count++ == 0 ) | |
| 236 { | |
| 237 next_dsr = dsr_list; | |
| 238 dsr_list = this; | |
| 239 } | |
| 240 | |
| 241 #endif | |
| 242 | |
| 243 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 244 }; | |
| 245 | |
| 246 // ------------------------------------------------------------------------- | |
| 2 | 247 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 248 // the HAL. | |
| 0 | 249 |
| 2 | 250 externC void |
| 251 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 252 { | |
| 253 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 254 intr->post_dsr (); | |
| 255 } | |
| 256 | |
| 257 // ------------------------------------------------------------------------- | |
| 258 | |
| 259 // FIXME: should have better name - Jifl | |
| 260 externC void | |
| 261 interrupt_end( | |
| 0 | 262 cyg_uint32 isr_ret, |
| 263 Cyg_Interrupt *intr, | |
| 264 HAL_SavedRegisters *regs | |
| 265 ) | |
| 266 { | |
| 267 // CYG_REPORT_FUNCTION(); | |
| 268 | |
| 2 | 269 // Sometimes we have a NULL intr object pointer. |
| 270 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
| 271 | |
| 272 CYG_INSTRUMENT_INTR(END, vector, isr_ret); | |
| 273 | |
| 274 | |
| 0 | 275 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 276 | |
| 277 // Only do this if we are in a non-chained configuration. | |
| 278 // If we are chained, then chain_isr below will do the DSR | |
| 279 // posting. | |
| 280 | |
| 2 | 281 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 282 |
| 283 #endif | |
| 284 | |
| 285 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 286 | |
| 287 // If we have GDB support enabled, and there is the possibility | |
| 288 // that this thread will be context switched as a result of this | |
| 289 // interrupt, then save the pointer to the saved thread context in | |
| 290 // the thread object so that GDB can get a meaningful context to | |
| 291 // look at. | |
| 292 | |
| 293 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 294 | |
| 295 #endif | |
| 296 | |
| 297 // Now unlock the scheduler, which may also call DSRs | |
| 298 // and cause a thread switch to happen. | |
| 299 | |
| 300 Cyg_Scheduler::unlock(); | |
| 301 | |
| 302 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 303 | |
| 304 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 305 | |
| 306 #endif | |
| 307 | |
| 2 | 308 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 309 } |
| 310 | |
| 311 // ------------------------------------------------------------------------- | |
| 312 // Interrupt chaining statics. | |
| 313 | |
| 314 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 315 | |
| 2 | 316 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_COUNT]; |
| 0 | 317 |
| 318 #endif | |
| 319 | |
| 320 // ------------------------------------------------------------------------- | |
| 321 // Chaining ISR inserted in HAL vector | |
| 322 | |
| 323 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 324 | |
| 2 | 325 cyg_uint32 |
| 326 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 327 { |
| 328 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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329 register cyg_uint32 isr_ret = 0; |
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330 |
| 0 | 331 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 332 | |
| 333 while( p != NULL ) | |
| 334 { | |
| 335 if( p->vector == vector ) | |
| 336 { | |
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337 isr_ret = p->isr(vector, p->data); |
| 0 | 338 |
| 2 | 339 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 340 |
| 2 | 341 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 342 } |
| 343 | |
| 344 p = p->next; | |
| 345 } | |
| 346 | |
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347 #ifdef HAL_DEFAULT_ISR |
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348 if( (isr_ret & Cyg_Interrupt::HANDLED) == 0 ) |
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349 { |
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350 // If we finished the loop for some reason other than that an |
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351 // ISR has handled the interrupt, call any default ISR to either |
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352 // report the spurious interrupt, or do some other HAL level processing |
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353 // such as GDB interrupt detection etc. |
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354 |
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355 HAL_DEFAULT_ISR( vector, NULL ); |
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356 } |
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357 #endif |
| 0 | 358 return 0; |
| 359 } | |
| 360 | |
| 361 #endif | |
| 362 | |
| 363 // ------------------------------------------------------------------------- | |
| 364 // Attach an ISR to an interrupt vector. | |
| 365 | |
| 2 | 366 void |
| 367 Cyg_Interrupt::attach(void) | |
| 0 | 368 { |
| 369 CYG_REPORT_FUNCTION(); | |
| 370 | |
| 2 | 371 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 372 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 373 |
| 374 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 375 | |
| 376 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 377 | |
| 378 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 379 | |
| 380 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 381 | |
| 382 cyg_uint32 index; | |
| 383 | |
| 384 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 385 | |
| 386 if( chain_list[index] == NULL ) | |
| 387 { | |
| 2 | 388 int in_use; |
| 0 | 389 // First Interrupt on this chain, just assign it and register |
| 390 // the chain_isr with the HAL. | |
| 391 | |
| 392 chain_list[index] = this; | |
| 393 | |
| 2 | 394 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 395 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 396 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 397 } | |
| 398 else | |
| 399 { | |
| 400 // There are already interrupts chained, add this one into the | |
| 401 // chain in priority order. | |
| 402 | |
| 403 Cyg_Interrupt **p = &chain_list[index]; | |
| 404 | |
| 405 while( *p != NULL ) | |
| 406 { | |
| 407 Cyg_Interrupt *n = *p; | |
| 408 | |
| 409 if( n->priority < priority ) break; | |
| 410 | |
| 411 p = &n->next; | |
| 412 } | |
| 413 next = *p; | |
| 414 *p = this; | |
| 415 } | |
| 416 | |
| 417 #else | |
| 418 | |
| 2 | 419 { |
| 420 int in_use; | |
| 421 | |
| 422 | |
| 423 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 424 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 425 | |
| 426 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 427 } | |
| 0 | 428 |
| 429 #endif | |
| 2 | 430 CYG_REPORT_RETURN(); |
| 0 | 431 } |
| 432 | |
| 433 // ------------------------------------------------------------------------- | |
| 434 // Detach the ISR from the vector | |
| 435 | |
| 2 | 436 void |
| 437 Cyg_Interrupt::detach(void) | |
| 0 | 438 { |
| 439 CYG_REPORT_FUNCTION(); | |
| 440 | |
| 2 | 441 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 442 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 443 |
| 444 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 445 | |
| 446 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 447 | |
| 448 // Remove the interrupt object from the vector chain. | |
| 449 | |
| 2 | 450 cyg_uint32 index; |
| 451 | |
| 452 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 453 | |
| 454 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 455 |
| 456 while( *p != NULL ) | |
| 457 { | |
| 458 Cyg_Interrupt *n = *p; | |
| 459 | |
| 460 if( n == this ) | |
| 461 { | |
| 462 *p = next; | |
| 463 break; | |
| 464 } | |
| 465 | |
| 466 p = &n->next; | |
| 467 } | |
| 468 | |
| 469 // If this was the last one, detach the vector. | |
| 470 | |
| 2 | 471 if( chain_list[index] == NULL ) |
| 0 | 472 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 473 | |
| 474 #else | |
| 475 | |
| 476 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 477 | |
| 478 #endif | |
| 2 | 479 |
| 480 CYG_REPORT_RETURN(); | |
| 0 | 481 |
| 482 } | |
| 483 | |
| 484 // ------------------------------------------------------------------------- | |
| 485 // Get the current service routine | |
| 486 | |
| 2 | 487 void |
| 488 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 489 { |
| 490 CYG_REPORT_FUNCTION(); | |
| 2 | 491 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 492 vsr); | |
| 0 | 493 |
| 2 | 494 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 495 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 496 |
| 497 HAL_VSR_GET( vector, vsr ); | |
| 2 | 498 |
| 499 CYG_REPORT_RETURN(); | |
| 0 | 500 } |
| 501 | |
| 502 // ------------------------------------------------------------------------- | |
| 503 // Install a vector service routine | |
| 504 | |
| 2 | 505 void |
| 506 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 507 { |
| 508 CYG_REPORT_FUNCTION(); | |
| 509 | |
| 2 | 510 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 511 "old VSR in is at %08x", vector, vsr, old); | |
| 512 | |
| 0 | 513 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 514 | |
| 2 | 515 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 516 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 517 |
| 518 CYG_INTERRUPT_STATE old_ints; | |
| 519 | |
| 520 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 521 | |
| 522 HAL_VSR_SET( vector, vsr, old ); | |
| 523 | |
| 524 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 525 |
| 526 CYG_REPORT_RETURN(); | |
| 0 | 527 } |
| 528 | |
| 529 // ------------------------------------------------------------------------- | |
| 530 // Disable interrupts at the CPU | |
| 531 | |
| 532 | |
| 2 | 533 void |
| 534 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 535 { |
| 536 CYG_REPORT_FUNCTION(); | |
| 537 | |
| 2 | 538 CYG_INSTRUMENT_INTR(DISABLE, disable_counter+1, 0); |
| 0 | 539 |
| 540 CYG_INTERRUPT_STATE dummy; | |
| 541 | |
| 542 HAL_DISABLE_INTERRUPTS(dummy); | |
| 543 | |
| 2 | 544 CYG_ASSERT( disable_counter >= 0 , "Disable counter negative"); |
| 545 | |
| 546 disable_counter++; | |
| 547 | |
| 548 CYG_REPORT_RETURN(); | |
| 0 | 549 } |
| 550 | |
| 551 | |
| 552 // ------------------------------------------------------------------------- | |
| 553 // Re-enable CPU interrupts | |
| 554 | |
| 2 | 555 void |
| 556 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 557 { |
| 558 CYG_REPORT_FUNCTION(); | |
| 559 | |
| 2 | 560 CYG_INSTRUMENT_INTR(ENABLE, disable_counter, 0); |
| 561 | |
| 562 CYG_ASSERT( disable_counter > 0 , "Disable counter not greater than zero"); | |
| 563 | |
| 564 disable_counter--; | |
| 0 | 565 |
| 2 | 566 if ( disable_counter == 0 ) |
| 567 { | |
| 568 HAL_ENABLE_INTERRUPTS(); | |
| 569 } | |
| 570 | |
| 571 CYG_REPORT_RETURN(); | |
| 0 | 572 } |
| 573 | |
| 574 // ------------------------------------------------------------------------- | |
| 575 // Mask a specific interrupt in a PIC | |
| 576 | |
| 2 | 577 void |
| 578 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 579 { |
| 580 CYG_REPORT_FUNCTION(); | |
| 2 | 581 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 582 |
| 2 | 583 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 584 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 585 |
| 586 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 587 | |
| 2 | 588 HAL_INTERRUPT_MASK( vector ); |
| 589 | |
| 590 CYG_REPORT_RETURN(); | |
| 0 | 591 } |
| 592 | |
| 593 // ------------------------------------------------------------------------- | |
| 594 // Clear PIC mask | |
| 595 | |
| 2 | 596 void |
| 597 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 598 { |
| 599 CYG_REPORT_FUNCTION(); | |
| 600 | |
| 2 | 601 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 602 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 603 |
| 604 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 605 | |
| 606 HAL_INTERRUPT_UNMASK( vector ); | |
| 2 | 607 |
| 608 CYG_REPORT_RETURN(); | |
| 0 | 609 } |
| 610 | |
| 611 | |
| 612 // ------------------------------------------------------------------------- | |
| 613 // Acknowledge interrupt at PIC | |
| 614 | |
| 2 | 615 void |
| 616 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 617 { |
| 618 // CYG_REPORT_FUNCTION(); | |
| 619 | |
| 2 | 620 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 621 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 622 |
| 623 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 624 | |
| 625 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 626 } | |
| 627 | |
| 628 // ------------------------------------------------------------------------- | |
| 629 // Change interrupt detection at PIC | |
| 630 | |
| 2 | 631 void |
| 632 Cyg_Interrupt::configure_interrupt( | |
| 0 | 633 cyg_vector vector, // vector to control |
| 634 cyg_bool level, // level or edge triggered | |
| 635 cyg_bool up // hi/lo level, rising/falling edge | |
| 636 ) | |
| 637 { | |
| 638 CYG_REPORT_FUNCTION(); | |
| 2 | 639 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 640 up); | |
| 0 | 641 |
| 2 | 642 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 643 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 644 |
| 645 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 646 | |
| 647 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 648 |
| 649 CYG_REPORT_RETURN(); | |
| 0 | 650 } |
| 651 | |
| 652 // ------------------------------------------------------------------------- | |
| 653 // EOF intr/intr.cxx |