Mercurial > ecos
annotate packages/hal/arm/aeb/current/src/plf_stub.c @ 36:e97d78785e2d ecos-sw-1999-09-12
Merge from eCos master repository on 1999-09-12-15:40:34-BST
| author | jlarmour |
|---|---|
| date | Sun, 12 Sep 1999 15:26:05 +0000 |
| parents | 443894e2e912 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 //============================================================================= |
| 2 // | |
| 3 // plf_stub.c | |
| 4 // | |
| 5 // Platform specific code for GDB stub support. | |
| 6 // | |
| 7 //============================================================================= | |
| 8 //####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. | |
| 26 // All Rights Reserved. | |
| 27 // ------------------------------------------- | |
| 28 // | |
| 29 //####COPYRIGHTEND#### | |
| 30 //============================================================================= | |
| 31 //#####DESCRIPTIONBEGIN#### | |
| 32 // | |
| 33 // Author(s): gthomas (based on the old ARM/AEB hal_stub.c) | |
| 34 // Contributors:gthomas, jskov | |
| 35 // Date: 1999-02-15 | |
| 36 // Purpose: Platform specific code for GDB stub support. | |
| 37 // | |
| 38 //####DESCRIPTIONEND#### | |
| 39 // | |
| 40 //============================================================================= | |
| 41 | |
| 42 #include <pkgconf/hal.h> | |
| 43 | |
| 44 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 45 | |
| 46 #include <cyg/hal/hal_stub.h> | |
| 47 | |
| 48 #include <cyg/hal/hal_io.h> // HAL IO macros | |
| 49 #include <cyg/hal/hal_intr.h> // HAL interrupt macros | |
| 50 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 51 #include <cyg/hal/drv_api.h> // HAL ISR support | |
| 52 #endif | |
| 53 | |
| 54 //----------------------------------------------------------------------------- | |
| 55 // Serial definitions. | |
| 56 | |
| 57 // 38400, UART1 | |
| 58 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0 | |
| 59 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB (13*3) | |
| 60 | |
| 61 // This is the base address of UART1 on the AEB-1 board. | |
| 62 #define CYG_DEVICE_SERIAL_RS232_16550_BASE 0xFFFF0400 | |
| 63 | |
| 64 // Define the serial registers. | |
| 65 #define CYG_DEVICE_SERIAL_RS232_16550_RBR \ | |
| 66 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 67 // receiver buffer register, read, dlab = 0 | |
| 68 #define CYG_DEVICE_SERIAL_RS232_16550_THR \ | |
| 69 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 70 // transmitter holding register, write, dlab = 0 | |
| 71 #define CYG_DEVICE_SERIAL_RS232_16550_DLL \ | |
| 72 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 73 // divisor latch (LS), read/write, dlab = 1 | |
| 74 #define CYG_DEVICE_SERIAL_RS232_16550_IER \ | |
| 75 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04) | |
| 76 // interrupt enable register, read/write, dlab = 0 | |
| 77 #define CYG_DEVICE_SERIAL_RS232_16550_DLM \ | |
| 78 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04) | |
| 79 // divisor latch (MS), read/write, dlab = 1 | |
| 80 #define CYG_DEVICE_SERIAL_RS232_16550_IIR \ | |
| 81 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) | |
| 82 // interrupt identification register, read, dlab = 0 | |
| 83 #define CYG_DEVICE_SERIAL_RS232_16550_FCR \ | |
| 84 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) | |
| 85 // fifo control register, write, dlab = 0 | |
| 86 #define CYG_DEVICE_SERIAL_RS232_16550_LCR \ | |
| 87 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x0C) | |
| 88 // line control register, read/write | |
| 89 #define CYG_DEVICE_SERIAL_RS232_16550_MCR \ | |
| 90 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10) | |
| 91 // modem control register, read/write | |
| 92 #define CYG_DEVICE_SERIAL_RS232_16550_LSR \ | |
| 93 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x14) | |
| 94 // line status register, read | |
| 95 #define CYG_DEVICE_SERIAL_RS232_16550_MSR \ | |
| 96 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x18) | |
| 97 // modem status register, read | |
| 98 | |
| 99 // The interrupt enable register bits. | |
| 100 #define SIO_IER_ERDAI 0x01 // enable received data available irq | |
| 101 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt | |
| 102 #define SIO_IER_ELSI 0x04 // enable receiver line status irq | |
| 103 #define SIO_IER_EMSI 0x08 // enable modem status interrupt | |
| 104 | |
| 105 // The interrupt identification register bits. | |
| 106 #define SIO_IIR_IP 0x01 // 0 if interrupt pending | |
| 107 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits | |
| 108 | |
| 109 // The line status register bits. | |
| 110 #define SIO_LSR_DR 0x01 // data ready | |
| 111 #define SIO_LSR_OE 0x02 // overrun error | |
| 112 #define SIO_LSR_PE 0x04 // parity error | |
| 113 #define SIO_LSR_FE 0x08 // framing error | |
| 114 #define SIO_LSR_BI 0x10 // break interrupt | |
| 115 #define SIO_LSR_THRE 0x20 // transmitter holding register empty | |
| 116 #define SIO_LSR_TEMT 0x40 // transmitter register empty | |
| 117 #define SIO_LSR_ERR 0x80 // any error condition | |
| 118 | |
| 119 // The modem status register bits. | |
| 120 #define SIO_MSR_DCTS 0x01 // delta clear to send | |
| 121 #define SIO_MSR_DDSR 0x02 // delta data set ready | |
| 122 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator | |
| 123 #define SIO_MSR_DDCD 0x08 // delta data carrier detect | |
| 124 #define SIO_MSR_CTS 0x10 // clear to send | |
| 125 #define SIO_MSR_DSR 0x20 // data set ready | |
| 126 #define SIO_MSR_RI 0x40 // ring indicator | |
| 127 #define SIO_MSR_DCD 0x80 // data carrier detect | |
| 128 | |
| 129 // The line control register bits. | |
| 130 #define SIO_LCR_WLS0 0x01 // word length select bit 0 | |
| 131 #define SIO_LCR_WLS1 0x02 // word length select bit 1 | |
| 132 #define SIO_LCR_STB 0x04 // number of stop bits | |
| 133 #define SIO_LCR_PEN 0x08 // parity enable | |
| 134 #define SIO_LCR_EPS 0x10 // even parity select | |
| 135 #define SIO_LCR_SP 0x20 // stick parity | |
| 136 #define SIO_LCR_SB 0x40 // set break | |
| 137 #define SIO_LCR_DLAB 0x80 // divisor latch access bit | |
| 138 | |
| 139 // Interrupt Enable Register | |
| 140 #define SIO_IER_RCV 0x01 | |
| 141 #define SIO_IER_XMT 0x02 | |
| 142 #define SIO_IER_LS 0x04 | |
| 143 #define SIO_IER_MS 0x08 | |
| 144 | |
| 145 // Modem Control Register | |
| 146 #define SIO_MCR_DTR 0x01 | |
| 147 #define SIO_MCR_RTS 0x02 | |
| 148 #define SIO_MCR_INT 0x08 // Enable interrupts | |
| 149 | |
| 150 #define LED (volatile char *)0xFFFF1C0C | |
| 151 | |
| 152 #define LED1 (7<<1) | |
| 153 #define LED2 (6<<1) | |
| 154 #define LED3 (5<<1) | |
| 155 #define LED4 (4<<1) | |
| 156 | |
| 157 #define LED_ON 0x01 | |
| 158 #define LED_OFF 0x00 | |
| 159 | |
| 160 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 161 static cyg_interrupt gdb_interrupt; | |
| 162 static cyg_handle_t gdb_interrupt_handle; | |
| 163 #endif | |
| 164 | |
| 165 //----------------------------------------------------------------------------- | |
| 166 | |
| 167 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 168 // This ISR is called only for serial receive interrupts. | |
| 169 int | |
| 170 cyg_hal_gdb_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) | |
| 171 { | |
| 172 cyg_uint8 c; | |
| 173 | |
| 174 c = hal_aeb_get_char(); // Fetch the character | |
| 175 if( 3 == c ) { // ^C | |
| 176 // Ctrl-C: set a breakpoint at PC so GDB will display the | |
| 177 // correct program context when stopping rather than the | |
| 178 // interrupt handler. | |
| 179 cyg_hal_gdb_interrupt (regs->pc); | |
| 180 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_UART1); | |
| 181 } | |
| 182 return 0; // No need to run DSR | |
| 183 } | |
| 184 | |
| 185 int | |
| 186 hal_aeb_interruptible(int state) | |
| 187 { | |
| 188 if (state) { | |
| 189 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_UART1); | |
| 190 } else { | |
| 191 cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_UART1); | |
| 192 } | |
| 193 | |
| 194 return 0; | |
| 195 } | |
| 196 #endif | |
| 197 | |
| 198 static void dummy(void) {} | |
| 199 | |
| 200 // Initialize the current serial port. | |
| 201 void hal_aeb_init_serial(void) | |
| 202 { | |
| 203 cyg_uint8 lcr; | |
| 204 | |
| 205 // 8-1-no parity. | |
| 206 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, | |
| 207 SIO_LCR_WLS0 | SIO_LCR_WLS1); | |
| 208 | |
| 209 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 210 lcr |= SIO_LCR_DLAB; | |
| 211 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 212 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLL, | |
| 213 CYG_DEVICE_SERIAL_RS232_BAUD_LSB); | |
| 214 dummy(); // FIXME! - GCC bug | |
| 215 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLM, | |
| 216 CYG_DEVICE_SERIAL_RS232_BAUD_MSB); | |
| 217 lcr &= ~SIO_LCR_DLAB; | |
| 218 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 219 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_FCR, 0x07); // Enable & clear FIFO | |
| 220 | |
| 221 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 222 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_UART1, | |
| 223 99, // Priority - what goes here? | |
| 224 0, // Data item passed to interrupt handler | |
| 225 cyg_hal_gdb_isr, | |
| 226 0, | |
| 227 &gdb_interrupt_handle, | |
| 228 &gdb_interrupt); | |
| 229 cyg_drv_interrupt_attach(gdb_interrupt_handle); | |
| 230 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_UART1); | |
| 231 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_IER, SIO_IER_RCV); | |
| 232 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS); | |
| 233 #endif | |
| 234 } | |
| 235 | |
| 236 // Write C to the current serial port. | |
| 237 void hal_aeb_put_char(int c) | |
| 238 { | |
| 239 cyg_uint8 lsr; | |
| 240 static int led_state = LED_ON; | |
| 241 | |
| 242 do { | |
| 243 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr); | |
| 244 } while ((lsr & SIO_LSR_THRE) == 0); | |
| 245 | |
| 246 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c); | |
| 247 *LED = led_state | LED1; | |
| 248 if (led_state == LED_ON) { | |
| 249 led_state = LED_OFF; | |
| 250 } else { | |
| 251 led_state = LED_ON; | |
| 252 } | |
| 253 } | |
| 254 | |
| 255 // Read one character from the current serial port. | |
| 256 int hal_aeb_get_char(void) | |
| 257 { | |
| 258 char c; | |
| 259 cyg_uint8 lsr; | |
| 260 | |
| 261 do { | |
| 262 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr); | |
| 263 } while ((lsr & SIO_LSR_DR) == 0); | |
| 264 | |
| 265 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, c); | |
| 266 return c; | |
| 267 } | |
| 268 | |
|
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269 |
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270 //----------------------------------------------------------------------------- |
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271 // Reset board (definitions from watchdog file aeb1.cxx) |
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272 |
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273 // Register definitions |
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274 #define CYGARC_REG_WATCHDOG_BASE 0xFFFFAC00 |
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275 #define CYGARC_REG_WATCHDOG_WDCTLR (CYGARC_REG_WATCHDOG_BASE+0x30) |
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276 #define CYGARC_REG_WATCHDOG_WDCNTR (CYGARC_REG_WATCHDOG_BASE+0x34) |
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277 |
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278 // Control register bits |
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279 #define CYGARC_REG_WATCHDOG_WDCTLR_EN 0x01 // enable |
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280 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_NMF 0x00 // non-maskable fiq |
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281 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_ER 0x04 // external reset |
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282 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR 0x06 // system reset |
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283 #define CYGARC_REG_WATCHDOG_WDCTLR_FRZ 0x08 // lock enable bit |
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284 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_MASK 0x70 // time out period |
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285 |
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286 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17 0x00 // 2^17 |
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287 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17_P 5242880 // = 5.2ms |
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288 |
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289 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25 0x40 // 2^25 |
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290 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P 1342177300 // = 1.3421773s |
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291 |
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292 void |
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293 hal_aeb_reset(void) |
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294 { |
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295 // Clear the watchdog counter. |
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296 HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0); |
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297 |
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298 // Enable the watchdog with the smallest timeout. |
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299 HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR, |
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300 (CYGARC_REG_WATCHDOG_WDCTLR_TOP_17 |
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301 | CYGARC_REG_WATCHDOG_WDCTLR_FRZ |
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302 | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR |
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303 | CYGARC_REG_WATCHDOG_WDCTLR_EN)); |
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304 |
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305 // Wait for it... |
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306 for(;;); |
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307 } |
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308 |
| 2 | 309 #endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
| 310 //----------------------------------------------------------------------------- | |
| 311 // End of plf_stub.c |