Mercurial > ecos
annotate packages/hal/mips/arch/current/include/hal_intr.h @ 8:ece80412419a ecos-sw-1999-05-21
Merge from eCos master repository on 1999-05-21-22:05:54-BST
| author | jlarmour |
|---|---|
| date | Fri, 21 May 1999 15:09:30 +0000 |
| parents | d376b777e2ce |
| children | d3fbcdfa1b2f |
| rev | line source |
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| 0 | 1 #ifndef CYGONCE_HAL_HAL_INTR_H |
| 2 #define CYGONCE_HAL_HAL_INTR_H | |
| 3 | |
| 2 | 4 //========================================================================== |
| 0 | 5 // |
| 2 | 6 // hal_intr.h |
| 0 | 7 // |
| 2 | 8 // HAL Interrupt and clock support |
| 0 | 9 // |
| 2 | 10 //========================================================================== |
| 0 | 11 //####COPYRIGHTBEGIN#### |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 2 | 32 //========================================================================== |
| 0 | 33 //#####DESCRIPTIONBEGIN#### |
| 34 // | |
| 2 | 35 // Author(s): nickg |
| 36 // Contributors: nickg, jskov, | |
| 37 // gthomas, jlarmour | |
| 38 // Date: 1999-02-16 | |
| 39 // Purpose: Define Interrupt support | |
| 40 // Description: The macros defined here provide the HAL APIs for handling | |
| 41 // interrupts and the clock. | |
| 0 | 42 // |
| 43 // Usage: | |
| 2 | 44 // #include <cyg/hal/hal_intr.h> |
| 45 // ... | |
| 46 // | |
| 0 | 47 // |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 2 | 50 //========================================================================== |
| 0 | 51 |
| 52 #include <pkgconf/hal.h> | |
| 53 | |
| 54 #include <cyg/infra/cyg_type.h> | |
| 55 #include <cyg/hal/hal_io.h> | |
| 56 | |
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57 #include <cyg/hal/var_intr.h> |
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58 |
| 2 | 59 //-------------------------------------------------------------------------- |
| 60 // MIPS vectors. | |
| 0 | 61 |
| 2 | 62 // These are the exception codes presented in the Cause register and |
| 63 // correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET | |
| 0 | 64 |
| 2 | 65 // External interrupt |
| 66 #define CYGNUM_HAL_VECTOR_INTERRUPT 0 | |
| 67 // TLB modification exception | |
| 68 #define CYGNUM_HAL_VECTOR_TLB_MOD 1 | |
| 69 // TLB miss (Load or IFetch) | |
| 70 #define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2 | |
| 71 // TLB miss (Store) | |
| 72 #define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3 | |
| 73 // Address error (Load or Ifetch) | |
| 74 #define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4 | |
| 75 // Address error (store) | |
| 76 #define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5 | |
| 77 // Bus error (Ifetch) | |
| 78 #define CYGNUM_HAL_VECTOR_IBE 6 | |
| 79 // Bus error (data load or store) | |
| 80 #define CYGNUM_HAL_VECTOR_DBE 7 | |
| 81 // System call | |
| 82 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8 | |
| 83 // Break point | |
| 84 #define CYGNUM_HAL_VECTOR_BREAKPOINT 9 | |
| 85 // Reserved instruction | |
| 86 #define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10 | |
| 87 // Coprocessor unusable | |
| 88 #define CYGNUM_HAL_VECTOR_COPROCESSOR 11 | |
| 89 // Arithmetic overflow | |
| 90 #define CYGNUM_HAL_VECTOR_OVERFLOW 12 | |
| 91 // Reserved | |
| 92 #define CYGNUM_HAL_VECTOR_RESERVED_13 13 | |
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93 // Floating point exception |
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94 #ifdef CYGHWR_HAL_MIPS_FPU |
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95 #define CYGNUM_HAL_VECTOR_FPE 15 |
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96 #endif |
| 0 | 97 |
| 2 | 98 #define CYGNUM_HAL_VSR_MIN 0 |
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99 #define CYGNUM_HAL_VSR_MAX 15 |
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100 #define CYGNUM_HAL_VSR_COUNT 16 |
| 2 | 101 |
| 102 // Exception vectors. These are the values used when passed out to an | |
| 103 // external exception handler using cyg_hal_deliver_exception() | |
| 0 | 104 |
| 2 | 105 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD |
| 106 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \ | |
| 107 CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL | |
| 108 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \ | |
| 109 CYGNUM_HAL_VECTOR_TLB_STORE_REFILL | |
| 110 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ | |
| 111 CYGNUM_HAL_VECTOR_LOAD_ADDRESS | |
| 112 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \ | |
| 113 CYGNUM_HAL_VECTOR_STORE_ADDRESS | |
| 114 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE | |
| 115 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE | |
| 116 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL | |
| 117 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT | |
| 118 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ | |
| 119 CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION | |
| 120 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR | |
| 121 #define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW | |
| 122 | |
| 123 // Min/Max exception numbers and how many there are | |
| 124 #define CYGNUM_HAL_EXCEPTION_MIN 1 | |
| 125 #define CYGNUM_HAL_EXCEPTION_MAX 13 | |
| 126 #define CYGNUM_HAL_EXCEPTION_COUNT 13 | |
| 0 | 127 |
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128 |
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129 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 130 |
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131 // the default for all MIPS variants is to use the 6 bits |
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132 // in the cause register. |
| 0 | 133 |
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134 #define CYGNUM_HAL_INTERRUPT_0 0 |
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135 #define CYGNUM_HAL_INTERRUPT_1 1 |
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136 #define CYGNUM_HAL_INTERRUPT_2 2 |
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137 #define CYGNUM_HAL_INTERRUPT_3 3 |
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138 #define CYGNUM_HAL_INTERRUPT_4 4 |
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139 #define CYGNUM_HAL_INTERRUPT_5 5 |
| 0 | 140 |
| 2 | 141 // Min/Max ISR numbers and how many there are |
| 142 #define CYGNUM_HAL_ISR_MIN 0 | |
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143 #define CYGNUM_HAL_ISR_MAX 5 |
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144 #define CYGNUM_HAL_ISR_COUNT 6 |
| 0 | 145 |
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146 // The vector used by the Real time clock. The default here is to use |
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147 // interrupt 5, which is connected to the counter/comparator registers |
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148 // in many MIPS variants. |
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149 |
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150 #ifndef CYGNUM_HAL_INTERRUPT_RTC |
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151 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5 |
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152 #endif |
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153 |
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154 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 155 |
| 156 #endif | |
| 157 | |
| 2 | 158 //-------------------------------------------------------------------------- |
| 0 | 159 // Static data used by HAL |
| 160 | |
| 161 // ISR tables | |
| 2 | 162 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
| 163 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; | |
| 164 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; | |
| 0 | 165 |
| 166 // VSR table | |
| 2 | 167 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; |
| 0 | 168 |
| 2 | 169 //-------------------------------------------------------------------------- |
| 0 | 170 // Default ISR |
| 171 | |
| 172 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); | |
| 173 | |
| 2 | 174 //-------------------------------------------------------------------------- |
| 0 | 175 // Interrupt state storage |
| 176 | |
| 177 typedef cyg_uint32 CYG_INTERRUPT_STATE; | |
| 178 | |
| 2 | 179 //-------------------------------------------------------------------------- |
| 0 | 180 // Interrupt control macros |
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181 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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182 // that might otherwise cause following code to run in the wrong state or |
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183 // cause a resource conflict. |
| 0 | 184 |
| 185 #define HAL_DISABLE_INTERRUPTS(_old_) \ | |
| 186 { \ | |
| 187 asm volatile ( \ | |
| 188 "mfc0 $8,$12; nop;" \ | |
| 189 "move %0,$8;" \ | |
| 190 "and $8,$8,0XFFFFFFFE;" \ | |
| 191 "mtc0 $8,$12;" \ | |
| 192 "nop; nop; nop;" \ | |
| 193 "and %0,%0,0X1;" \ | |
| 194 : "=r"(_old_) \ | |
| 195 : \ | |
| 196 : "$8" \ | |
| 197 ); \ | |
| 198 } | |
| 199 | |
| 200 #define HAL_ENABLE_INTERRUPTS() \ | |
| 201 { \ | |
| 202 asm volatile ( \ | |
| 203 "mfc0 $8,$12; nop;" \ | |
| 204 "or $8,$8,1;" \ | |
| 205 "mtc0 $8,$12;" \ | |
| 206 "nop; nop; nop;" \ | |
| 207 : \ | |
| 208 : \ | |
| 209 : "$8" \ | |
| 210 ); \ | |
| 211 } | |
| 212 | |
| 213 #define HAL_RESTORE_INTERRUPTS(_old_) \ | |
| 214 { \ | |
| 215 asm volatile ( \ | |
| 216 "mfc0 $8,$12; nop;" \ | |
| 217 "and %0,%0,0x1;" \ | |
| 218 "or $8,$8,%0;" \ | |
| 219 "mtc0 $8,$12;" \ | |
| 220 "nop; nop; nop;" \ | |
| 221 : \ | |
| 222 : "r"(_old_) \ | |
| 223 : "$8" \ | |
| 224 ); \ | |
| 225 } | |
| 226 | |
| 227 #define HAL_QUERY_INTERRUPTS( _state_ ) \ | |
| 228 { \ | |
| 229 asm volatile ( \ | |
| 230 "mfc0 %0,$12; nop;" \ | |
| 231 "and %0,%0,0x1;" \ | |
| 232 : "=r"(_state_) \ | |
| 233 : \ | |
| 234 : "$8" \ | |
| 235 ); \ | |
| 236 } | |
| 237 | |
| 2 | 238 //-------------------------------------------------------------------------- |
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239 // Routine to execute DSRs using separate interrupt stack |
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240 |
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241 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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242 externC void hal_interrupt_stack_call_pending_DSRs(void); |
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243 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ |
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244 hal_interrupt_stack_call_pending_DSRs() |
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245 |
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246 // these are offered solely for stack usage testing |
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247 // if they are not defined, then there is no interrupt stack. |
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248 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base |
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249 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack |
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250 // use them to declare these extern however you want: |
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251 // extern char HAL_INTERRUPT_STACK_BASE[]; |
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252 // extern char HAL_INTERRUPT_STACK_TOP[]; |
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253 // is recommended |
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254 #endif |
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255 |
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256 //-------------------------------------------------------------------------- |
| 0 | 257 // Vector translation. |
| 258 // For chained interrupts we only have a single vector though which all | |
| 259 // are passed. For unchained interrupts we have a vector per interrupt. | |
| 260 | |
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261 #ifndef HAL_TRANSLATE_VECTOR |
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262 |
| 0 | 263 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
| 264 | |
| 265 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 | |
| 266 | |
| 267 #else | |
| 268 | |
| 269 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) | |
| 270 | |
| 271 #endif | |
| 272 | |
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273 #endif |
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274 |
| 2 | 275 //-------------------------------------------------------------------------- |
| 0 | 276 // Interrupt and VSR attachment macros |
| 277 | |
| 2 | 278 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
| 279 CYG_MACRO_START \ | |
| 280 cyg_uint32 _index_; \ | |
| 281 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ | |
| 282 \ | |
| 283 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ | |
| 284 (_state_) = 0; \ | |
| 285 else \ | |
| 286 (_state_) = 1; \ | |
| 287 CYG_MACRO_END | |
| 288 | |
| 289 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ | |
| 290 { \ | |
| 291 cyg_uint32 _index_; \ | |
| 292 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 293 \ | |
| 294 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ | |
| 295 { \ | |
| 296 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ | |
| 297 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ | |
| 298 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ | |
| 299 } \ | |
| 0 | 300 } |
| 301 | |
| 302 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ | |
| 303 { \ | |
| 304 cyg_uint32 _index_; \ | |
| 305 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 306 \ | |
| 307 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ | |
| 308 { \ | |
| 309 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ | |
| 310 hal_interrupt_data[_index_] = 0; \ | |
| 311 hal_interrupt_objects[_index_] = 0; \ | |
| 312 } \ | |
| 313 } | |
| 314 | |
| 315 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ | |
| 316 *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; | |
| 317 | |
| 318 | |
| 2 | 319 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ |
| 320 if( _poldvsr_ != NULL) \ | |
| 321 *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ | |
| 322 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ | |
| 323 CYG_MACRO_END | |
| 324 | |
| 325 // This is an ugly name, but what it means is: grab the VSR back to eCos | |
| 326 // internal handling, or if you like, the default handler. But if | |
| 327 // cooperating with GDB and CygMon, the default behaviour is to pass most | |
| 328 // exceptions to CygMon. This macro undoes that so that eCos handles the | |
| 329 // exception. So use it with care. | |
| 0 | 330 |
| 2 | 331 externC void __default_exception_vsr(void); |
| 332 externC void __default_interrupt_vsr(void); | |
| 333 | |
| 334 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ | |
| 335 HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ | |
| 336 ? (CYG_ADDRESS)__default_interrupt_vsr \ | |
| 337 : (CYG_ADDRESS)__default_exception_vsr, \ | |
| 338 _poldvsr_ ); \ | |
| 339 CYG_MACRO_END | |
| 340 | |
| 341 //-------------------------------------------------------------------------- | |
| 0 | 342 // Interrupt controller access |
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343 // The default code here simply uses the fields present in the CP0 status |
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344 // and cause registers to implement this functionality. |
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345 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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346 // that might otherwise cause following code to run in the wrong state or |
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347 // cause a resource conflict. |
| 0 | 348 |
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349 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 350 |
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351 #define HAL_INTERRUPT_MASK( _vector_ ) \ |
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352 CYG_MACRO_START \ |
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353 asm volatile ( \ |
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354 "mfc0 $3,$12\n" \ |
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355 "la $2,0x00000400\n" \ |
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356 "sllv $2,$2,%0\n" \ |
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357 "nor $2,$2,$0\n" \ |
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358 "and $3,$3,$2\n" \ |
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359 "mtc0 $3,$12\n" \ |
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360 "nop; nop; nop\n" \ |
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361 : \ |
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362 : "r"(_vector_) \ |
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363 : "$2", "$3" \ |
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364 ); \ |
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365 CYG_MACRO_END |
| 0 | 366 |
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367 #define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
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368 CYG_MACRO_START \ |
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369 asm volatile ( \ |
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370 "mfc0 $3,$12\n" \ |
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371 "la $2,0x00000400\n" \ |
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372 "sllv $2,$2,%0\n" \ |
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373 "or $3,$3,$2\n" \ |
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374 "mtc0 $3,$12\n" \ |
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375 "nop; nop; nop\n" \ |
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376 : \ |
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377 : "r"(_vector_) \ |
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378 : "$2", "$3" \ |
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379 ); \ |
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380 CYG_MACRO_END |
| 0 | 381 |
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382 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
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383 CYG_MACRO_START \ |
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384 asm volatile ( \ |
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385 "mfc0 $3,$13\n" \ |
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386 "la $2,0x00000400\n" \ |
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387 "sllv $2,$2,%0\n" \ |
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388 "nor $2,$2,$0\n" \ |
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389 "and $3,$3,$2\n" \ |
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390 "mtc0 $3,$13\n" \ |
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391 "nop; nop; nop\n" \ |
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392 : \ |
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393 : "r"(_vector_) \ |
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394 : "$2", "$3" \ |
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395 ); \ |
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396 CYG_MACRO_END |
| 0 | 397 |
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398 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) |
| 0 | 399 |
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400 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) |
| 0 | 401 |
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402 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 403 |
| 404 #endif | |
| 405 | |
| 2 | 406 //-------------------------------------------------------------------------- |
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407 // Clock control. |
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408 // This code uses the count and compare registers that are present in many |
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409 // MIPS variants. |
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410 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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411 // that might otherwise cause following code to run in the wrong state or |
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412 // cause a resource conflict. |
| 0 | 413 |
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414 #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
| 2 | 415 |
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416 #define HAL_CLOCK_INITIALIZE( _period_ ) \ |
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417 CYG_MACRO_START \ |
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418 asm volatile ( \ |
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419 "mtc0 $0,$9\n" \ |
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420 "nop; nop; nop\n" \ |
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421 "mtc0 %0,$11\n" \ |
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422 "nop; nop; nop\n" \ |
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423 : \ |
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424 : "r"(_period_) \ |
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425 ); \ |
| 2 | 426 CYG_MACRO_END |
| 427 | |
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428 #define HAL_CLOCK_RESET( _vector_, _period_ ) \ |
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429 CYG_MACRO_START \ |
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430 asm volatile ( \ |
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431 "mtc0 $0,$9\n" \ |
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432 "nop; nop; nop\n" \ |
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433 "mtc0 %0,$11\n" \ |
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434 "nop; nop; nop\n" \ |
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435 : \ |
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436 : "r"(_period_) \ |
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437 ); \ |
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438 CYG_MACRO_END |
| 2 | 439 |
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440 #define HAL_CLOCK_READ( _pvalue_ ) \ |
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441 CYG_MACRO_START \ |
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442 register CYG_WORD32 result; \ |
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443 asm volatile ( \ |
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444 "mfc0 %0,$9\n" \ |
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445 : "=r"(result) \ |
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446 ); \ |
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447 *(_pvalue_) = result; \ |
| 2 | 448 CYG_MACRO_END |
| 449 | |
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450 #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
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451 |
| 2 | 452 #endif |
| 453 | |
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454 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ |
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455 !defined(HAL_CLOCK_LATENCY) |
| 2 | 456 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) |
| 457 #endif | |
| 0 | 458 |
| 2 | 459 //-------------------------------------------------------------------------- |
| 0 | 460 #endif // ifndef CYGONCE_HAL_HAL_INTR_H |
| 461 // End of hal_intr.h |
