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annotate packages/hal/arm/sa11x0/brutus/current/src/brutus_misc.c @ 108:ff3f181b64bd ecos-sw-2000-07-04

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Merge from eCos master repository on 2000-07-04-20:42:44-BST
author jlarmour
date Tue, 04 Jul 2000 20:17:21 +0000
parents
children 6b5f480c6929
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1 //==========================================================================
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2 //
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3 // brutus_misc.c
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4 //
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5 // HAL misc board support code for StrongARM SA1110/Brutus
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: hmt
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36 // Travis C. Furrer <furrer@mit.edu>
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37 // Date: 2000-05-21
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38 // Purpose: HAL board support
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39 // Description: Implementations of HAL board interfaces
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //========================================================================*/
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44
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45 #include <pkgconf/hal.h>
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46 #include <pkgconf/system.h>
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47 #include CYGBLD_HAL_PLATFORM_H
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48
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49 #include <cyg/infra/cyg_type.h> // base types
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50 #include <cyg/infra/cyg_trac.h> // tracing macros
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51 #include <cyg/infra/cyg_ass.h> // assertion macros
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52
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53 #include <cyg/hal/hal_io.h> // IO macros
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54 #include <cyg/hal/hal_arch.h> // Register state info
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55 #include <cyg/hal/hal_diag.h>
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56 #include <cyg/hal/hal_intr.h> // Interrupt names
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57 #include <cyg/hal/hal_cache.h>
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58 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
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59 #include <cyg/hal/brutus.h> // Platform specifics
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60
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61 #include <cyg/infra/diag.h> // diag_printf
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62
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63 // -------------------------------------------------------------------------
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64 // MMU initialization:
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65 //
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66 // These structures are laid down in memory to define the translation
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67 // table.
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68 //
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69
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70 /*
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71 * SA-1100 Translation Table Base Bit Masks */
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72 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
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73
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74 /*
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75 * SA-1100 Domain Access Control Bit Masks
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76 */
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77 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
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78 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
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79 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
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80
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81 struct ARM_MMU_FIRST_LEVEL_FAULT {
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82 int id : 2;
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83 int sbz : 30;
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84 };
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85 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
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86
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87 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
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88 int id : 2;
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89 int imp : 2;
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90 int domain : 4;
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91 int sbz : 1;
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92 int base_address : 23;
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93 };
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94 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
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95
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96 struct ARM_MMU_FIRST_LEVEL_SECTION {
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97 int id : 2;
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98 int b : 1;
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99 int c : 1;
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100 int imp : 1;
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101 int domain : 4;
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102 int sbz0 : 1;
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103 int ap : 2;
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104 int sbz1 : 8;
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105 int base_address : 12;
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106 };
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107 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
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108
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109 struct ARM_MMU_FIRST_LEVEL_RESERVED {
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110 int id : 2;
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111 int sbz : 30;
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112 };
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113 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
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114
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115 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
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116 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
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117
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118 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
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119
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120 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
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121 cacheable, bufferable, perm) \
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122 CYG_MACRO_START \
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123 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
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124 \
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125 desc.word = 0; \
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126 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
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127 desc.section.domain = 0; \
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128 desc.section.c = (cacheable); \
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129 desc.section.b = (bufferable); \
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130 desc.section.ap = (perm); \
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131 desc.section.base_address = (actual_base); \
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132 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
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133 = desc.word; \
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134 CYG_MACRO_END
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135
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136 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
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137 { int i; int j = abase; int k = vbase; \
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138 for (i = size; i > 0 ; i--,j++,k++) \
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139 { \
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140 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
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141 } \
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142 }
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143
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144 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
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145 unsigned long word;
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146 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
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147 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
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148 struct ARM_MMU_FIRST_LEVEL_SECTION section;
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149 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
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150 };
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151
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152 #define ARM_UNCACHEABLE 0
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153 #define ARM_CACHEABLE 1
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154 #define ARM_UNBUFFERABLE 0
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155 #define ARM_BUFFERABLE 1
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156
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157 #define ARM_ACCESS_PERM_NONE_NONE 0
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158 #define ARM_ACCESS_PERM_RO_NONE 0
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159 #define ARM_ACCESS_PERM_RO_RO 0
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160 #define ARM_ACCESS_PERM_RW_NONE 1
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161 #define ARM_ACCESS_PERM_RW_RO 2
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162 #define ARM_ACCESS_PERM_RW_RW 3
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163
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164 void
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165 hal_mmu_init(void)
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166 {
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167 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
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168 unsigned long i;
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169
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170 /*
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171 * Set the TTB register
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172 */
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173 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
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174
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175 /*
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176 * Set the Domain Access Control Register
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177 */
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178 i = ARM_ACCESS_TYPE_MANAGER(0) |
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179 ARM_ACCESS_TYPE_NO_ACCESS(1) |
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180 ARM_ACCESS_TYPE_NO_ACCESS(2) |
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181 ARM_ACCESS_TYPE_NO_ACCESS(3) |
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182 ARM_ACCESS_TYPE_NO_ACCESS(4) |
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183 ARM_ACCESS_TYPE_NO_ACCESS(5) |
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184 ARM_ACCESS_TYPE_NO_ACCESS(6) |
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185 ARM_ACCESS_TYPE_NO_ACCESS(7) |
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186 ARM_ACCESS_TYPE_NO_ACCESS(8) |
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187 ARM_ACCESS_TYPE_NO_ACCESS(9) |
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188 ARM_ACCESS_TYPE_NO_ACCESS(10) |
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189 ARM_ACCESS_TYPE_NO_ACCESS(11) |
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190 ARM_ACCESS_TYPE_NO_ACCESS(12) |
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191 ARM_ACCESS_TYPE_NO_ACCESS(13) |
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192 ARM_ACCESS_TYPE_NO_ACCESS(14) |
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193 ARM_ACCESS_TYPE_NO_ACCESS(15);
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194 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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195
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196 /*
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197 * First clear all TT entries - ie Set them to Faulting
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198 */
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199 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
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200
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201 /* Actual Virtual Size Attributes Function */
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202 /* Base Base MB cached? buffered? access permissions */
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203 /* xxx00000 xxx00000 */
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204 X_ARM_MMU_SECTION(0x000, 0x400, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
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205 X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
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206 X_ARM_MMU_SECTION(0x100, 0x100, 1, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static RAM - 512K */
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207 X_ARM_MMU_SECTION(0x180, 0x180, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static select 3 */
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208 X_ARM_MMU_SECTION(0x200, 0x200, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket 0 */
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209 X_ARM_MMU_SECTION(0x300, 0x300, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets 1 */
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210 X_ARM_MMU_SECTION(0x800, 0x800, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
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211 X_ARM_MMU_SECTION(0xC00, 0x000, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
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212 X_ARM_MMU_SECTION(0xC80, 0x004, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 1 */
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213 X_ARM_MMU_SECTION(0xD00, 0x008, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 2 */
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214 X_ARM_MMU_SECTION(0xD80, 0x00C, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 3 */
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215 X_ARM_MMU_SECTION(0xC00, 0xC00, 256, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Banks - raw access */
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216 X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
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217
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218 }
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219
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220 //
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221 // Platform specific initialization
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222 //
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223
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224 void
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225 plf_hardware_init(void)
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226 {
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227 }