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annotate packages/hal/mips/ref4955/current/include/plf_intr.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
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1 #ifndef CYGONCE_HAL_PLF_INTR_H
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2 #define CYGONCE_HAL_PLF_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // plf_intr.h
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7 //
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8 // REF4955 Interrupt and clock support
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
208
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
208
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
208
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): jskov
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46 // Contributors: jskov, nickg
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47 // Date: 2000-05-09
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48 // Purpose: Define Interrupt support
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // interrupts and the clock for the REF4955 board.
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51 //
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52 // Usage:
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53 // #include <cyg/hal/plf_intr.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //==========================================================================
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60
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61 #include <pkgconf/hal.h>
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62
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63 #include <cyg/infra/cyg_type.h>
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64
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65 //--------------------------------------------------------------------------
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66 // Interrupt vectors.
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67
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68 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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69
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70
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71 // The first 6 correspond to the interrupt lines in the status/cause regs
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72 #define CYGNUM_HAL_INTERRUPT_V320USC_INT0 0
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73 #define CYGNUM_HAL_INTERRUPT_V320USC_INT1 1
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74 #define CYGNUM_HAL_INTERRUPT_EXT 2
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75 #define CYGNUM_HAL_INTERRUPT_LAN 3
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76 #define CYGNUM_HAL_INTERRUPT_IO 4
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77 #define CYGNUM_HAL_INTERRUPT_COMPARE 5
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78
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79
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80 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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81
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82 // This overlaps with LB_MBI below but it doesn't matter. It's only used
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83 // by the HAL to access the special chaining entry in the ISR tables.
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84 // All other attempted access to the ISR table will be redirected to this
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85 // entry (curtsey of HAL_TRANSLATE_VECTOR). The other vector definitions
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86 // are still valid, but only for enable/disable/config etc. (i.e., in
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87 // chaining mode they have associated entries in the ISR tables).
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88 #define CYGNUM_HAL_INTERRUPT_CHAINING 6
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89
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90 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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91 (_index_) = CYGNUM_HAL_INTERRUPT_CHAINING
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92
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93 #endif
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94
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95
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96 // The next 32 correspond to the interrupt lines in the V320USC's interrupt
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97 // controller. These are decoded from the controller when an interrupt
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98 // enters via CYGNUM_HAL_INTERRUPT_V320USC_INT0.
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99 #define CYGNUM_HAL_INTERRUPT_INTC_V320USC_base 6
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100 #define CYGNUM_HAL_INTERRUPT_LB_MBI 6
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101 #define CYGNUM_HAL_INTERRUPT_PCI_MBI 7
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102 #define CYGNUM_HAL_INTERRUPT_RESERVED_2 8
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103 #define CYGNUM_HAL_INTERRUPT_I2O_OP_NE 9
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104 #define CYGNUM_HAL_INTERRUPT_I2O_IF_NF 10
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105 #define CYGNUM_HAL_INTERRUPT_I2O_IP_NE 11
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106 #define CYGNUM_HAL_INTERRUPT_I2O_OP_NF 12
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107 #define CYGNUM_HAL_INTERRUPT_I2O_OF_NE 13
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108 #define CYGNUM_HAL_INTERRUPT_RESERVED_8 14
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109 #define CYGNUM_HAL_INTERRUPT_RESERVED_9 15
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110 #define CYGNUM_HAL_INTERRUPT_RESERVED_10 16
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111 #define CYGNUM_HAL_INTERRUPT_RESERVED_11 17
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112 #define CYGNUM_HAL_INTERRUPT_TIMER0 18
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113 #define CYGNUM_HAL_INTERRUPT_TIMER1 19
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114 #define CYGNUM_HAL_INTERRUPT_RESERVED_14 20
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115 #define CYGNUM_HAL_INTERRUPT_ENUM 21
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116 #define CYGNUM_HAL_INTERRUPT_DMA0 22
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117 #define CYGNUM_HAL_INTERRUPT_DMA1 23
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118 #define CYGNUM_HAL_INTERRUPT_RESERVED_18 24
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119 #define CYGNUM_HAL_INTERRUPT_RESERVED_19 25
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120 #define CYGNUM_HAL_INTERRUPT_PWR_STATE 26
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121 #define CYGNUM_HAL_INTERRUPT_HBI 27
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122 #define CYGNUM_HAL_INTERRUPT_WDI 28
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123 #define CYGNUM_HAL_INTERRUPT_BWI 29
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124 #define CYGNUM_HAL_INTERRUPT_PSLAVE_PI 30
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125 #define CYGNUM_HAL_INTERRUPT_PMASTER_PI 31
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126 #define CYGNUM_HAL_INTERRUPT_PCI_T_ABORT 32
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127 #define CYGNUM_HAL_INTERRUPT_PCI_M_ABORT 33
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128 #define CYGNUM_HAL_INTERRUPT_DRAM_PI 34
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129 #define CYGNUM_HAL_INTERRUPT_RESERVED_29 35
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130 #define CYGNUM_HAL_INTERRUPT_DI0 36
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131 #define CYGNUM_HAL_INTERRUPT_DI1 37
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132
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133 // The next 6 correspond to the interrupt lines specific to the PCI
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134 // connector (decoded from CYGNUM_HAL_INTERRUPT_V320USC_INT1)
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135 #define CYGNUM_HAL_INTERRUPT_INTC_PCI_base 38
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136 #define CYGNUM_HAL_INTERRUPT_SERR 38
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137 #define CYGNUM_HAL_INTERRUPT_PERR 39
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138 #define CYGNUM_HAL_INTERRUPT_INTD 40
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139 #define CYGNUM_HAL_INTERRUPT_INTC 41
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140 #define CYGNUM_HAL_INTERRUPT_INTB 42
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141 #define CYGNUM_HAL_INTERRUPT_INTA 43
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142
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143 // The next 5 correspond to the interrupt lines specific to the REF4955
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144 // board (decoded from CYGNUM_HAL_INTERRUPT_IO)
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145 #define CYGNUM_HAL_INTERRUPT_INTC_IO_base 44
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146 #define CYGNUM_HAL_INTERRUPT_SOFTWARE 44
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147 #define CYGNUM_HAL_INTERRUPT_INT_SWITCH 45
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148 #define CYGNUM_HAL_INTERRUPT_PARALLEL 46
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149 #define CYGNUM_HAL_INTERRUPT_DEBUG_UART 47
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150 #define CYGNUM_HAL_INTERRUPT_USER_UART 48
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151
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152
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153 // Min/Max ISR numbers and how many there are
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154 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_V320USC_INT0
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155 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_USER_UART
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156 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
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157
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158 // The vector used by the Real time clock
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159 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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160
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161 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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162
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163 #endif
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164
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165 //--------------------------------------------------------------------------
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166 // Interrupt controler information
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167
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168 // V320USC
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169 #define CYGARC_REG_INT_STAT 0xb80000ec
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170
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171 #define CYGARC_REG_INT_CFG0 0xb80000e0
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172 #define CYGARC_REG_INT_CFG1 0xb80000e4
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173 #define CYGARC_REG_INT_CFG2 0xb80000e8
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174 #define CYGARC_REG_INT_CFG3 0xb8000158
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175
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176 #define CYGARC_REG_INT_CFG_INT0 0x00000100
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177 #define CYGARC_REG_INT_CFG_INT1 0x00000200
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178 #define CYGARC_REG_INT_CFG_INT2 0x00000400
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179 #define CYGARC_REG_INT_CFG_INT3 0x00000800
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180
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181
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182 // FPGA
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183 #define CYGARC_REG_PCI_STAT 0xb5300000
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184 #define CYGARC_REG_PCI_MASK 0xb5300030
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185
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186 #define CYGARC_REG_IO_STAT 0xb5300010
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187 #define CYGARC_REG_IO_MASK 0xb5300040
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188
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189
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190 #define HAL_INTERRUPT_MASK( _vector_ ) \
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191 CYG_MACRO_START \
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192 if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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193 { \
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194 asm volatile ( \
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195 "mfc0 $3,$12\n" \
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196 "la $2,0x00000400\n" \
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197 "sllv $2,$2,%0\n" \
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198 "nor $2,$2,$0\n" \
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199 "and $3,$3,$2\n" \
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200 "mtc0 $3,$12\n" \
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201 "nop; nop; nop\n" \
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202 : \
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203 : "r"(_vector_) \
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204 : "$2", "$3" \
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205 ); \
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206 } \
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207 else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
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208 { \
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209 cyg_uint8 _mask_; \
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210 cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
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211 HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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212 _mask_ &= ~(1<<_shift_); \
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213 HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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214 } \
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215 else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
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216 { \
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217 cyg_uint8 _mask_; \
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218 cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
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219 HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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220 _mask_ &= ~(1<<_shift_); \
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221 HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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222 } else { /* V320USC */ \
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223 cyg_uint32 _mask_; \
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224 cyg_uint32 _shift_ = \
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225 (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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226 HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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227 _mask_ &= !(1<<_shift_); \
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228 HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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229 } \
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230 CYG_MACRO_END
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231
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232 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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233 CYG_MACRO_START \
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234 if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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235 { \
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236 asm volatile ( \
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237 "mfc0 $3,$12\n" \
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238 "la $2,0x00000400\n" \
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239 "sllv $2,$2,%0\n" \
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240 "or $3,$3,$2\n" \
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241 "mtc0 $3,$12\n" \
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242 "nop; nop; nop\n" \
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243 : \
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244 : "r"(_vector_) \
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245 : "$2", "$3" \
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246 ); \
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247 } \
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248 else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
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249 { \
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250 cyg_uint8 _mask_; \
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251 cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
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252 HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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253 _mask_ |= (1<<_shift_); \
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254 HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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255 } \
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256 else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
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257 { \
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258 cyg_uint8 _mask_; \
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259 cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
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260 HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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261 _mask_ |= (1<<_shift_); \
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262 HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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263 } else { /* V320USC */ \
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264 cyg_uint32 _mask_; \
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265 cyg_uint32 _shift_ = \
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266 (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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267 HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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268 _mask_ |= (1<<_shift_); \
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269 HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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270 } \
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271 CYG_MACRO_END
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272
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273 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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274 CYG_MACRO_START \
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275 cyg_uint32 _srvector_ = _vector_; \
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276 if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) { \
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277 _srvector_ = CYGNUM_HAL_INTERRUPT_IO; \
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278 } else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) { \
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279 _srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT1; \
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280 } else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_V320USC_base) { \
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281 cyg_uint32 _mask_; \
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282 cyg_uint32 _shift_ = \
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283 (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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284 _mask_ = (1<<_shift_); \
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285 HAL_WRITE_UINT32(CYGARC_REG_INT_STAT, _mask_ ); \
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286 _srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT0; \
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287 } \
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288 asm volatile ( \
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289 "mfc0 $3,$13\n" \
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290 "la $2,0x00000400\n" \
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291 "sllv $2,$2,%0\n" \
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292 "nor $2,$2,$0\n" \
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293 "and $3,$3,$2\n" \
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294 "mtc0 $3,$13\n" \
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295 "nop; nop; nop\n" \
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296 : \
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297 : "r"(_srvector_) \
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298 : "$2", "$3" \
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299 ); \
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300 CYG_MACRO_END
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301
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302 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
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303
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304 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
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305
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306 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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307
151
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308
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309 //----------------------------------------------------------------------------
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310 // Reset.
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311 #define CYGARC_REG_BOARD_RESET 0xb5400000
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312
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313 #define HAL_PLATFORM_RESET() HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,0)
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314
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315 #define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
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316
134
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317 //--------------------------------------------------------------------------
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318 #endif // ifndef CYGONCE_HAL_PLF_INTR_H
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319 // End of plf_intr.h