Mercurial > ecos
changeset 134:d2f49caf9e38 ecos-sw-2000-11-03
Merge from eCos master repository on 2000-11-03-09:00:49-GMT
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,7 +1,20 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * ecos.db: Added cq7750 target and SH3/SH4 variant packages. Moved + EDK7708 package. + +2000-10-25 Drew Moseley <dmoseley@redhat.com> + + * ecos.db: Add support for SA1100 Multimedia + 2000-10-20 Gary Thomas <gthomas@redhat.com> * ecos.db: Add FLASH drivers for PowerPC/MBX. +2000-10-20 Gary Thomas <gthomas@redhat.com> + + * ecos.db: Include FLASH drivers for all Cirrus Logic targets. + 2000-09-15 Jesper Skov <jskov@redhat.com> * ecos.db: Made PID use generic 16x5x driver. @@ -9,6 +22,7 @@ 2000-09-15 Jesper Skov <jskov@redhat.c 2000-09-14 Jesper Skov <jskov@redhat.com> * ecos.db: Added generic 16x5x driver package. + * ecos.db: Use generic 16x5x driver for REF4955. 2000-09-06 Jesper Skov <jskov@redhat.com> @@ -98,6 +112,10 @@ 2000-06-22 Jesper Skov <jskov@redhat.c * ecos.db: Add CYGPKG_SNMPLIB and CYGPKG_SNMPAGENT. +2000-06-06 Jesper Skov <jskov@redhat.com> + + * ecos.db: Removed REF4955 watchdog. Isn't supported on the board. + 2000-06-05 John Dallaway <jld@redhat.com> * ecos.db: @@ -128,10 +146,19 @@ 2000-05-25 John Dallaway <jld@redhat.c * ecos.db: Tidy V850-related display strings. +2000-05-25 Jesper Skov <jskov@redhat.com> + + * ecos.db: Added REF4955 serial driver package. + Added wallclock driver package. + 2000-05-16 Nick Garnett <nickg@cygnus.co.uk> * ecos.db: Fixed naming bug in CYGPKG_LIBC_SETJMP entry. +2000-05-10 Jesper Skov <jskov@redhat.com> + + * ecos.db: Added tx49 related packages. + 2000-04-26 Jesper Skov <jskov@redhat.com> * ecos.db: ceb_v850 - include serial driver.
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,11 @@ +* Added a port to the Toshiba MIPS TX49 chip, with the REF4955 reference + platform. This includes serial device driver and wallclock device driver + support. +* PowerPC 40x variant support added. +* Added SH4 support. Split SH architecture HAL into variants in the process. +* Added SH4/CQ7750 platform support [still untested] +* Port to Intel SA1100 Multimedia evalulation board added, including FLASH + driver and RedBoot support * FLASH driver added for PowerPC/MBX * sigsetjmp() and siglongjmp() added * A choice of getcwd() implementations have been added
--- a/packages/compat/posix/current/ChangeLog +++ b/packages/compat/posix/current/ChangeLog @@ -1,3 +1,25 @@ +2000-11-02 Jonathan Larmour <jlarmour@redhat.com> + + * src/signal.cxx (sigtimedwait): return signal number on success, + not 0 + (SIGNAL_RETURN_VALUE): New macro for returning from functions with + valid non-zero returns + (sigwaitinfo): Pass on sigtimedwait result with SIGNAL_RETURN_VALUE + macro as it may return the signal number. + +2000-11-01 Jonathan Larmour <jlarmour@redhat.com> + + * src/signal.cxx (sigtimedwait): Check for SIGALRMs as a special + case when looping as it won't have been set pending if it was + masked. + (check_sigalarm): New function extracted from the posix signal ASR + (sigalrm_action): Unconditionally wake up threads waiting in sigwait + so that they can check for pending SIGALRMs even if they were + masked. + (cyg_deliver_signals): Handle SIG_DFL signals properly, and check + for bad signal handlers. + (cyg_posix_signal_start): Initialize default signal actions to SIG_DFL + 2000-10-27 Jesper Skov <jskov@redhat.com> * tests/signal2.c (cause_illegal_access): Don't loop forever.
--- a/packages/compat/posix/current/src/signal.cxx +++ b/packages/compat/posix/current/src/signal.cxx @@ -47,6 +47,7 @@ #include <pkgconf/hal.h> #include <pkgconf/kernel.h> #include <pkgconf/posix.h> +#include <pkgconf/isoinfra.h> #include <cyg/kernel/ktypes.h> // base kernel types #include <cyg/infra/cyg_trac.h> // tracing macros @@ -80,6 +81,13 @@ CYG_MACRO_START return __retval; \ CYG_MACRO_END +// Similarly for functions that have valid non-zero returns +#define SIGNAL_RETURN_VALUE(val) \ +CYG_MACRO_START \ + CYG_REPORT_RETVAL( val ); \ + return val; \ +CYG_MACRO_END + // Range check on a signal value. #define SIGNAL_VALID(_sig_) (((_sig_) > 0) && ((_sig_) < ((int)sizeof(sigset_t)*8))) @@ -149,6 +157,12 @@ externC void cyg_posix_signal_start() siginfo[i].next = siginfo_next; siginfo_next = &siginfo[i]; } + + // initialize all signal actions to SIG_DFL + for ( unsigned int i=0; i<(sizeof(sigstate)/sizeof(signal_state)); i++ ) + { + sigstate[i].sa.sa_handler = SIG_DFL; + } // Clear the pending signal set sigemptyset( &sig_pending ); @@ -283,8 +297,7 @@ cyg_bool cyg_deliver_signals() signal_state *ss = &sigstate[signo]; sigset_t sigbit = 1L<<signo; - if( ss->sa.sa_handler != SIG_DFL && - ss->sa.sa_handler != SIG_IGN ) + if( ss->sa.sa_handler != SIG_IGN ) { sigset_t oldmask = self->sigmask; siginfo_t lsi; @@ -348,12 +361,23 @@ cyg_bool cyg_deliver_signals() if( ss->sa.sa_flags & SA_SIGINFO ) { // A sigaction delivery - + CYG_CHECK_FUNC_PTR( ss->sa.sa_sigaction, + "Bad sa_sigaction signal handler" ); ss->sa.sa_sigaction( signo, &lsi, NULL ); } + if ( ss->sa.sa_handler == SIG_DFL ) + { + // FIXME: should do something better here +#if CYGINT_ISO_EXIT + _exit( -signo ); +#endif + CYG_FAIL("Unhandled POSIX signal"); + } else { // This is a standard signal delivery. + CYG_CHECK_FUNC_PTR( ss->sa.sa_handler, + "Bad sa_handler signal handler" ); ss->sa.sa_handler( signo ); } @@ -386,14 +410,18 @@ static void sigalrm_action( Cyg_Alarm *a sigalrm_pending = true; sigemptyset( &mask ); sigaddset( &mask, SIGALRM ); + // Wake up any threads in sigsuspend() and sigwait() in case they + // are waiting for an alarm, and would have SIGALRM masked + signal_sigwait.broadcast(); + cyg_posix_pthread_release_thread( &mask ); } // ------------------------------------------------------------------------- -// signal ASR function. This is called from the general POSIX ASR to -// deal with any signal related issues. +// Check for SIGALRMs. This is called from the ASR and sigtimedwait() +// as alarms need to be handled as a special case. -externC void cyg_posix_signal_asr(pthread_info *self) +static __inline__ void check_sigalarm(void) { // If there is a pending SIGALRM, generate it if( sigalrm_pending ) @@ -409,12 +437,20 @@ externC void cyg_posix_signal_asr(pthrea // generate the signal cyg_sigqueue( &sev, SI_USER ); } +} + +// ------------------------------------------------------------------------- +// signal ASR function. This is called from the general POSIX ASR to +// deal with any signal related issues. + +externC void cyg_posix_signal_asr(pthread_info *self) +{ + check_sigalarm(); // Now call cyg_deliver_signals() to see if we can // handle any signals now. cyg_deliver_signals(); - } //========================================================================== @@ -560,7 +596,7 @@ externC int sigaction (int sig, const s // ------------------------------------------------------------------------- // Queue signal to process with value. -externC int sigqueue (pid_t pid, int sig, const union sigval value) +externC int sigqueue (pid_t pid, int sig, const union sigval value) { SIGNAL_ENTRY(); @@ -715,7 +751,7 @@ externC int sigwaitinfo (const sigset_t int ret = sigtimedwait( set, info, NULL ); - SIGNAL_RETURN(ret); + SIGNAL_RETURN_VALUE(ret); } // ------------------------------------------------------------------------- @@ -757,6 +793,10 @@ externC int sigtimedwait (const sigset_ } } else signal_sigwait.wait(); + + // Special case check for SIGALRM since the fact SIGALRM is masked + // would have prevented it being set pending in the alarm handler. + check_sigalarm(); } if( err == 0 ) @@ -821,7 +861,10 @@ externC int sigtimedwait (const sigset_ signal_mutex.unlock(); - SIGNAL_RETURN(err); + if (err) + SIGNAL_RETURN(err); + else + SIGNAL_RETURN_VALUE( info->si_signo ); } //==========================================================================
--- a/packages/compat/uitron/current/ChangeLog +++ b/packages/compat/uitron/current/ChangeLog @@ -1,3 +1,8 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * include/uit_func.inl: CYG_SCHED_UNIQUE_PRIORITIES changed to + CYGINT_KERNEL_SCHEDULER_UNIQUE_PRIORITIES + 2000-09-13 Jonathan Larmour <jlarmour@redhat.com> * include/uit_objs.hxx (CYG_UITRON_OBJS_INIT_PRIORITY): Define
--- a/packages/compat/uitron/current/include/uit_func.inl +++ b/packages/compat/uitron/current/include/uit_func.inl @@ -463,7 +463,7 @@ ter_tsk ( ID tskid ) p->force_resume(); // let it run p->kill(); // and set prio high so it runs RIGHT NOW!! #ifdef CYGIMP_THREAD_PRIORITY -#if CYG_SCHED_UNIQUE_PRIORITIES != 0 +#if CYGINT_KERNEL_SCHEDULER_UNIQUE_PRIORITIES != 0 // see if we are already at prio 0: if ( 0 == cyg_uitron_dis_dsp_old_priority ) // then dispatch is enabled, we are not at prio 0 @@ -475,7 +475,7 @@ ter_tsk ( ID tskid ) } Cyg_Scheduler::unlock(); #ifdef CYGIMP_THREAD_PRIORITY -#if CYG_SCHED_UNIQUE_PRIORITIES == 0 +#if CYGINT_KERNEL_SCHEDULER_UNIQUE_PRIORITIES == 0 if ( (E_OK == ret) && (0 != cyg_uitron_dis_dsp_old_priority) ) { // then dispatching is disabled, so our prio is 0 too Cyg_Thread::yield(); // so let the dying thread run;
--- a/packages/cygmon/current/ChangeLog +++ b/packages/cygmon/current/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/cygmon.cdl: Improve cygmon.elf make dependencies + 2000-10-17 Drew Moseley <dmoseley@redhat.com> * misc/utils.c: Fix a typo. Also make sure we are ignoring the
--- a/packages/cygmon/current/cdl/cygmon.cdl +++ b/packages/cygmon/current/cdl/cygmon.cdl @@ -96,7 +96,7 @@ cdl_package CYGPKG_CYGMON { This is handled by a rule in the target CDL." make -priority 320 { - <PREFIX>/bin/cygmon.elf : <PACKAGE>/misc/ecos_bsp.c <PACKAGE>/misc/ecos_dummy.c <PACKAGE>/misc/cpu-mon.c <PACKAGE>/misc/monitor.c <PACKAGE>/misc/monitor_cmd.c <PACKAGE>/misc/ledit.c <PACKAGE>/misc/breakpoints.c <PACKAGE>/misc/bplist-dynamic.c <PACKAGE>/misc/utils.c <PACKAGE>/misc/generic_fmt32.c <PACKAGE>/misc/generic_mem.c <PACKAGE>/misc/bsp/common/bsp.c <PACKAGE>/misc/bsp/common/bsp_if.c <PACKAGE>/misc/bsp/common/shared-data.c <PACKAGE>/misc/bsp/common/sysinfo.c <PACKAGE>/misc/bsp/common/console-io.c <PACKAGE>/misc/bsp/common/debug-io.c <PACKAGE>/misc/bsp/common/sprintf.c <PACKAGE>/misc/bsp/common/syscall.c <PACKAGE>/misc/bsp/common/printf.c <PACKAGE>/misc/bsp/common/vprintf.c <PACKAGE>/misc/bsp/common/breakpoint.c <PACKAGE>/misc/bsp/common/singlestep.c <PACKAGE>/misc/bsp/common/generic-mem.c <PACKAGE>/misc/bsp/common/bsp_cache.c <PACKAGE>/misc/bsp/common/gdb-cpu.c <PACKAGE>/misc/bsp/common/hex-utils.c + <PREFIX>/bin/cygmon.elf : $(PREFIX)/lib/target.ld $(PREFIX)/lib/vectors.o $(PREFIX)/lib/libtarget.a $(PREFIX)/lib/libextras.a <PACKAGE>/misc/ecos_bsp.c <PACKAGE>/misc/ecos_dummy.c <PACKAGE>/misc/cpu-mon.c <PACKAGE>/misc/monitor.c <PACKAGE>/misc/monitor_cmd.c <PACKAGE>/misc/ledit.c <PACKAGE>/misc/breakpoints.c <PACKAGE>/misc/bplist-dynamic.c <PACKAGE>/misc/utils.c <PACKAGE>/misc/generic_fmt32.c <PACKAGE>/misc/generic_mem.c <PACKAGE>/misc/bsp/common/bsp.c <PACKAGE>/misc/bsp/common/bsp_if.c <PACKAGE>/misc/bsp/common/shared-data.c <PACKAGE>/misc/bsp/common/sysinfo.c <PACKAGE>/misc/bsp/common/console-io.c <PACKAGE>/misc/bsp/common/debug-io.c <PACKAGE>/misc/bsp/common/sprintf.c <PACKAGE>/misc/bsp/common/syscall.c <PACKAGE>/misc/bsp/common/printf.c <PACKAGE>/misc/bsp/common/vprintf.c <PACKAGE>/misc/bsp/common/breakpoint.c <PACKAGE>/misc/bsp/common/singlestep.c <PACKAGE>/misc/bsp/common/generic-mem.c <PACKAGE>/misc/bsp/common/bsp_cache.c <PACKAGE>/misc/bsp/common/gdb-cpu.c <PACKAGE>/misc/bsp/common/hex-utils.c @sh -c "mkdir -p misc/bsp/common $(dir $@)" $(CC) -c -I$(REPOSITORY)/$(PACKAGE)/misc $(INCLUDE_PATH) $(CFLAGS) -DHAVE_BSP -D__ECOS__ -o misc/ecos_bsp.o $(REPOSITORY)/$(PACKAGE)/misc/ecos_bsp.c $(CC) -c -I$(REPOSITORY)/$(PACKAGE)/misc $(INCLUDE_PATH) $(CFLAGS) -DHAVE_BSP -D__ECOS__ -o misc/ecos_dummy.o $(REPOSITORY)/$(PACKAGE)/misc/ecos_dummy.c
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/ChangeLog @@ -0,0 +1,36 @@ +2000-10-25 Drew Moseley <dmoseley@redhat.com> + + * src/sa1100mm_flash.c: New file. Support for SA1100 Multimedia + board. + * src/flash_query.c: Ditto. + * src/flash_program_buf.c: Ditto. + * src/flash_erase_block.c: Ditto. + * src/flash.h: Ditto. + * cdl/flash_sa1100mm.cdl: Ditto. + * ChangeLog: Ditto. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/cdl/flash_sa1100mm.cdl @@ -0,0 +1,82 @@ +# ==================================================================== +# +# flash_sa1100mm.cdl +# +# FLASH memory - Hardware support on StrongARM SA1100 Multimedia +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): dmoseley +# Original data: gthomas +# Contributors: +# Date: 2000-10-25 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_SA1100MM { + display "StrongARM SA1100 Multimedia FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_SA11X0 + + implements CYGHWR_IO_FLASH_DEVICE + + include_dir . + include_files ; # none _exported_ whatsoever + description "FLASH memory device support for StrongARM SA1100 Multimedia" + compile sa1100mm_flash.c + + make -priority 1 { + flash_erase_block.o: $(REPOSITORY)/$(PACKAGE)/src/flash_erase_block.c + $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_erase_block.c + echo " .globl flash_erase_block_end" >>flash_erase_block.s + echo "flash_erase_block_end:" >>flash_erase_block.s + $(CC) -c -o flash_erase_block.o flash_erase_block.s + $(AR) rcs $(PREFIX)/lib/libtarget.a flash_erase_block.o + } + make -priority 1 { + flash_program_buf.o: $(REPOSITORY)/$(PACKAGE)/src/flash_program_buf.c + $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_program_buf.c + echo " .globl flash_program_buf_end" >>flash_program_buf.s + echo "flash_program_buf_end:" >>flash_program_buf.s + $(CC) -c -o flash_program_buf.o flash_program_buf.s + $(AR) rcs $(PREFIX)/lib/libtarget.a flash_program_buf.o + } + make -priority 1 { + flash_query.o: $(REPOSITORY)/$(PACKAGE)/src/flash_query.c + $(CC) -S $(INCLUDE_PATH) $(CFLAGS) -g0 -fno-function-sections $(REPOSITORY)/$(PACKAGE)/src/flash_query.c + echo " .globl flash_query_end" >>flash_query.s + echo "flash_query_end:" >>flash_query.s + $(CC) -c -o flash_query.o flash_query.s + $(AR) rcs $(PREFIX)/lib/libtarget.a flash_query.o + } +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/src/flash.h @@ -0,0 +1,66 @@ +//========================================================================== +// +// flash.h +// +// Flash programming - device constants, etc. +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-10-25 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef _FLASH_HWR_H_ +#define _FLASH_HWR_H_ + +// SA1100 Multimedia FLASH layout +// 2x 28F016SV +// each device is 16x1M organized as 32x128K blocks + +#define FLASH_Read_ID 0x00900090 +#define FLASH_Read_Status 0x00700070 +#define FLASH_Clear_Status 0x00500050 +#define FLASH_Status_Ready 0x00800080 +#define FLASH_Program 0x00100010 +#define FLASH_Block_Erase 0x00200020 +#define FLASH_Confirm 0x00D000D0 +#define FLASH_Reset 0xFFFFFFFF + +#define FLASH_BLOCK_SIZE 0x40000 + +#define FLASH_Intel_code 0x89 +#define FLASH_28F016SV_low 0xA0 +#define FLASH_28F016SV_hi 0x66 + +#endif // _FLASH_HWR_H_
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/src/flash_erase_block.c @@ -0,0 +1,86 @@ +//========================================================================== +// +// flash_erase_block.c +// +// Flash programming +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-07-14 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include "flash.h" + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_cache.h> + +// +// CAUTION! This code must be copied to RAM before execution. Therefore, +// it must not contain any code which might be position dependent! +// + +int +flash_erase_block(volatile unsigned long *block) +{ + unsigned long stat; + int timeout = 5000000; + int cache_on; + + HAL_DCACHE_IS_ENABLED(cache_on); + if (cache_on) { + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + } + + // Clear any error conditions + *block = FLASH_Clear_Status; + + // Set to erase + *block = FLASH_Block_Erase; + *block = FLASH_Confirm; + while(((stat = *block) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) break; + } + + // Restore ROM to "normal" mode + *block = FLASH_Reset; + + if (cache_on) { + HAL_DCACHE_ENABLE(); + } + + return stat; +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/src/flash_program_buf.c @@ -0,0 +1,94 @@ +//========================================================================== +// +// flash_program_buf.c +// +// Flash programming +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-07-14 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include "flash.h" + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_cache.h> + +// +// CAUTION! This code must be copied to RAM before execution. Therefore, +// it must not contain any code which might be position dependent! +// + +int +flash_program_buf(volatile unsigned long *addr, unsigned long *data, int len) +{ + unsigned long stat = 0; + int timeout = 5000000; + int cache_on; + volatile unsigned long *orig_addr = addr; + + HAL_DCACHE_IS_ENABLED(cache_on); + if (cache_on) { + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + } + + // Clear any error conditions + *addr = FLASH_Clear_Status; + + while (len > 0) { + *addr = FLASH_Program; + *addr = *data++; + timeout = 5000000; + while (((stat = *addr) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + goto bad; + } + } + addr++; + len -= sizeof(unsigned long); + } + + // Restore ROM to "normal" mode + bad: + *orig_addr = FLASH_Reset; + + if (cache_on) { + HAL_DCACHE_ENABLE(); + } + + return stat; +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/src/flash_query.c @@ -0,0 +1,86 @@ +//========================================================================== +// +// flash_query.c +// +// Flash programming - query device +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-07-26 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include "flash.h" + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_cache.h> + +// +// CAUTION! This code must be copied to RAM before execution. Therefore, +// it must not contain any code which might be position dependent! +// + +#define CNT 20*1000*10 // Approx 200ms + +int +flash_query(unsigned char *data) +{ + volatile unsigned long *lROM; + volatile unsigned char *cROM; + int i, cnt; + int cache_on; + + HAL_DCACHE_IS_ENABLED(cache_on); + if (cache_on) { + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + } + + lROM = (unsigned long *)0x08000000; + cROM = (unsigned char *)0x08000000; + + lROM[0] = FLASH_Read_ID; + for (cnt = CNT; cnt > 0; cnt--) ; + for (i = 0; i < 8; i++) { + *data++ = cROM[i]; + } + lROM[0] = FLASH_Reset; + + if (cache_on) { + HAL_DCACHE_ENABLE(); + } + + return 0; +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/sa1100mm/current/src/sa1100mm_flash.c @@ -0,0 +1,117 @@ +//========================================================================== +// +// sa1100mm_flash.c +// +// Flash programming +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-07-26 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_cache.h> + +#define _FLASH_PRIVATE_ +#include <cyg/io/flash.h> + +#include "flash.h" + +int +flash_hwr_init(void) +{ + unsigned char data[96]; + extern char flash_query, flash_query_end; + typedef int code_fun(unsigned char *); + code_fun *_flash_query; + int code_len, stat, num_regions, region_size; + + // Copy 'program' code to RAM for execution + code_len = (unsigned long)&flash_query_end - (unsigned long)&flash_query; + _flash_query = (code_fun *)flash_info.work_space; + memcpy(_flash_query, &flash_query, code_len); + HAL_DCACHE_SYNC(); // Should guarantee this code will run + HAL_ICACHE_DISABLE(); // is also required to avoid old contents + + stat = (*_flash_query)(data); + + HAL_ICACHE_ENABLE(); + + if ((data[0] == FLASH_Intel_code) && + (data[4] == FLASH_28F016SV_low) && + (data[5] == FLASH_28F016SV_hi)) { + num_regions = 32; + region_size = 0x20000; + flash_info.block_size = region_size; + flash_info.blocks = num_regions; + flash_info.start = (void *)0x08000000; + flash_info.end = (void *)(0x08000000+(num_regions*region_size)); + return FLASH_ERR_OK; + } else { + printf("Can't identify FLASH, sorry\n"); + diag_dump_buf(data, sizeof(data)); + return FLASH_ERR_HWR; + } +} + +// Map a hardware status to a package error +int +flash_hwr_map_error(int err) +{ + if (err & 0x7E) { + if (err & 0x10) { + return FLASH_ERR_PROGRAM; + } else + if (err & 0x20) { + return FLASH_ERR_ERASE; + } else + return FLASH_ERR_HWR; // FIXME + } else { + return FLASH_ERR_OK; + } +} + +// See if a range of FLASH addresses overlaps currently running code +bool +flash_code_overlaps(void *start, void *end) +{ + extern char _stext, _etext; + + return ((((unsigned long)&_stext >= (unsigned long)start) && + ((unsigned long)&_stext < (unsigned long)end)) || + (((unsigned long)&_etext >= (unsigned long)start) && + ((unsigned long)&_etext < (unsigned long)end))); +}
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/ref4955/current/ChangeLog @@ -0,0 +1,58 @@ +2000-09-18 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: Use CDL to specify testing parameters. + + * include/mips_tx49_ref4955_ser.inl: Follow type naming changes in + generic driver. + +2000-09-14 Jesper Skov <jskov@redhat.com> + + * include/mips_tx49_ref4955_ser.inl: Use with generic 16x5x serial + driver. + * src/ref4955_serial.c: Deleted. + * src/ref4955_serial.h: Deleted. + * cdl/ser_mips_ref4955.cdl: Changed accordingly. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/ref4955_serial.c (pc_serial_set_config): Now use keys to make + more flexible. + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_ref4955.cdl: + * src/ref4955_serial.h: + * src/ref4955_serial.c: + REF4955 serial driver. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/ref4955/current/cdl/ser_mips_ref4955.cdl @@ -0,0 +1,175 @@ +# ==================================================================== +# +# ser_mips_ref4955.cdl +# +# eCos serial MIPS/REF4955 configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 2000-05-24 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_REF4955 { + display "REF4955 serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_TX49_REF4955 + + requires CYGPKG_ERROR + include_dir cyg/io + + description " + This option enables the serial device drivers for the + REF4955." + doc redirect/ecos-device-drivers.html + + # FIXME: This really belongs in the GENERIC_16X5X package + cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED { + display "Generic 16x5x serial driver required" + } + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/mips_tx49_ref4955_ser.inl>" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_mips_ref4955.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 { + display "REF4955 serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 0." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME { + display "Device name for the REF4955 serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the + REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD { + display "Baud rate for the REF4955 serial port 0 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE { + display "Buffer size for the REF4955 serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 { + display "REF4955 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the + REF4955 port 1." + + implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED +# implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW +# implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + cdl_option CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME { + display "Device name for the REF4955 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for + the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD { + display "Baud rate for the REF4955 serial port 1 driver" + flavor data + legal_values { 1200 2400 4800 9600 14400 19200 38400 57600 115200} + default_value 38400 + description " + This option specifies the default baud rate (speed) + for the REF4955 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE { + display "Buffer size for the REF4955 serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers + used for the REF4955 port 1." + } + } + + + cdl_component CYGPKG_IO_SERIAL_MIPS_REF4955_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"ref4955\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_ref4955.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/ref4955/current/include/mips_tx49_ref4955_ser.inl @@ -0,0 +1,168 @@ +//========================================================================== +// +// devs/serial/mips/ref4955/src/mips_tx49_ref4955_ser.inl +// +// REF4955 Serial I/O definitions. +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:gthomas, jskov +// Date: 2000-05-24 +// Purpose: REF4955 Serial definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1 +#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2 + +//----------------------------------------------------------------------------- +// The REF4955 board has a 14.318 MHz crystal, but the PC87338 part +// uses a 24MHz internal clock for baud rate calculation. +#define BAUD_DIVISOR(_x_) 24000000/13/16/(_x_) + +static unsigned short select_baud[] = { + 0, // Unused + 0, // 50 + 0, // 75 + 0, // 110 + 0, // 134.5 + 0, // 150 + 0, // 200 + 0, // 300 + 0, // 600 + BAUD_DIVISOR(1200), + 0, // 1800 + BAUD_DIVISOR(2400), + 0, // 3600 + BAUD_DIVISOR(4800), + 0 , // 7200 + BAUD_DIVISOR(9600), + BAUD_DIVISOR(14400), + BAUD_DIVISOR(19200), + BAUD_DIVISOR(38400), + BAUD_DIVISOR(57600), + BAUD_DIVISOR(115200), + 0, // 230400 +}; + +//----------------------------------------------------------------------------- +// Port 0 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL0 +static pc_serial_info pc_serial_info0 = {CYG_DEVICE_SERIAL_SCC1, + CYGNUM_HAL_INTERRUPT_DEBUG_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE > 0 +static unsigned char pc_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; +static unsigned char pc_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf0[0], + sizeof(pc_serial_out_buf0), + &pc_serial_in_buf0[0], + sizeof(pc_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel0, + pc_serial_funs, + pc_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io0, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel0 + ); +#endif + +//----------------------------------------------------------------------------- +// Port 1 descriptors + +#ifdef CYGPKG_IO_SERIAL_MIPS_REF4955_SERIAL1 +static pc_serial_info pc_serial_info1 = {CYG_DEVICE_SERIAL_SCC2, + CYGNUM_HAL_INTERRUPT_USER_UART}; +#if CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE > 0 +static unsigned char pc_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; +static unsigned char pc_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &pc_serial_out_buf1[0], + sizeof(pc_serial_out_buf1), + &pc_serial_in_buf1[0], + sizeof(pc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(pc_serial_channel1, + pc_serial_funs, + pc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_REF4955_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(pc_serial_io1, + CYGDAT_IO_SERIAL_MIPS_REF4955_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + pc_serial_init, + pc_serial_lookup, // Serial driver may need initializing + &pc_serial_channel1 + ); +#endif + +// EOF mips_tx49_ref4955_ser.inl
new file mode 100644 --- /dev/null +++ b/packages/devs/wallclock/mips/ref4955/current/ChangeLog @@ -0,0 +1,40 @@ +2000-05-26 Jesper Skov <jskov@redhat.com> + + * cdl/wallclock_ref4955.cdl: + * src/wallclock_ref4955.cxx: + * src/ds1742.inl: [deleted] + Added set-get mode. Moved Dallas driver to its own package. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/wallclock_ref4955.cdl: + * src/wallclock_ref4955.cxx: + * src/ds1742.inl: + Added wallclock driver REF4955 (Dallas 1742) + (set_ds_hwclock): Clear frequency test bit. + +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### + +
new file mode 100644 --- /dev/null +++ b/packages/devs/wallclock/mips/ref4955/current/cdl/wallclock_ref4955.cdl @@ -0,0 +1,93 @@ +# ==================================================================== +# +# wallclock_ref4955.cdl +# +# eCos wallclock for REF4955 driver configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: jskov +# Date: 2000-05-25 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955 { + parent CYGPKG_IO_WALLCLOCK + active_if CYGPKG_IO_WALLCLOCK + display "REF4955 wallclock driver" + requires CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742 + requires CYGPKG_HAL_MIPS_TX49_REF4955 + hardware + compile wallclock_ref4955.cxx + implements CYGINT_WALLCLOCK_HW_IMPLEMENTATIONS + implements CYGINT_WALLCLOCK_SET_GET_MODE_SUPPORTED + active_if CYGIMP_WALLCLOCK_HARDWARE + + cdl_option CYGIMP_WALLCLOCK_HARDWARE { + parent CYGPKG_IO_WALLCLOCK_IMPLEMENTATION + display "Hardware wallclock" + default_value 1 + implements CYGINT_WALLCLOCK_IMPLEMENTATIONS + } + + cdl_component CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955_OPTIONS { + display "REF4955 wallclock build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the wallclock device. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the wallclock device. These flags are removed from + the set of global flags if present." + } + + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/wallclock/mips/ref4955/current/src/wallclock_ref4955.cxx @@ -0,0 +1,114 @@ +//========================================================================== +// +// devs/wallclock/mips/ref4955/ref4955.cxx +// +// Wallclock implementation +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-05-25 +// Purpose: Wallclock driver for REF4955 +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/kernel.h> // Kernel config +#include <pkgconf/wallclock.h> // Wallclock device config + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/infra/cyg_type.h> // Common type definitions and support + +#include <cyg/io/wallclock.hxx> // The WallClock API +#include <cyg/io/wallclock/wallclock.inl> // Helpers + +#include <cyg/infra/diag.h> // For debugging + +// REF4955 has a Dallas 1742W part. +#define DS_BASE 0xb5000000 +#include <cyg/io/wallclock/ds1742.inl> + +//----------------------------------------------------------------------------- +// Functions required for the hardware-driver API. + +// Returns the number of seconds elapsed since 1970-01-01 00:00:00. +cyg_uint32 +Cyg_WallClock::get_hw_seconds(void) +{ + cyg_uint32 year, month, mday, hour, minute, second; + + get_ds_hwclock(&year, &month, &mday, &hour, &minute, &second); + +#if 0 + // This will cause the test to eventually fail due to these printouts + // causing timer interrupts to be lost... + diag_printf("year %02d\n", year); + diag_printf("month %02d\n", month); + diag_printf("mday %02d\n", mday); + diag_printf("hour %02d\n", hour); + diag_printf("minute %02d\n", minute); + diag_printf("second %02d\n", second); +#endif + + cyg_uint32 now = _simple_mktime(year, month, mday, hour, minute, second); + return now; +} + +#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE + +// Sets the clock. Argument is seconds elapsed since 1970-01-01 00:00:00. +void +Cyg_WallClock::set_hw_seconds( cyg_uint32 secs ) +{ + cyg_uint32 year, month, mday, hour, minute, second; + + _simple_mkdate(secs, &year, &month, &mday, &hour, &minute, &second); + + set_ds_hwclock(year, month, mday, hour, minute, second); +} + +#endif + +void +Cyg_WallClock::init_hw_seconds(void) +{ +#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE + init_ds_hwclock(); +#else + // This is our base: 1970-01-01 00:00:00 + // Set the HW clock - if for nothing else, just to be sure it's in a + // legal range. Any arbitrary base could be used. + // After this the hardware clock is only read. + set_ds_hwclock(1970,1,1,0,0,0); +#endif +} + +//----------------------------------------------------------------------------- +// End of devs/wallclock/mips/ref4955/wallclock_ref4955.cxx
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -124,6 +124,16 @@ package CYGPKG_DEVS_FLASH_EBSA285 { on the StrongARM EBSA-285 platform." } +package CYGPKG_DEVS_FLASH_SA1100MM { + alias { "FLASH memory support for StrongARM SA1100 Multimedia" flash_sa1100mm } + directory devs/flash/arm/sa1100mm + script flash_sa1100mm.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the StrongARM SA1100 Multimedia platform." +} + package CYGPKG_DEVS_FLASH_EDB7XXX { alias { "FLASH memory support for Cirrus Logic EDB7xxx" flash_edb7xxx } directory devs/flash/arm/edb7xxx @@ -250,6 +260,15 @@ package CYGPKG_IO_SERIAL_TX39_JMR3904 { } +package CYGPKG_IO_SERIAL_MIPS_REF4955 { + alias { "TX49 REF4955 serial device drivers" + devs_serial_mips_ref4955 ref4955_serial_driver } + hardware + directory devs/serial/mips/ref4955 + script ser_mips_ref4955.cdl + description "TX49 REF4955 serial device drivers" +} + package CYGPKG_IO_SERIAL_MIPS_VRC4373 { alias { "VRC4373 serial device drivers" devs_serial_mips_vrc4373 vrc4373_serial_driver } @@ -460,6 +479,15 @@ package CYGPKG_DEVICES_WALLCLOCK_DALLAS_ the Dallas 1742 wallclock." } +package CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955 { + alias { "Wallclock driver for REF4955 board" devices_wallclock_ref4955 device_wallclock_ref4955 } + directory devs/wallclock/mips/ref4955 + script wallclock_ref4955.cdl + hardware + description " + This package provides a wallclock driver implementation for the + Toshiba REF4955 board." +} package CYGPKG_DEVICES_WATCHDOG_ARM_AEB { @@ -768,6 +796,17 @@ package CYGPKG_HAL_ARM_SA11X0_BRUTUS { The BRUTUS HAL package provides the support needed to run eCos on a Intel StrongARM SA1110 evaulation board (brutus)." } + +package CYGPKG_HAL_ARM_SA11X0_SA1100MM { + alias { "Intel SA1100 Multimedia eval board" hal_arm_sa11x0_sa1100mm } + directory hal/arm/sa11x0/sa1100mm + script hal_arm_sa11x0_sa1100mm.cdl + hardware + description " + The MULTIMEDIA HAL package provides the support needed to run + eCos on a Intel StrongARM SA1110 Multimedia evaluation board." +} + package CYGPKG_HAL_ARM_EDB7XXX { alias { "Cirrus Logic development board" hal_arm_edb7xxx arm_edb7xxx_hal } directory hal/arm/edb7xxx @@ -798,17 +837,37 @@ package CYGPKG_HAL_SH { description " The SH (SuperH) architecture HAL package provides generic support for this processor architecture. It is also - necessary to select a specific target platform HAL - package." + necessary to select variant and target platform HAL + packages." +} + +package CYGPKG_HAL_SH_SH3 { + alias { "SH3 architecture" hal_sh_sh3 } + directory hal/sh/sh3 + script hal_sh_sh3.cdl + hardware + description " + The SH3 (SuperH 3) variant HAL package provides generic + support for SH3 variant CPUs." +} + +package CYGPKG_HAL_SH_SH4 { + alias { "SH4 architecture" hal_sh_sh4 } + directory hal/sh/sh4 + script hal_sh_sh4.cdl + hardware + description " + The SH4 (SuperH 4) variant HAL package provides generic + support for SH4 variant CPUs." } package CYGPKG_HAL_SH_EDK7708 { alias { "Hitachi SH7708 board" hal_sh_edk sh_edk_hal } - directory hal/sh/edk + directory hal/sh/edk7708 script hal_sh_edk7708.cdl hardware description " - The edk HAL package provides the support needed to run + This SH HAL package provides the support needed to run eCos on a Hitachi SH3 EDK7708 board." } package CYGPKG_HAL_SH_SH7708_CQ7708 { @@ -817,10 +876,19 @@ package CYGPKG_HAL_SH_SH7708_CQ7708 { script hal_sh_sh7708_cq7708.cdl hardware description " - The cq HAL package provides the support needed to run + This SH HAL package provides the support needed to run eCos on a CqREEK SH7708 board." } +package CYGPKG_HAL_SH_SH7750_CQ7750 { + alias { "CqREEK SH7750 board" hal_sh_cqsh4 sh_cqsh4_hal } + directory hal/sh/cq7750 + script hal_sh_sh7750_cq7750.cdl + hardware + description " + This SH HAL package provides the support needed to run + eCos on a CqREEK SH7750 board." +} # -------------------------------------------------------------------------- # i386 packages @@ -926,6 +994,17 @@ package CYGPKG_HAL_POWERPC_PPC60x { select a specific target platform HAL package." } +package CYGPKG_HAL_POWERPC_PPC40x { + alias { "PowerPC 40x variant HAL" hal_ppc40x ppc40x_hal ppc40x_arch_hal } + directory hal/powerpc/ppc40x/ + script hal_powerpc_ppc40x.cdl + hardware + description " + The PowerPC 40x variant HAL package provides generic support + for this processor variant. It is also necessary to + select a specific target platform HAL package." +} + package CYGPKG_HAL_POWERPC_COGENT { alias { "Cogent CMA286/287 board" hal_powerpc_cogent powerpc_cogent_hal } directory hal/powerpc/cogent @@ -1037,6 +1116,27 @@ package CYGPKG_HAL_MIPS_TX39_JMR3904 { } +package CYGPKG_HAL_MIPS_TX49 { + alias { "TX49 chip HAL" hal_tx49 tx49_hal tx49_arch_hal } + directory hal/mips/tx49/ + script hal_mips_tx49.cdl + hardware + description " + The TX49 architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." +} + +package CYGPKG_HAL_MIPS_TX49_REF4955 { + alias { "Toshiba TX4955 reference platform" hal_tx49_ref4955 tx49_ref4955_hal } + directory hal/mips/ref4955 + script hal_mips_tx49_ref4955.cdl + hardware + description " + The REF4955 HAL package should be used when targetting the + actual hardware." +} + package CYGPKG_HAL_MIPS_VR4300 { alias { "VR4300 chip HAL" hal_vr4300 vr4300_hal vr4300_arch_hal } @@ -1231,6 +1331,19 @@ target brutus { eCos on an Intel StrongARM SA1100 evaluation board." } +target sa1100mm { + alias { "Intel StrongARM SA1100 Multimedia board" sa1100mm } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_SA11X0 + CYGPKG_HAL_ARM_SA11X0_SA1100MM + CYGPKG_IO_SERIAL_ARM_SA11X0 + } + description " + The sa1100mm target provides the packages needed to run + eCos on an Intel StrongARM SA1100 Multimedia evaluation board." +} + + target edb7xxx { alias { "Cirrus Logic development board" edb7211 eb7xxx eb7211 } packages { CYGPKG_HAL_ARM @@ -1259,6 +1372,7 @@ CMA230 (ARM7TDMI) or CMA222 (ARM710T) bo target sh7708 { alias { "Hitachi EDK/SH7708 board" edk7708 } packages { CYGPKG_HAL_SH + CYGPKG_HAL_SH_SH3 CYGPKG_HAL_SH_EDK7708 CYGPKG_DEVICES_WALLCLOCK_SH3 CYGPKG_IO_SERIAL_SH_SCI @@ -1273,6 +1387,7 @@ target sh7708 { target cq7708 { alias { "CqREEK SH7708 board" cq7708 } packages { CYGPKG_HAL_SH + CYGPKG_HAL_SH_SH3 CYGPKG_HAL_SH_SH7708_CQ7708 CYGPKG_IO_SERIAL_SH_SCI CYGPKG_IO_SERIAL_SH_CQ7708 @@ -1282,6 +1397,17 @@ target cq7708 { eCos on a CqREEK SH7708 board." } +target cq7750 { + alias { "CqREEK SH7750 board" cqsh4 } + packages { CYGPKG_HAL_SH + CYGPKG_HAL_SH_SH4 + CYGPKG_HAL_SH_SH7750_CQ7750 + CYGPKG_IO_SERIAL_SH_SCIF } + description " + The sh7750 target provides the packages needed to run + eCos on a CqREEK SH7750 board." +} + # -------------------------------------------------------------------------- # i386 targets target linux { @@ -1414,6 +1540,21 @@ target tx39_sim { use any of the eCos device drivers when the simulator is running in this mode." } +target ref4955 { + alias { "Toshiba TX4955 reference platform" tx49 } + packages { CYGPKG_HAL_MIPS + CYGPKG_HAL_MIPS_TX49 + CYGPKG_HAL_MIPS_TX49_REF4955 + CYGPKG_IO_SERIAL_GENERIC_16X5X + CYGPKG_IO_SERIAL_MIPS_REF4955 + CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955 + CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742 + } + description " + The ref4955 target provides the packages needed to run + eCos on a Toshiba TX4955 reference platform." +} + target vrc4373 { alias { "NEC VRC4373 board" } packages { CYGPKG_HAL_MIPS
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/ChangeLog @@ -0,0 +1,41 @@ +2000-10-25 Drew Moseley <dmoseley@redhat.com> + + * src/sa1100mm_misc.c: New file. Support for SA1100 Multimedia + board. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.mlt: Ditto. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.ldi: Ditto. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.h: Ditto. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.mlt: Ditto. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.ldi: Ditto. + * include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.h: Ditto. + * include/sa1100mm.h: Ditto. + * include/hal_platform_setup.h: Ditto. + * include/hal_platform_ints.h: Ditto. + * cdl/hal_arm_sa11x0_sa1100mm.cdl: Ditto. + * Changelog: Ditto. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/cdl/hal_arm_sa11x0_sa1100mm.cdl @@ -0,0 +1,329 @@ +# ==================================================================== +# +# hal_arm_sa11x0_sa1100mm.cdl +# +# ARM SA1100/Multimedia platform HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): dmoseley +# Original data: gthomas +# Contributors: +# Date: 2000-10-25 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_SA11X0_SA1100MM { + display "ARM SA1100/Multimedia evaluation board" + parent CYGPKG_HAL_ARM_SA11X0 + hardware + include_dir cyg/hal + define_header hal_arm_sa11x0_sa1100mm.h + description " + This HAL platform package provides generic + support for the Intel StrongARM SA1100 based evalation board, + known as 'SA1100 Multimedia'." + + compile sa1100mm_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_sa11x0.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_sa11x0_sa1100mm.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"StrongARM 1100\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Multimedia development system\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the SA1100 Multimedia eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using eCos GDB + stubs. Select 'rom' when building a stand-alone application + which will be put into ROM, or for the special case of + building the eCos GDB stubs themselves." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 1 + description " + The multimedia board has two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 1 + description " + The multimedia board has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=strongarm1100 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_HAL_ARM_SA11X0_SA1100MM_OPTIONS { + display "StrongARM SA1100/Multimedia build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_ARM_SA11X0_SA1100MM_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the StrongARM SA1100 Multimedia HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_SA11X0_SA1100MM_CFLAGS_REMOVE { + display "Supressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the StrongARM SA1100 Multimedia HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGPKG_HAL_ARM_SA11X0_SA1100MM_TESTS { + display "StrongARM SA1100/Multimedia tests" + flavor data + no_define +# calculated { "tests/dram-test" } + calculated { "" } + description " + This option specifies the set of tests for the StrongARM SA1100 Multimedia HAL." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_sa11x0_sa1100mm_ram" : \ + "arm_sa11x0_sa1100mm_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_sa1100mm_ram.ldi>" : \ + "<pkgconf/mlt_arm_sa11x0_sa1100mm_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_sa11x0_sa1100mm_ram.h>" : \ + "<pkgconf/mlt_arm_sa11x0_sa1100mm_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/hal_platform_ints.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Date: 2000-05-08 +// Purpose: Define Interrupt support +// Description: The interrupt details for the SA1100/Multimedia are defined here. +// Usage: +// #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_GPIO0 0 +#define CYGNUM_HAL_INTERRUPT_GPIO1 1 +#define CYGNUM_HAL_INTERRUPT_GPIO2 2 +#define CYGNUM_HAL_INTERRUPT_GPIO3 3 +#define CYGNUM_HAL_INTERRUPT_GPIO4 4 +#define CYGNUM_HAL_INTERRUPT_GPIO5 5 +#define CYGNUM_HAL_INTERRUPT_GPIO6 6 +#define CYGNUM_HAL_INTERRUPT_GPIO7 7 +#define CYGNUM_HAL_INTERRUPT_GPIO8 8 +#define CYGNUM_HAL_INTERRUPT_GPIO9 9 +#define CYGNUM_HAL_INTERRUPT_GPIO10 10 +#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly +#define CYGNUM_HAL_INTERRUPT_LCD 12 +#define CYGNUM_HAL_INTERRUPT_UDC 13 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_UART2 16 +#define CYGNUM_HAL_INTERRUPT_UART3 17 +#define CYGNUM_HAL_INTERRUPT_MCP 18 +#define CYGNUM_HAL_INTERRUPT_SSP 19 +#define CYGNUM_HAL_INTERRUPT_TIMER0 26 +#define CYGNUM_HAL_INTERRUPT_TIMER1 27 +#define CYGNUM_HAL_INTERRUPT_TIMER2 28 +#define CYGNUM_HAL_INTERRUPT_TIMER3 29 +#define CYGNUM_HAL_INTERRUPT_HZ 30 +#define CYGNUM_HAL_INTERRUPT_ALARM 31 + +// GPIO bits 31..11 can generate interrupts as well, but they all +// end up clumped into interrupt signal #11. Using the symbols +// below allow for detection of these separately. + +#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11) +#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12) +#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13) +#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14) +#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15) +#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16) +#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17) +#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18) +#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19) +#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20) +#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21) +#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22) +#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23) +#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24) +#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25) +#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26) +#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27) + +#define CYGNUM_HAL_INTERRUPT_NONE -1 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX (27+32) + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/hal_platform_setup.h @@ -0,0 +1,370 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, dmoseley +// Travis C. Furrer <furrer@mit.edu> +// Date: 2000-05-08 +// Purpose: Intel SA1100 Multimedia platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// This file should only be used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_sa11x0.h> // Platform specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions + +#if defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU + +#if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000) +#define SA11X0_PLL_CLOCK 0x0 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700) +#define SA11X0_PLL_CLOCK 0x1 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500) +#define SA11X0_PLL_CLOCK 0x2 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200) +#define SA11X0_PLL_CLOCK 0x3 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000) +#define SA11X0_PLL_CLOCK 0x4 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700) +#define SA11X0_PLL_CLOCK 0x5 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500) +#define SA11X0_PLL_CLOCK 0x6 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200) +#define SA11X0_PLL_CLOCK 0x7 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900) +#define SA11X0_PLL_CLOCK 0x8 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700) +#define SA11X0_PLL_CLOCK 0x9 +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400) +#define SA11X0_PLL_CLOCK 0xA +#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200) +#define SA11X0_PLL_CLOCK 0xB +#else +#error Invalid processor clock speed +#endif + +// This function is called very early on by the boot ROM (or by any ROM +// based startup). It's job is to initialize the hardware to a known state +// so that eCos applications can execute properly. + +// This version of the code is patterned after the contribution from +// Travis Furer (@MIT) + + +// Define macro used to diddle the LEDs during early initialization. +// Can use r0+r1. Argument in \x. + +#define CYGHWR_LED_MACRO _set_LEDS \x + +// Initialize GPIOs +#define GPIO_GRER (SA11X0_GPIO_RISING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL) +#define GPIO_GFER (SA11X0_GPIO_FALLING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL) +#define GPIO_GAFR (SA11X0_GPIO_ALTERNATE_FUNCTION-SA11X0_GPIO_PIN_LEVEL) +#define GPIO_GEDR (SA11X0_GPIO_EDGE_DETECT_STATUS-SA11X0_GPIO_PIN_LEVEL) +#define GPIO_GPDR (SA11X0_GPIO_PIN_DIRECTION-SA11X0_GPIO_PIN_LEVEL) +#define GPIO_GPCR (SA11X0_GPIO_PIN_OUTPUT_CLEAR-SA11X0_GPIO_PIN_LEVEL) + .macro _init_GPIO + ldr r1,=SA11X0_GPIO_PIN_LEVEL + mov r0,#0 + str r0,[r1,#GPIO_GRER] // Disable rising edge detects + str r0,[r1,#GPIO_GFER] // Disable falling edge detects + str r0,[r1,#GPIO_GAFR] // No alt. funcs. during init + sub r0,r0,#1 + str r0,[r1,#GPIO_GPCR] // Force all outputs to low + str r0,[r1,#GPIO_GEDR] // Clear edge detect status + ldr r0,=0x00100300 + str r0,[r1,#GPIO_GPDR] // Only LEDs outputs (for now) + .endm + +#define DISCRETE_LED_REG_BASE 0x18800000 +#define KEYPAD_IO_O 0x4 +#define DISCRETE_LED_O 0x6 +#define HEX_LED_REG_BASE 0x18c00000 +#define HEX_LED_O 0x0 +#define HEX_DATA_MASK 0x0F +#define HEX_LED_0_STROBE 0x10 +#define HEX_LED_1_STROBE 0x20 +#define HEX_LED_BOTH_STROBES (HEX_LED_0_STROBE | HEX_LED_1_STROBE) + +// Display value on hex LED display + .macro _set_LEDS,val + ldr r1, =HEX_LED_REG_BASE + + ldr r2, =\val + and r2, r2, #0xf + orr r0, r2, #HEX_LED_0_STROBE + str r0, [r1, #HEX_LED_O] + + ldr r2, =\val + mov r2, r2, LSR #4 + orr r0, r2, #HEX_LED_1_STROBE + str r0, [r1, #HEX_LED_O] + + nop + .endm + +// Initialize HEX display. + .macro _init_HEX_DISPLAY + ldr r1, =DISCRETE_LED_REG_BASE + ldr r2, =~0 + str r2, [r1, #KEYPAD_IO_O] + str r2, [r1, #DISCRETE_LED_O] + _set_LEDS 0x23 + .endm + +// Setup pin directions: +// inputs: all serial receive pins +// outputs: all LCD pins, all serial transmit pins + .macro _init_PERIPHERAL_PINS + ldr r0,=0x00355FFF + ldr r1,=SA11X0_PPC_PIN_DIRECTION + str r0,[r1] + mov r0,#0 // Force initial state + ldr r1,=SA11X0_PPC_PIN_STATE + str r0,[r1] + ldr r1,=SA11X0_PPC_PIN_ASSIGNMENT // Disable any reassignments + str r0,[r1] + .endm + +// Set core frequency (this can take up to 150us) + .macro _set_CLOCK_FREQUENCY + mov r0,#SA11X0_PLL_CLOCK + ldr r1,=SA11X0_PWR_MGR_PLL_CONFIG + str r0,[r1] + .endm + +// Enable clock switching (must be done after setting core frequency) + .macro _enable_CLOCK_SWITCHING + mcr p15,0,r1,c15,c1,2 + .endm + +// Initialize memory interfaces. (ROM, SRAM, Flash, DRAM, etc) +// +// SA1100 Multimedia memory is as follows: +// ROM 128K (assuming 32 bit accesses) +// Flash 4M (assuming 32 bit accesses) +// RAM 8M +// +// From SA11X0 Manual, Section 10.7.1: +// +// The following flow should be followed when coming out of +// reset, whether for sleep or power-up: +// +// - Read boot ROM and write to memory configuration +// registers, but do not enable DRAM banks. +// +// - If necessary, finish any DRAM power-up wait period +// (usually about 100us). +// +// - If coming out of sleep, see Section 9.5, Power +// Manager on page 9-26 on how to release the nCAS and +// nRAS pins from their self-refresh state. +// +// - If coming out of sleep, wait the DRAM-specific +// post-self-refresh precharge period before issuing +// a new DRAM transaction. +// +// - If power-on reset, perform the number of +// initialization refreshes required by the specific +// DRAM part by reading disabled banks. A read from +// any disabled bank will refresh all four banks. +// +// - Enable DRAM banks by setting MDCNFG:DE3:0. +// +#define DRAM_CONFIG_VALUE (SA11X0_DRAM_REFRESH_INTERVAL(312) | \ + SA11X0_DATA_INPUT_LATCH_CAS_PLUS_THREE | \ + SA11X0_DRAM_CAS_BEFORE_RAS(5) | \ + SA11X0_DRAM_RAS_PRECHARGE(4) | \ + SA11X0_DRAM_CLOCK_CPU_CLOCK | \ + SA11X0_DRAM_ROW_ADDRESS_BITS_11 | \ + SA11X0_DRAM_BANK_0_ENABLED | \ + SA11X0_DRAM_BANK_1_DISABLED | \ + SA11X0_DRAM_BANK_2_DISABLED | \ + SA11X0_DRAM_BANK_3_DISABLED) + +#define DRAM_CAS0_WAVEFORM 0xF0F0F00F +#define DRAM_CAS1_WAVEFORM 0XF0F0F0F0 +#define DRAM_CAS2_WAVEFORM 0xFFFFFFF0 + +#define BANK_0_CONTROL_VALUE SA11X0_STATIC_ROM_TYPE_FLASH | \ + SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS | \ + SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_RECOVERY(0x7) +#define BANK_1_CONTROL_VALUE SA11X0_STATIC_ROM_TYPE_FLASH | \ + SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS | \ + SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_RECOVERY(0x7) +#define STATIC_CONTROL_0_VALUE (SA11X0_STATIC_ROM_BANK_0(BANK_0_CONTROL_VALUE) | \ + SA11X0_STATIC_ROM_BANK_1(BANK_1_CONTROL_VALUE)) + +#define BANK_2_CONTROL_VALUE SA11X0_STATIC_ROM_TYPE_FLASH | \ + SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS | \ + SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_RECOVERY(0x7) +#define BANK_3_CONTROL_VALUE SA11X0_STATIC_ROM_TYPE_FLASH | \ + SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS | \ + SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F) | \ + SA11X0_STATIC_ROM_RECOVERY(0x7) +#define STATIC_CONTROL_1_VALUE (SA11X0_STATIC_ROM_BANK_2(BANK_2_CONTROL_VALUE) | \ + SA11X0_STATIC_ROM_BANK_3(BANK_3_CONTROL_VALUE)) + + .macro _init_MEM_INTERFACES + /* + * Initialize the DRAM Controller + */ + ldr r0, =SA11X0_DRAM_CONFIGURATION + ldr r1, =DRAM_CONFIG_VALUE + str r1, [r0] + + ldr r0, =SA11X0_DRAM0_CAS_0 + ldr r1, =DRAM_CAS0_WAVEFORM + str r1, [r0] + + ldr r0, =SA11X0_DRAM0_CAS_1 + ldr r1, =DRAM_CAS1_WAVEFORM + str r1, [r0] + + ldr r0, =SA11X0_DRAM0_CAS_2 + ldr r1, =DRAM_CAS2_WAVEFORM + str r1, [r0] + + ldr r0, =SA11X0_STATIC_CONTROL_0 + + /* + * Get the reset ROM setup + */ + ldr r1, [r0] + + /* + * Get the 16/32 bit setting to merge into the appropriate + * register values later on. + */ + and r1, r1, #SA11X0_STATIC_ROM_BUS_WIDTH_MASK + + /* + * MSC0 - bank 0 ROM, bank 1 FLASH + */ + ldr r2, =STATIC_CONTROL_0_VALUE + orr r1, r1, r2 + + str r1, [r0] + + /* + * MSC1 - bank 2 SRAM, bank 3 REG + */ + ldr r0, =SA11X0_STATIC_CONTROL_1 + ldr r1, =STATIC_CONTROL_1_VALUE + str r1, [r0] + + /* + * Delay to let the DRAM warm up + */ + ldr r0, =0x200 +0: subs r0, r0, #1 + bne 0b + + .endm + + + .macro _platform_setup1 + nop + nop + nop + nop + nop + nop + nop + nop + nop + + _init_GPIO + _init_HEX_DISPLAY /* this is flaky sometimes */ + _init_HEX_DISPLAY /* so do it twice just in case */ + + _set_LEDS 0x15 + + _init_PERIPHERAL_PINS + _set_LEDS 0x13 + + _set_CLOCK_FREQUENCY + _enable_CLOCK_SWITCHING + _set_LEDS 0x12 + + _init_MEM_INTERFACES + _set_LEDS 0x11 + + // Set up a stack [for calling C code] + ldr r1,=__startup_stack + ldr r2,=SA11X0_RAM_BANK0_BASE + orr sp,r1,r2 + + // Create MMU tables + bl hal_mmu_init + + _set_LEDS 0x09 + // Enable MMU + ldr r2,=10f + ldr r1,=MMU_Control_Init|MMU_Control_M + mcr MMU_CP,0,r1,MMU_Control,c0 + mov pc,r2 /* Change address spaces */ + + nop + nop + nop +10: + _set_LEDS 0x08 + + .endm + +#else // STARTUP_ROM +#define PLATFORM_SETUP1 +#endif + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.h @@ -0,0 +1,10 @@ +// eCos memory layout - Tue Apr 04 20:19:06 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x800000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.ldi @@ -0,0 +1,24 @@ +// eCos memory layout - Tue Apr 04 20:19:06 2000 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x10000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 0 800000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 10000 10000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.h @@ -0,0 +1,16 @@ +// eCos memory layout - Tue Apr 04 20:19:06 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x800000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +extern char CYG_LABEL_NAME (_reserved) []; +#define CYGMEM_SECTION_reserved (CYG_LABEL_NAME (_reserved)) +#define CYGMEM_SECTION_reserved_SIZE (0x8000)
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.ldi @@ -0,0 +1,25 @@ +// eCos memory layout - Tue Apr 04 20:19:06 2000 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x800000 + rom : ORIGIN = 0x50000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/pkgconf/mlt_arm_sa11x0_sa1100mm_rom.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 0 800000 0 ! +region rom 50000000 40000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/include/sa1100mm.h @@ -0,0 +1,50 @@ +#ifndef CYGONCE_SA1100MM_H +#define CYGONCE_SA1100MM_H + +/*============================================================================= +// +// sa1100mm.h +// +// Platform specific support (registers, etc) +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dmoseley +// Contributors: dmoseley +// Date: 2000-10-25 +// Purpose: Intel SA1110/Multimedia platform specific support routines +// Description: +// Usage: #include <cyg/hal/sa1100mm.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +/*---------------------------------------------------------------------------*/ +/* end of sa1100mm.h */ +#endif /* CYGONCE_SA1100MM_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/sa11x0/sa1100mm/current/src/sa1100mm_misc.c @@ -0,0 +1,227 @@ +//========================================================================== +// +// sa1100mm_misc.c +// +// HAL misc board support code for StrongARM SA1110/Multimedia +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: hmt, dmoseley +// Travis C. Furrer <furrer@mit.edu> +// Date: 2000-05-21 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_sa11x0.h> // Hardware definitions +#include <cyg/hal/sa1100mm.h> // Platform specifics + +#include <cyg/infra/diag.h> // diag_printf + +// ------------------------------------------------------------------------- +// MMU initialization: +// +// These structures are laid down in memory to define the translation +// table. +// + +/* + * SA-1100 Translation Table Base Bit Masks */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * SA-1100 Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + int id : 2; + int imp : 2; + int domain : 4; + int sbz : 1; + int base_address : 23; +}; +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + int id : 2; + int b : 1; + int c : 1; + int imp : 1; + int domain : 4; + int sbz0 : 1; + int ap : 2; + int sbz1 : 8; + int base_address : 12; +}; +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + CYG_MACRO_START \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + CYG_MACRO_END + +#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \ + { int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--,j++,k++) \ + { \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +void +hal_mmu_init(void) +{ + unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_TYPE_MANAGER(0) | + ARM_ACCESS_TYPE_NO_ACCESS(1) | + ARM_ACCESS_TYPE_NO_ACCESS(2) | + ARM_ACCESS_TYPE_NO_ACCESS(3) | + ARM_ACCESS_TYPE_NO_ACCESS(4) | + ARM_ACCESS_TYPE_NO_ACCESS(5) | + ARM_ACCESS_TYPE_NO_ACCESS(6) | + ARM_ACCESS_TYPE_NO_ACCESS(7) | + ARM_ACCESS_TYPE_NO_ACCESS(8) | + ARM_ACCESS_TYPE_NO_ACCESS(9) | + ARM_ACCESS_TYPE_NO_ACCESS(10) | + ARM_ACCESS_TYPE_NO_ACCESS(11) | + ARM_ACCESS_TYPE_NO_ACCESS(12) | + ARM_ACCESS_TYPE_NO_ACCESS(13) | + ARM_ACCESS_TYPE_NO_ACCESS(14) | + ARM_ACCESS_TYPE_NO_ACCESS(15); + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x500, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */ + X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */ + X_ARM_MMU_SECTION(0x100, 0x100, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA-1101 Development Board Registers */ + X_ARM_MMU_SECTION(0x180, 0x180, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ct8020 DSP */ + X_ARM_MMU_SECTION(0x184, 0x184, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* XBusReg */ + X_ARM_MMU_SECTION(0x188, 0x188, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegA */ + X_ARM_MMU_SECTION(0x18C, 0x18C, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegB */ + X_ARM_MMU_SECTION(0x190, 0x190, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD A */ + X_ARM_MMU_SECTION(0x194, 0x194, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD B */ + X_ARM_MMU_SECTION(0x200, 0x200, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets */ + X_ARM_MMU_SECTION(0xC00, 0, 8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */ + X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */ + X_ARM_MMU_SECTION(0x800, 0x800, 1024, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */ + +} + +// +// Platform specific initialization +// + +void +plf_hardware_init(void) +{ +}
--- a/packages/hal/i386/arch/current/ChangeLog +++ b/packages/hal/i386/arch/current/ChangeLog @@ -1,3 +1,9 @@ +2000-11-01 Jonathan Larmour <jlarmour@redhat.com> + + * src/vectors.S (hal_pc_irq): Use correct register for ISR return value + when calling interrupt_end() + Thanks to Phil Hinton for reporting. + 2000-10-20 Jonathan Larmour <jlarmour@redhat.com> * src/vectors.S (_start): call constructors after initializing
--- a/packages/hal/i386/arch/current/src/vectors.S +++ b/packages/hal/i386/arch/current/src/vectors.S @@ -232,7 +232,7 @@ hal_pc_irq: movl (%ebx, %ecx, 4), %edx # regs is left from the push of ebp above; pushl %edx - pushl %eax + pushl %esi # the old eax was saved in esi before hal_intc_ack call interrupt_end addl $8, %esp #endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */
--- a/packages/hal/i386/linux/current/ChangeLog +++ b/packages/hal/i386/linux/current/ChangeLog @@ -1,3 +1,10 @@ +2000-11-02 Jonathan Larmour <jlarmour@redhat.com> + + * src/entry.c (_linux_entry): Extend memory using brk() syscall to + match memory layout + + * src/syscall-i386-linux-1.0.S: Add brk syscall + 2000-10-20 Jonathan Larmour <jlarmour@redhat.com> * include/pkgconf/mlt_i386_linux_ram.mlt:
--- a/packages/hal/i386/linux/current/src/entry.c +++ b/packages/hal/i386/linux/current/src/entry.c @@ -32,7 +32,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): proven -// Contributors:proven, jskov +// Contributors:proven, jskov, jlarmour // Date: 1999-01-06 // Purpose: Entry point for Linux synthetic target. // @@ -40,18 +40,29 @@ // //========================================================================= +#include <pkgconf/system.h> #include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include CYGHWR_MEMORY_LAYOUT_H externC void cyg_hal_isr_init( void ); externC void cyg_hal_invoke_constructors( void ); externC void cyg_start( void ); externC void cyg_hal_hardware_init( void ); +externC void *cyg_hal_sys_brk(void *newbrk); void _linux_entry( void ) { + void *oldbrk=NULL; + void *newbrk=(void *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); // Should get argc argv cyg_hal_hardware_init(); cyg_hal_isr_init(); + // unconditionally set memory regino to the size specified in the + // memory layout + oldbrk = cyg_hal_sys_brk(newbrk); + // should check + CYG_ASSERT( oldbrk>=newbrk, "brk() failed" ); cyg_hal_invoke_constructors(); cyg_start(); }
--- a/packages/hal/i386/linux/current/src/syscall-i386-linux-1.0.S +++ b/packages/hal/i386/linux/current/src/syscall-i386-linux-1.0.S @@ -583,3 +583,7 @@ SYSCALL5(_newselect) //========================================================================== // machdep_sys_fdatasync() SYSCALL1(fdatasync) + +//========================================================================== +// machdep_sys_brk() +SYSCALL1(brk)
--- a/packages/hal/i386/pc/current/ChangeLog +++ b/packages/hal/i386/pc/current/ChangeLog @@ -1,3 +1,8 @@ +2000-11-02 Fabrice Gautier <Fabrice_Gautier@sdesigns.com> + + * src/platform.inc (hal_cpu_init): Load image from floppy one + sector at a time to avoid "DMA access across 64k boundary" error. + 2000-10-20 Jonathan Larmour <jlarmour@redhat.com> * include/pkgconf/mlt_i386_pc_floppy.mlt:
--- a/packages/hal/i386/pc/current/include/platform.inc +++ b/packages/hal/i386/pc/current/include/platform.inc @@ -65,8 +65,7 @@ sectorsPerTrack = 18 bytesPerSector = 512 - bytesPerTrack = sectorsPerTrack * bytesPerSector - dptLength = 3 /* words. */ + esPerSector = 32 /* = 512/16 */ cld /* always count up. */ @@ -78,9 +77,9 @@ andl $0xF000, %eax movw %ax, %ss - /* Ask the BIOS for info about the amount of RAM available. We push these - onto the stack for later use. - */ + /* Ask the BIOS for info about the amount of RAM available. We push + * these onto the stack for later use. + */ xorl %eax, %eax movb $0x88, %ah /* Get the amount of extended memory. */ @@ -93,35 +92,63 @@ shl $10, %eax pushl %eax - - /* Read the rest of the image to _start. This code works by reading a track - at a time... + /* reset floppy */ + movb $0,%ah + movb $0,%dl + int $0x13 + jc _error + + /* Read the rest of the image to _start. This code works by reading + only one sector at a time to avoid "buffer cross 64k boundary" fatal + problem... This is slow but should work in almost all situations. + _start should be aligned on a 512 bytes boundary to be sure. */ - movl $_edata, %eax - movl $_start, %ebx /* Our destination address. */ - subl %ebx, %eax /* Number of bytes in the image. */ - movl $1, %ecx /* Track/sector to read from (starts at 1). */ + /* destination pointer es:bx */ + /* With correct alignement, bx should be 0 and es should be a multiple + * of 32. If not it may cause the "buffer cross 64k boundary" problem + * (cf above) + */ + movl $_start,%eax + movw %ax,%bx + andw $0xF,%bx + shrl $4,%eax + movw %ax, %es -0: - cmpl $0, %eax - jle 1f + /* initials head/track/sector */ + movw $0,%dx + movw $1,%cx + + xorl %edi,%edi + jmp _loadsector - pushl %eax /* Save the number of bytes we want. */ - pushl %ebx /* Save our current address. */ - pushl %ecx /* Save our disk location. */ +_nextsector: + addw $esPerSector, %di /* advance buffer pointer */ + shll $4,%edi + cmpl $_edata,%edi + jg _endload /* next sector ? */ + shrl $4,%edi + movw %di,%es + incb %cl + cmpb $sectorsPerTrack, %cl + jbe _loadsector /* next head ?*/ + movb $1, %cl + incb %dh + cmpb $1, %dh + je _loadsector /* next track ? */ + movb $0, %dh + incb %ch - /* Read in a track with head 0. */ - - movl %ebx, %eax /* Put our address into ES:BX. */ - shr $4, %eax - movw %ax, %es - andl $0xF, %ebx - movw $0, %dx /* Disk 0, head 0 */ - movb $0x02, %ah - movb $sectorsPerTrack, %al /* Read the entire track. */ - movb $1, %cl - int $0x13 /* CX points to our track/sector. */ +_loadsector: + + pushw %es + movw $0x0201, %ax + int $0x13 + popw %di + jc _error + + movw $(0x0E*256+'.'), %ax /* print a dot */ + int $0x10 /* So go ahead and resume execution at the real starting address. This only serves to move us quickly to the real starting location; and has @@ -129,52 +156,13 @@ 0: reading the first track, then we limit ourselves to reading images of 30k bytes max before overwriting ourselves at 0x7C00. */ - - ljmp $0, $2f - hlt - .align 4 -2: - - popl %ecx - popl %ebx - popl %eax - - /* Add our length to the address. */ - addl $bytesPerTrack, %ebx - subl $bytesPerTrack, %eax - - /* Maybe read in a track with head 1. */ - cmpl $0, %eax - jle 1f - - pushl %eax /* Save the number of bytes we want. */ - pushl %ebx /* Save our current address. */ - pushl %ecx + ljmp $0,$_nextsector - movl %ebx, %eax /* Put our address into ES:BX. */ - shr $4, %eax - movw %ax, %es - andl $0xF, %ebx - movw $0x0100, %dx /* Disk 0, head 1 */ - movb $0x02, %ah - movb $sectorsPerTrack, %al /* Read the entire track. */ - movb $1, %cl - int $0x13 /* CX points to our track/sector. */ - - popl %ecx - popl %ebx - popl %eax - - /* Add our length to the address. */ - addl $bytesPerTrack, %ebx - subl $bytesPerTrack, %eax - - /* Move to the next track. */ - addb $0x1, %ch - - jmp 0b - +_error: /* halt on error */ + cli + hlt + jmp _start /* Write the 0x55/0xAA signature at the end of the first block. Without this signature the BIOS won't consider this block to be bootable. @@ -184,10 +172,11 @@ 2: .byte 0x55 .byte 0xAA - +_endload: 1: - /* Lets be nice and wait for the diskette drive motor to go off before continuing. */ + /* Lets be nice and wait for the diskette drive motor to go off + * before continuing. */ movw $0x40, %ax movw %ax, %es @@ -250,7 +239,9 @@ gdtStart: .byte 0xCF .byte 0x00 - /* Selector 0x18 == shorter code: faults any code access 0xF0000000-0xFFFFFFFF. */ + /* Selector 0x18 == shorter code: faults any code + * access 0xF0000000-0xFFFFFFFF. + */ .word 0xFFFF .word 0x0000 .byte 0x00 @@ -292,8 +283,8 @@ 3: popfl /* Save the standard and extended memory lengths into some static variables... - I'm predicting that someone is going to break our way of passing a pointer - to this structure... may as well avoid that problem now. + I'm predicting that someone is going to break our way of passing a + pointer to this structure... may as well avoid that problem now. */ .data .align 4 @@ -312,7 +303,7 @@ pc_extended_memory_size: /* _pc_entry() takes a pointer to our startup array (which only has standard and extended memory sizes in it, on the stack). */ - movl %esp, %ebx /* They are the last parameters on the stack. */ + movl %esp, %ebx /* They are the last parameters on the stack. */ pushl %ebx #endif /* CYG_HAL_STARTUP_FLOPPY */ @@ -323,8 +314,9 @@ pc_extended_memory_size: vector 15. */ - /* Save the standard and extended memory lengths into some static variables... - */ + /* Save the standard and extended memory lengths into some static + * variables... + */ .data .align 4 .globl pc_standard_memory_size
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -54,6 +54,7 @@ 2000-09-01 Jonathan Larmour <jlarmour@ * include/mips-stub.h: Change vr4300 register sizes to use 32-bit target_register_t, and tell the generic stub to use sign extension. + Ditto for tx49 * include/hal_cache.h (_HAL_ASM_SET_MIPS_ISA): Don't use pasting when it doesn't result in a preprocessing token. Just use string concatenation. @@ -144,6 +145,10 @@ 2000-05-15 Jesper Skov <jskov@redhat.c * src/vectors.S: Allow warm-start to be treated like cold-start if platform requires it. +2000-05-11 Jesper Skov <jskov@redhat.com> + + * include/mips-stub.h: Added register size for TX49. + 2000-05-10 Jesper Skov <jskov@redhat.com> * include/arch.inc: Force assembler into MIPS3 mode before using
--- a/packages/hal/mips/arch/current/include/mips-stub.h +++ b/packages/hal/mips/arch/current/include/mips-stub.h @@ -62,6 +62,13 @@ extern "C" { typedef unsigned long target_register_t; // We need to sign-extend the registers so GDB doesn't get confused. #define CYGARC_SIGN_EXTEND_REGISTERS +#elif defined(CYGPKG_HAL_MIPS_TX49) + // Even though we are only working with 32 bit registers, GDB expects 64 bits + #define REGSIZE(X) 8 + typedef unsigned long target_register_t; + + // We need to sign-extend the registers so GDB doesn't get confused. + #define CYGARC_SIGN_EXTEND_REGISTERS #else #define REGSIZE(X) 4 typedef unsigned long target_register_t;
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/ChangeLog @@ -0,0 +1,320 @@ +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt: + Add heap1 section + + * include/pkgconf/mlt_mips_tx49_ref4955_ram.h: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.h: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi: + Regenerated + +2000-09-06 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: Flush cache after copying vectors. + + * src/plf_misc.c (hal_platform_init): Removed cache-enabling + code. This is now done earlier in the variant init code. + +2000-07-21 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: Moved vector copying code to + hal_mon_init so it comes after cache initialization. + +2000-06-30 Jesper Skov <jskov@redhat.com> + + * src/pc87338.c: calling i/f macro changes. + + * src/hal_diag.c: Fix warning. + + * cdl/hal_mips_tx49_ref4955.cdl: Endian options next to each + other. + + * include/platform.inc: Only define hal_memc_setup if it will have + a content - otherwise the assembler emits a (harmless) warning. + +2000-06-29 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Changed to match the below. + + * src/pc87338.c: Use per-channel data struct instead of crufty code. + +2000-06-28 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Cleanup. + +2000-06-26 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: + * src/pc87338.c: + * include/plf_intr.h: + Moved Ctrl-c handling to driver file. Added timeout and proper + channel changing services. + + * cdl/hal_mips_tx49_ref4955.cdl: Removed ROM_DEBUG_CHANNEL option. + +2000-06-21 Jonathan Larmour <jlarmour@redhat.co.uk> + + * misc/slow_cat.tcl: Fix quoting when invoking TCL interpreter + * misc/swap4.tcl: Likewise + +2000-06-21 Jesper Skov <jskov@redhat.com> + + * src/plf_stub.c: + * src/pc87338.c: [added] + * src/pc87338.inl: [deleted] + * src/hal_diag.c: + * include/plf_stub.h: + * include/hal_diag.h: + * cdl/hal_mips_tx49_ref4955.cdl: + Whenever a serial driver is included, use it to service both ports + via the vector table, both for diag and stub use. Configurations + which rely on the vector table then do not need any serial driver, + regardless of which port is configured for use. + +2000-06-15 Jesper Skov <jskov@redhat.com> + + * include/hal_diag.h: Only define HAL_PLF_DIAG functions when + required. + + * src/plf_misc.c: Comment fix. + + * src/plf_stub.c: Config option renamed. + + * src/hal_diag.c: + * include/hal_diag.h: + Use common HAL console wrappers for virtual vector diag. + + * cdl/hal_mips_tx49_ref4955.cdl: Added final console/debug comm + config options. Cleaned up USE_ROM_MONITOR option. + +2000-06-13 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c (hal_ctrlc_isr): Only return handled when the irq + was indeed handled. + + * cdl/hal_mips_tx49_ref4955.cdl: Added some virtual vector config + variables. + +2000-06-09 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Only use table diag if so configured. + +2000-06-08 Jesper Skov <jskov@redhat.com> + + * src/plf_stub.c: init code moved to common HAL. + + * src/plf_misc.c: Moved some code and init responsibilities to + common HAL. + + * src/hal_diag.c: Allow use of ROM interface for diag IO. + + * include/plf_stub.h (HAL_STUB_PLATFORM_RESET_ENTRY): defined + (mostly for testing, as the board has reset). + + * include/hal_diag.h: Use diag_init to allow for configuration. + + * cdl/hal_mips_tx49_ref4955.cdl: Tweaks for + CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT. + +2000-06-06 Jonathan Larmour <jlarmour@redhat.co.uk> + + * misc/slow_cat.tcl: Use more correct runes to restart with tclsh + * misc/swap4.tcl: likewise + +2000-05-30 Jesper Skov <jskov@redhat.com> + + * include/plf_intr.h: + Handle V320USC sources in mask/unmask/ack macros. + + * src/plf_misc.c: + * include/plf_intr.h: + Set VSC320 interrupt controller as per spec. + + * include/plf_stub.h (HAL_STUB_PLATFORM_RESET): Memory access to + reset board. + + * src/platform.S: + * src/plf_mk_defs.c: + Mask request bits with enable bits on VSC320. + +2000-05-26 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_mips_tx49_ref4955_rom.h: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.h: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt: + Updated MLT files. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: Set up thread debug ptr. + + * cdl/hal_mips_tx49_ref4955.cdl: Include thread support in stub. + +2000-05-24 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: Don't use k0/k1 in init code (not a + problem per se, but for consistency). + +2000-05-23 Jesper Skov <jskov@redhat.com> + + * src/plf_mk_defs.c: + * src/platform.S: + * include/plf_intr.h: + * include/platform.inc (hal_intc_translate): Use vectors 0-5 even + when chaining is enabled. + + * misc/slow_cat.tcl: Removed the regexp magic. gets handles the + conversion. + +2000-05-22 Jesper Skov <jskov@redhat.com> + + * misc/slow_cat.tcl: Comments and minor tweaks. + + * src/platform.S: + * include/platform.inc: + * src/plf_mk_defs.c: + * cdl/hal_mips_tx49_ref4955.cdl: + Use mk_defs definitions instead of magic constants. + + * cdl/hal_mips_tx49_ref4955.cdl: Generate swapped srec file. + + * src/pc87338.inl: + * src/hal_diag.c: + Cleanup. + +2000-05-18 Jesper Skov <jskov@redhat.com> + + * include/plf_io.h: Define endian-safe IO macros. + + * src/plf_stub.c: + * src/hal_diag.c: + Use specified ports. + + * cdl/hal_mips_tx49_ref4955.cdl: Change default endianess to + big. Add options to control debug/diag ports. + + * src/platform.S: Set V320SC to big-endian mode when required. + +2000-05-17 Jesper Skov <jskov@redhat.com> + + * src/plf_stub.c: + * src/plf_misc.c: + * src/pc87338.inl: + Ctrl-c code uses local stub if available. + + * src/hal_diag.c: Fixed for running under stub. + + * include/plf_intr.h: Fix warnings. + + * include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi: + Leave gap for virtual table. + + * src/plf_misc.c: Support ctrl-c. + + * src/platform.S: Springboard code must use mask since sources are + set to interrupt when disabled. + + * src/pc87338.inl: Added interrupt definitions and interrupt init. + + * src/plf_stub.c: + * include/plf_stub.h: + Platform stub init of virtual vector table. + + * include/plf_intr.h: Added control macros. Only handles on-board + interrupt controller, not the V320USC one. + + * include/platform.inc: Use VSR/break springboard. + +2000-05-16 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: + Use FPU in 32 bit mode. + +2000-05-15 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_tx49_ref4955.cdl: Require warm-starts to be treated + like cold-starts. + + * src/plf_stub.c: + * include/plf_stub.h: + * include/plf_io.h: + * include/hal_diag.h: + Cleanup. + + * src/platform.S: Adjust springboard code for the three interrupt + controllers. + * include/plf_intr.h: Change vectors to match decoding. + * include/platform.inc: Cleanup. Enable FPU. + * cdl/hal_mips_tx49_ref4955.cdl: Cleanup. Fix incrementer rate. + +2000-05-12 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c (hal_platform_init): Initialize SuperIO chip. + + * src/platform.S: Added magic assembler operand. + + * src/hal_diag.c: Cleaned up. + + * include/platform.inc (hal_memc_init): Added configury. + + * cdl/hal_mips_tx49_ref4955.cdl: Default to GDB_stubs ROM monitor. + +2000-05-11 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi: + More space for vectors and VSR table [need to update .h&.ldi] + + * include/platform.inc: Move memory setup into a function. Fix + register typos. + + * include/platform.inc: Re-added the magic debug exception VSR + pointers. Copy VSRs to vector space [needs configury]. + + * include/pkgconf/mlt_mips_tx49_ref4955_ram.h: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.h: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi: + * include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt: + Updated for platform. + + * include/platform.inc: Some definitions added. + + * cdl/hal_mips_tx49_ref4955.cdl: don't move srec image. + +2000-05-10 Jesper Skov <jskov@redhat.com> + + * Cloned from jmr3904. Still stuff to clean out and stuff to add. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/cdl/hal_mips_tx49_ref4955.cdl @@ -0,0 +1,296 @@ +# ==================================================================== +# +# hal_mips_tx49_ref4955.cdl +# +# TX49/REF4955 board HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: bartv +# Contributors: +# Date: 2000-05-15 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_MIPS_TX49_REF4955 { + display "REF4955 evaluation board" + parent CYGPKG_HAL_MIPS + requires CYGPKG_HAL_MIPS_TX49 + define_header hal_mips_tx49_ref4955.h + include_dir cyg/hal + description " + The REF4955 HAL package should be used when targetting the + actual hardware." + + compile hal_diag.c platform.S plf_misc.c plf_stub.c pc87338.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mips_tx49.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_tx49_ref4955.h>" + + puts $::cdl_header "#define CYGHWR_HAL_MIPS_WARMSTART_COLDSTART" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the REF4955 board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. RAM + bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap typically + requires that the eCos application be blown into EPROMs or + equivalent technology." + } + + cdl_option CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN { + display "Board endian mode" + flavor data + legal_values {"big" "little"} + default_value {"big"} + no_define + description " + The TX4955 Reference Platform can be used in either big or + little endian mode. This option select which. The board + will also need to be reconfigured if this option changes." + } + cdl_option CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN_SET { + display "Communicate endian setting to variant HAL" + active_if {CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN == "big"} + calculated 1 + implements CYGINT_HAL_MIPS_MSBFIRST + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The REF4955 board has two separate serial ports. This option + chooses which of these ports will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The REF4955 board has two separate serial ports. This option + chooses which of these ports will be used for diagnostic output." + } + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + <PREFIX>/include/cyg/hal/plf_defs.inc : <PACKAGE>/src/plf_mk_defs.c + $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,plf_defs.tmp -o plf_mk_defs.tmp -S $< + fgrep .equ plf_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 plf_defs.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm plf_defs.tmp plf_mk_defs.tmp + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated { 660000 } + description " + The count and compare registers of the TX49 are used + to drive the eCos kernel RTC. The count register + increments at 66MHz on the REF4955." + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "mips-tx49-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-mips2 -EB -mabi=eabi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-mips2 -EL -mabi=eabi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-g -mips2 -EB -mabi=eabi -nostdlib -Wl,--gc-sections -Wl,-static" : "-g -mips2 -EL -mabi=eabi -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + SREC data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) --strip-unneeded -O srec $< pre-swap.srec + $(OBJCOPY) --strip-unneeded --change-addresses 0x40400000 $< be-swap.img + $(OBJCOPY) -O binary be-swap.img be-swap.bin + $(REPOSITORY)/$(PACKAGE)/misc/swap4.tcl be-swap.bin be.bin + $(OBJCOPY) --change-address 0xbfc00000 -I binary -O srec be.bin $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "mips_tx49_ref4955_ram" : \ + "mips_tx49_ref4955_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_tx49_ref4955_ram.ldi>" : \ + "<pkgconf/mlt_mips_tx49_ref4955_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_tx49_ref4955_ram.h>" : \ + "<pkgconf/mlt_mips_tx49_ref4955_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for GDB stubs. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + \"GDB_stubs\" provides support when GDB stubs are + included in the ROM monitor or boot ROM, allowing debugging + via GDB." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/hal_diag.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, nickg +// Date: 2000-05-15 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_ram.h @@ -0,0 +1,37 @@ +// eCos memory layout - Fri Oct 20 06:22:02 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x80000000) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_for_rom) []; +#endif +#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom)) +#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x7c00) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x84000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi @@ -0,0 +1,43 @@ +// eCos memory layout - Fri Oct 20 06:22:02 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x80000000, LENGTH = 0x4000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x7c00; + SECTION_rom_vectors (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt @@ -0,0 +1,29 @@ +version 0 +region ram 80000000 4000000 0 ! +section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table ! +section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom ! +section reserved_for_rom 7c00 10 0 0 0 1 0 1 rom_vectors rom_vectors ! +section rom_vectors 0 10 0 1 0 1 0 1 ROMISC ROMISC ! +section ROMISC 0 4 0 1 0 1 0 1 RELOCS RELOCS ! +section RELOCS 0 4 0 1 0 1 0 1 init init ! +section init 0 4 0 1 0 1 0 1 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 data1 data1 ! +section data1 0 8 0 1 0 1 0 1 eh_frame eh_frame ! +section eh_frame 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 ctors ctors ! +section ctors 0 4 0 1 0 1 0 1 dtors dtors ! +section dtors 0 4 0 1 0 1 0 1 devtab devtab ! +section devtab 0 4 0 1 0 1 0 1 got got ! +section got 0 4 0 1 0 1 0 1 dynamic dynamic ! +section dynamic 0 4 0 1 0 1 0 1 sdata sdata ! +section sdata 0 4 0 1 0 1 0 1 lit8 lit8 ! +section lit8 0 8 0 1 0 1 0 1 lit4 lit4 ! +section lit4 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_rom.h @@ -0,0 +1,35 @@ +// eCos memory layout - Fri Oct 20 06:22:57 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x80000000) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xbfc00000) +#define CYGMEM_REGION_rom_SIZE (0x1000000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x84000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi @@ -0,0 +1,43 @@ +// eCos memory layout - Fri Oct 20 06:22:57 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x80000000, LENGTH = 0x4000000 + rom : ORIGIN = 0xbfc00000, LENGTH = 0x1000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xbfc00000, LMA_EQ_VMA) + SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.rodata1)) + SECTION_data1 (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_eh_frame (ram, ALIGN (0x8), FOLLOWING (.data1)) + SECTION_gcc_except_table (ram, ALIGN (0x8), FOLLOWING (.eh_frame)) + SECTION_ctors (ram, ALIGN (0x8), FOLLOWING (.gcc_except_table)) + SECTION_dtors (ram, ALIGN (0x8), FOLLOWING (.ctors)) + SECTION_devtab (ram, ALIGN (0x8), FOLLOWING (.dtors)) + SECTION_got (ram, ALIGN (0x8), FOLLOWING (.devtab)) + SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got)) + SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic)) + SECTION_lit8 (ram, ALIGN (0x8), FOLLOWING (.sdata)) + SECTION_lit4 (ram, ALIGN (0x8), FOLLOWING (.lit8)) + SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt @@ -0,0 +1,29 @@ +version 0 +region ram 80000000 4000000 0 ! +region rom bfc00000 1000000 1 ! +section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table ! +section reserved_virtual_table 100 10 0 0 0 1 0 0 data ! +section data 0 10 1 1 0 1 0 1 data1 data1 ! +section data1 0 8 1 1 0 1 0 1 eh_frame eh_frame ! +section eh_frame 0 8 1 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 8 1 1 0 1 0 1 ctors ctors ! +section ctors 0 8 1 1 0 1 0 1 dtors dtors ! +section dtors 0 8 1 1 0 1 0 1 devtab devtab ! +section devtab 0 8 1 1 0 1 0 1 got got ! +section got 0 8 1 1 0 1 0 1 dynamic dynamic ! +section dynamic 0 8 1 1 0 1 0 1 sdata sdata ! +section sdata 0 8 1 1 0 1 0 1 lit8 lit8 ! +section lit8 0 8 1 1 0 1 0 1 lit4 lit4 ! +section lit4 0 8 1 1 0 1 0 0 sbss ! +section sbss 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 bfc00000 bfc00000 ROMISC ROMISC ! +section ROMISC 0 8 0 1 0 1 0 1 RELOCS RELOCS ! +section RELOCS 0 8 0 1 0 1 0 1 init init ! +section init 0 8 0 1 0 1 0 1 text text ! +section text 0 8 0 1 0 1 0 1 fini fini ! +section fini 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/platform.inc @@ -0,0 +1,234 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## REF4955/TX4955 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors:nickg,jskov +## Date: 2000-05-15 +## Purpose: REF4955/TX4955 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the REF4955/TX4955 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> +#include <cyg/hal/plf_defs.inc> + + +#------------------------------------------------------------------------------ +# Macro for copying vectors to RAM if necessary. +#if !defined(CYGSEM_HAL_USE_ROM_MONITOR) + + .macro hal_vectors_init + # If we don~t play nice with a ROM monitor, copy the required + # vectors into the proper location. + la t0,0x80000000 # dest addr + la t1,utlb_vector # source addr + la t3,utlb_vector_end # end dest addr +1: + lw v0,0(t1) # get word + addi t1,t1,4 + sw v0,0(t0) # write word + addi t0,t0,4 + bne t1,t3,1b + nop + + la t0,0x80000180 # dest addr + la t1,other_vector # source addr + la t3,other_vector_end # end dest addr +1: + lw v0,0(t1) # get word + addi t1,t1,4 + sw v0,0(t0) # write word + addi t0,t0,4 + bne t1,t3,1b + nop + + .set mips3 # Set ISA to MIPS 3 to allow cache insns + # Now clear the region in the caches + la t0,0x80000000 # dest addr + ori t1,t0,0x200 # source addr +1: cache 0x01,0(t0) # Flush word from data cache + cache 0x01,1(t0) + cache 0x01,2(t0) + cache 0x01,3(t0) + nop + cache 0x00,0(t0) # Invalidate icache for word + cache 0x00,1(t0) + cache 0x00,2(t0) + cache 0x00,3(t0) + nop + addi t0,t0,0x20 + bne t0,t1,1b + nop + .set mips0 # reset ISA to default + + .endm + +#else + + .macro hal_vectors_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MIPS_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + hal_vectors_init + # Set default exception VSR for all vectors + ori a0,zero,CYGNUM_HAL_VSR_COUNT + la a1,__default_exception_vsr + la a2,hal_vsr_table +1: sw a1,0(a2) + addi a2,a2,4 + addi a0,a0,-1 + bne a0,zero,1b + nop + + # Now set special VSRs + la a0,hal_vsr_table + # Set interrupt VSR + la a1,__default_interrupt_vsr + sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0) + # Add special handler on breakpoint vector to allow GDB and + # GCC to both use 'break' without conflicts. + la a1,__break_vsr_springboard + sw a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0) + # Set exception handler on special vectors + # FIXME: Should use proper definitions + la a1,__default_exception_vsr + sw a1,32*4(a0) # debug + sw a1,33*4(a0) # utlb + sw a1,34*4(a0) # nmi + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + hal_vectors_init + # Set interrupt VSR + la a0,hal_vsr_table + la a1,__default_interrupt_vsr + sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0) + .endm + +#else + + .macro hal_mon_init + hal_vectors_init + .endm + +#endif + +#define CYGPKG_HAL_MIPS_MON_DEFINED +#endif + +#------------------------------------------------------------------------------ + +#if !defined(CYG_HAL_STARTUP_RAM) + .macro hal_memc_init + // Only initialize the SDRAM controller when running in ROM + .extern hal_memc_setup + lar t0,hal_memc_setup + jalr t0 + nop + .endm +#define CYGPKG_HAL_MIPS_MEMC_DEFINED +#endif + +#------------------------------------------------------------------------------ +# Decide whether the VSR table is defined externally, or is to be defined +# here. + +## ISR tables are defined in platform.S +#define CYG_HAL_MIPS_ISR_TABLES_DEFINED + +## VSR table is at a fixed RAM address defined by the linker script +#define CYG_HAL_MIPS_VSR_TABLE_DEFINED + +##----------------------------------------------------------------------------- +## For chaining, use the calculated cause vector number. + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + .macro hal_intc_translate inum,vnum + move \vnum,\inum # Vector == interrupt number + .endm +#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED +#endif + +##----------------------------------------------------------------------------- +#ifdef CYG_STARTUP_ROM + +## Initial SR value for use in ROM: +## CP0 usable +## Vectors in RAM +## FP registers are 32 bit +## All hw ints disabled +#define INITIAL_SR 0x30000000 + +#else + +## Initial SR value for use standalone: +## CP0 usable +## Vectors to RAM +## FP registers are 32 bit +## All hw ints disabled +#define INITIAL_SR 0x30000000 + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/plf_cache.h @@ -0,0 +1,59 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/plf_intr.h @@ -0,0 +1,302 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// REF4955 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, nickg +// Date: 2000-05-09 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the REF4955 board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + + +// The first 6 correspond to the interrupt lines in the status/cause regs +#define CYGNUM_HAL_INTERRUPT_V320USC_INT0 0 +#define CYGNUM_HAL_INTERRUPT_V320USC_INT1 1 +#define CYGNUM_HAL_INTERRUPT_EXT 2 +#define CYGNUM_HAL_INTERRUPT_LAN 3 +#define CYGNUM_HAL_INTERRUPT_IO 4 +#define CYGNUM_HAL_INTERRUPT_COMPARE 5 + + +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) + +// This overlaps with LB_MBI below but it doesn't matter. It's only used +// by the HAL to access the special chaining entry in the ISR tables. +// All other attempted access to the ISR table will be redirected to this +// entry (curtsey of HAL_TRANSLATE_VECTOR). The other vector definitions +// are still valid, but only for enable/disable/config etc. (i.e., in +// chaining mode they have associated entries in the ISR tables). +#define CYGNUM_HAL_INTERRUPT_CHAINING 6 + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ + (_index_) = CYGNUM_HAL_INTERRUPT_CHAINING + +#endif + + +// The next 32 correspond to the interrupt lines in the V320USC's interrupt +// controller. These are decoded from the controller when an interrupt +// enters via CYGNUM_HAL_INTERRUPT_V320USC_INT0. +#define CYGNUM_HAL_INTERRUPT_INTC_V320USC_base 6 +#define CYGNUM_HAL_INTERRUPT_LB_MBI 6 +#define CYGNUM_HAL_INTERRUPT_PCI_MBI 7 +#define CYGNUM_HAL_INTERRUPT_RESERVED_2 8 +#define CYGNUM_HAL_INTERRUPT_I2O_OP_NE 9 +#define CYGNUM_HAL_INTERRUPT_I2O_IF_NF 10 +#define CYGNUM_HAL_INTERRUPT_I2O_IP_NE 11 +#define CYGNUM_HAL_INTERRUPT_I2O_OP_NF 12 +#define CYGNUM_HAL_INTERRUPT_I2O_OF_NE 13 +#define CYGNUM_HAL_INTERRUPT_RESERVED_8 14 +#define CYGNUM_HAL_INTERRUPT_RESERVED_9 15 +#define CYGNUM_HAL_INTERRUPT_RESERVED_10 16 +#define CYGNUM_HAL_INTERRUPT_RESERVED_11 17 +#define CYGNUM_HAL_INTERRUPT_TIMER0 18 +#define CYGNUM_HAL_INTERRUPT_TIMER1 19 +#define CYGNUM_HAL_INTERRUPT_RESERVED_14 20 +#define CYGNUM_HAL_INTERRUPT_ENUM 21 +#define CYGNUM_HAL_INTERRUPT_DMA0 22 +#define CYGNUM_HAL_INTERRUPT_DMA1 23 +#define CYGNUM_HAL_INTERRUPT_RESERVED_18 24 +#define CYGNUM_HAL_INTERRUPT_RESERVED_19 25 +#define CYGNUM_HAL_INTERRUPT_PWR_STATE 26 +#define CYGNUM_HAL_INTERRUPT_HBI 27 +#define CYGNUM_HAL_INTERRUPT_WDI 28 +#define CYGNUM_HAL_INTERRUPT_BWI 29 +#define CYGNUM_HAL_INTERRUPT_PSLAVE_PI 30 +#define CYGNUM_HAL_INTERRUPT_PMASTER_PI 31 +#define CYGNUM_HAL_INTERRUPT_PCI_T_ABORT 32 +#define CYGNUM_HAL_INTERRUPT_PCI_M_ABORT 33 +#define CYGNUM_HAL_INTERRUPT_DRAM_PI 34 +#define CYGNUM_HAL_INTERRUPT_RESERVED_29 35 +#define CYGNUM_HAL_INTERRUPT_DI0 36 +#define CYGNUM_HAL_INTERRUPT_DI1 37 + +// The next 6 correspond to the interrupt lines specific to the PCI +// connector (decoded from CYGNUM_HAL_INTERRUPT_V320USC_INT1) +#define CYGNUM_HAL_INTERRUPT_INTC_PCI_base 38 +#define CYGNUM_HAL_INTERRUPT_SERR 38 +#define CYGNUM_HAL_INTERRUPT_PERR 39 +#define CYGNUM_HAL_INTERRUPT_INTD 40 +#define CYGNUM_HAL_INTERRUPT_INTC 41 +#define CYGNUM_HAL_INTERRUPT_INTB 42 +#define CYGNUM_HAL_INTERRUPT_INTA 43 + +// The next 5 correspond to the interrupt lines specific to the REF4955 +// board (decoded from CYGNUM_HAL_INTERRUPT_IO) +#define CYGNUM_HAL_INTERRUPT_INTC_IO_base 44 +#define CYGNUM_HAL_INTERRUPT_SOFTWARE 44 +#define CYGNUM_HAL_INTERRUPT_INT_SWITCH 45 +#define CYGNUM_HAL_INTERRUPT_PARALLEL 46 +#define CYGNUM_HAL_INTERRUPT_DEBUG_UART 47 +#define CYGNUM_HAL_INTERRUPT_USER_UART 48 + + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_V320USC_INT0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_USER_UART +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Interrupt controler information + +// V320USC +#define CYGARC_REG_INT_STAT 0xb80000ec + +#define CYGARC_REG_INT_CFG0 0xb80000e0 +#define CYGARC_REG_INT_CFG1 0xb80000e4 +#define CYGARC_REG_INT_CFG2 0xb80000e8 +#define CYGARC_REG_INT_CFG3 0xb8000158 + +#define CYGARC_REG_INT_CFG_INT0 0x00000100 +#define CYGARC_REG_INT_CFG_INT1 0x00000200 +#define CYGARC_REG_INT_CFG_INT2 0x00000400 +#define CYGARC_REG_INT_CFG_INT3 0x00000800 + + +// FPGA +#define CYGARC_REG_PCI_STAT 0xb5300000 +#define CYGARC_REG_PCI_MASK 0xb5300030 + +#define CYGARC_REG_IO_STAT 0xb5300010 +#define CYGARC_REG_IO_MASK 0xb5300040 + + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + CYG_MACRO_START \ + if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ + } \ + else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \ + { \ + cyg_uint8 _mask_; \ + cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \ + HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \ + _mask_ &= ~(1<<_shift_); \ + HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \ + } \ + else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \ + { \ + cyg_uint8 _mask_; \ + cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \ + HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \ + _mask_ &= ~(1<<_shift_); \ + HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \ + } else { /* V320USC */ \ + cyg_uint32 _mask_; \ + cyg_uint32 _shift_ = \ + (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \ + HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \ + _mask_ &= !(1<<_shift_); \ + HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \ + } \ + CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "or $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ + } \ + else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \ + { \ + cyg_uint8 _mask_; \ + cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \ + HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \ + _mask_ |= (1<<_shift_); \ + HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \ + } \ + else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \ + { \ + cyg_uint8 _mask_; \ + cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \ + HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \ + _mask_ |= (1<<_shift_); \ + HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \ + } else { /* V320USC */ \ + cyg_uint32 _mask_; \ + cyg_uint32 _shift_ = \ + (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \ + HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \ + _mask_ |= (1<<_shift_); \ + HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \ + } \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + cyg_uint32 _srvector_ = _vector_; \ + if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) { \ + _srvector_ = CYGNUM_HAL_INTERRUPT_IO; \ + } else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) { \ + _srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT1; \ + } else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_V320USC_base) { \ + cyg_uint32 _mask_; \ + cyg_uint32 _shift_ = \ + (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \ + _mask_ = (1<<_shift_); \ + HAL_WRITE_UINT32(CYGARC_REG_INT_STAT, _mask_ ); \ + _srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT0; \ + } \ + asm volatile ( \ + "mfc0 $3,$13\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$13\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_srvector_) \ + : "$2", "$3" \ + ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/plf_io.h @@ -0,0 +1,191 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// HAL platform device IO register support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-05-18 +// Purpose: Define IO register support +// Description: The macros defined here provide the HAL APIs for handling +// device IO control registers. +// +// Usage: +// #include <cyg/hal/plf_io.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +// Little-endian version +#if (CYG_BYTEORDER == CYG_LSBFIRST) + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#else // Big-endian version + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = _r_[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + _r_[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#endif // Big-endian + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +// Little-endian version +#if (CYG_BYTEORDER == CYG_LSBFIRST) + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#else // Big-endian version + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = _r_[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + _r_[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#endif // Big-endian + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +// Note: same macros for little- and big-endian systems. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))) + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +#define HAL_IO_MACROS_DEFINED + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_IO_H +// End of plf_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/include/plf_stub.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-05-15 +// Purpose: Platform HAL stub support for MIPS/REF4955 boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/mips-stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +extern void hal_plf_stub_init( void ); +#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init(); + +//---------------------------------------------------------------------------- +// Reset. +#define CYGARC_REG_BOARD_RESET 0xb5400000 + +#define HAL_STUB_PLATFORM_RESET() HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,0) + +#define HAL_STUB_PLATFORM_RESET_ENTRY 0xbfc00000 + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/misc/slow_cat.tcl @@ -0,0 +1,25 @@ +#!/bin/sh +# these lines restart using the tcl shell \ + exec sh -c "if ( echo | tclsh ) 2>/dev/null ; then \ + exec tclsh \"${0}\" ${1+${*}} ; \ + elif ( echo | cygtclsh80 ) 2>/dev/null ; then \ + exec cygtclsh80 \"${0}\" ${1+${*}} ; \ + else \ + echo Could not find TCL interpreter ; \ + exit 1 ; \ + fi" + +# Can be used like this: +# Get flash ready for programming using Minicom or similar +# [o (Option menu), a (flAsh menu), b (Boot write)] +# Then execute the following +# slow_cat.tcl < install/bin/gdb_module.srec >/dev/ttyS0 + +# Delay lines by 1/10 of a second to allow the flash to recover The +# gets also strips off the broken (DOS) new-lines that objcopy is +# generating. The puts replace them with 0x0a which the firmware +# requires. +while { 0 <= [gets stdin line] } { + puts $line + after 100 +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/misc/swap4.tcl @@ -0,0 +1,30 @@ +#!/bin/sh +# these lines restart using the tcl shell \ + exec sh -c "if ( echo | tclsh ) 2>/dev/null ; then \ + exec tclsh \"${0}\" ${1+${*}} ; \ + elif ( echo | cygtclsh80 ) 2>/dev/null ; then \ + exec cygtclsh80 \"${0}\" ${1+${*}} ; \ + else \ + echo Could not find TCL interpreter ; \ + exit 1 ; \ + fi" + +proc filter { input_file output_file } { + set input_fd [open $input_file "r"] + set output_fd [open $output_file "w"] + + fconfigure $input_fd -translation binary + fconfigure $output_fd -translation binary + while { 1 } { + set data [read $input_fd 4] + if { [eof $input_fd] } { + break + } + binary scan $data "i" var + puts -nonewline $output_fd [binary format "I" $var] + } + close $input_fd + close $output_fd +} + +filter [lindex $argv 0] [lindex $argv 1]
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/hal_diag.c @@ -0,0 +1,209 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:nickg, jskov +// Date: 2000-05-10 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_misc.h> // Helper functions + +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/hal_if.h> // ROM calling interface + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // CYG_HAL_GDB_x_CRITICAL_IO_REGION +#endif + +externC void cyg_hal_plf_serial_init_channel(void* __ch_data); +externC void cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch); +externC cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data); + +//----------------------------------------------------------------------------- +// Hit the hardware directly. Either wrap in GDB O-packets, or write +// data raw to device. + +// Decide when to wrap text output as GDB O-packets +#if (CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL \ + == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL) + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) \ + || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + +#define CYG_DIAG_GDB + +#endif + +#endif + +//----------------------------------------------------------------------------- +// There are two serial ports. Hardwire to use one of them. +#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1 +#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2 + +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0) +#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC1) +#else +#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC2) +#endif + +static channel_data_t channel = { BASE, 0, 0}; + +#ifdef CYG_DIAG_GDB + +void +hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + cyg_hal_plf_serial_putc(&channel, '$'); + cyg_hal_plf_serial_putc(&channel, 'O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + cyg_hal_plf_serial_putc(&channel, h); + cyg_hal_plf_serial_putc(&channel, l); + csum += h; + csum += l; + } + cyg_hal_plf_serial_putc(&channel, '#'); + cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]); + cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]); + + c1 = cyg_hal_plf_serial_getc(&channel); + + if( c1 == '+' ) break; + } + + pos = 0; + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + } +} + +void +hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(&channel); +} + +#else // CYG_DIAG_GDB + +// Hit the hardware directly, no GDB translation + +void +hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(&channel); +} + +void +hal_diag_write_char(char c) +{ + cyg_hal_plf_serial_putc(&channel, c); +} + + +#endif + +// Reagardless whether encoding or not we alway initialize the device. + +void +hal_diag_init(void) +{ + // Init serial device + cyg_hal_plf_serial_init_channel((void*)&channel); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/pc87338.c @@ -0,0 +1,413 @@ +#ifndef CYGONCE_HAL_PC_SER_H +#define CYGONCE_HAL_PC_SER_H +//============================================================================= +// +// pc87338.c +// +// Simple driver for the serial controllers in the PC87338 SuperIO chip +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-06-20 +// Description: Simple driver for the PC87338 serial controllers +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +//----------------------------------------------------------------------------- +// Controller definitions. + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1 +#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2 + +//----------------------------------------------------------------------------- +// Serial registers (shared by all banks) +#define CYG_DEVICE_BSR (0x03) +#define CYG_DEVICE_LCR (0x03) + +#define CYG_DEVICE_BSR_BANK0 0x00 +#define CYG_DEVICE_BSR_BANK2 0xe0 + +#define CYG_DEVICE_LCR_LEN_5BIT 0x00 +#define CYG_DEVICE_LCR_LEN_6BIT 0x01 +#define CYG_DEVICE_LCR_LEN_7BIT 0x02 +#define CYG_DEVICE_LCR_LEN_8BIT 0x03 +#define CYG_DEVICE_LCR_STOP_1 0x00 +#define CYG_DEVICE_LCR_STOP_2 0x04 +#define CYG_DEVICE_LCR_PARITY_NONE 0x00 +#define CYG_DEVICE_LCR_PARITY_ODD 0x08 +#define CYG_DEVICE_LCR_PARITY_EVEN 0x18 +#define CYG_DEVICE_LCR_PARITY_LOGIC1 0x28 +#define CYG_DEVICE_LCR_PARITY_LOGIC0 0x38 +#define CYG_DEVICE_LCR_SBRK 0x40 + +// Bank 0 (control/status) +#define CYG_DEVICE_BK0_TXD (0x00) +#define CYG_DEVICE_BK0_RXD (0x00) +#define CYG_DEVICE_BK0_IER (0x01) +#define CYG_DEVICE_BK0_EIR (0x02) +#define CYG_DEVICE_BK0_FCR (0x02) +#define CYG_DEVICE_BK0_MCR (0x04) +#define CYG_DEVICE_BK0_LSR (0x05) +#define CYG_DEVICE_BK0_MSR (0x06) +#define CYG_DEVICE_BK0_SPR (0x07) +#define CYG_DEVICE_BK0_ASCR (0x07) + +#define CYG_DEVICE_BK0_LSR_RXDA 0x01 +#define CYG_DEVICE_BK0_LSR_OE 0x02 +#define CYG_DEVICE_BK0_LSR_PE 0x04 +#define CYG_DEVICE_BK0_LSR_FE 0x08 +#define CYG_DEVICE_BK0_LSR_BRK 0x10 +#define CYG_DEVICE_BK0_LSR_TXRDY 0x20 +#define CYG_DEVICE_BK0_LSR_TXEMP 0x40 +#define CYG_DEVICE_BK0_LSR_ER_INF 0x80 + +#define CYG_DEVICE_BK0_IER_TMR_IE 0x80 +#define CYG_DEVICE_BK0_IER_SFIF_IE 0x40 +#define CYG_DEVICE_BK0_IER_TXEMP_IE 0x20 +#define CYG_DEVICE_BK0_IER_DMA_IE 0x10 +#define CYG_DEVICE_BK0_IER_MS_IE 0x08 +#define CYG_DEVICE_BK0_IER_LS_IE 0x04 +#define CYG_DEVICE_BK0_IER_TXLDL_IE 0x02 +#define CYG_DEVICE_BK0_IER_RXHDL_IE 0x01 + +#define CYG_DEVICE_BK0_EIR_FEN1 0x80 +#define CYG_DEVICE_BK0_EIR_FEN0 0x40 +#define CYG_DEVICE_BK0_EIR_RXFT 0x08 +#define CYG_DEVICE_BK0_EIR_IPR1 0x04 +#define CYG_DEVICE_BK0_EIR_IPR0 0x02 +#define CYG_DEVICE_BK0_EIR_IPF 0x01 + +#define CYG_DEVICE_BK0_EIR_mask 0x07 +#define CYG_DEVICE_BK0_EIR_IRQ_ERR 0x06 +#define CYG_DEVICE_BK0_EIR_IRQ_RX 0x04 +#define CYG_DEVICE_BK0_EIR_IRQ_TX 0x02 + +#define CYG_DEVICE_BK0_MCR_ISEN 0x08 // interrupt signal enable + + +// Bank 2 (baud generator) +#define CYG_DEVICE_BK2_BGDL (0x00) +#define CYG_DEVICE_BK2_BGDH (0x01) +#define CYG_DEVICE_BK2_EXCR1 (0x02) +#define CYG_DEVICE_BK2_EXCR2 (0x04) +#define CYG_DEVICE_BK2_TXFLV (0x06) +#define CYG_DEVICE_BK2_RXFLV (0x07) + + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +//----------------------------------------------------------------------------- +// The minimal init, get and put functions. All by polling. + +void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 lcr; + + HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK0); + HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_IER, 0); + HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_MCR, CYG_DEVICE_BK0_MCR_ISEN); + + // Disable FIFOs + HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_FCR, 0); + + // 8-1-no parity. + HAL_WRITE_UINT8(base+CYG_DEVICE_LCR, + CYG_DEVICE_LCR_LEN_8BIT | CYG_DEVICE_LCR_STOP_1 | CYG_DEVICE_LCR_PARITY_NONE); + + // Set speed to 38400 (switch bank, remember old LCR setting) + HAL_READ_UINT8(base+CYG_DEVICE_LCR, lcr); + HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK2); + HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDL, 3); + HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDH, 0); + HAL_WRITE_UINT8(base+CYG_DEVICE_LCR, lcr); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 lsr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr); + } while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0); + + HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_TXD, __ch); + + // Hang around until the character has been safely sent. + do { + HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr); + } while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 lsr; + + HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr); + if ((lsr & CYG_DEVICE_BK0_LSR_RXDA) == 0) + return false; + + HAL_READ_UINT8 (base+CYG_DEVICE_BK0_RXD, *ch); + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +static const channel_data_t channels[2] = { + { (cyg_uint8*)CYG_DEVICE_SERIAL_SCC1, 1000, CYGNUM_HAL_INTERRUPT_DEBUG_UART}, + { (cyg_uint8*)CYG_DEVICE_SERIAL_SCC2, 1000, CYGNUM_HAL_INTERRUPT_USER_UART} +}; + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 ier; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); + ier |= CYG_DEVICE_BK0_IER_RXHDL_IE; + HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); + + HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); + ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE; + HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); + + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + cyg_uint8 eir, c; + channel_data_t* chan = (channel_data_t*)__ch_data; + CYGARC_HAL_SAVE_GP(); + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir); + + *__ctrlc = 0; + if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) { + + HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[0].isr_vector); + HAL_INTERRUPT_MASK(channels[1].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel((void*)&channels[0]); + cyg_hal_plf_serial_init_channel((void*)&channels[1]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Set channel 1 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +//----------------------------------------------------------------------------- +// end of pc87338.c +#endif // CYGONCE_HAL_PC_SER_INL
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/platform.S @@ -0,0 +1,338 @@ +##============================================================================= +## +## platform.S +## +## MIPS REF4955-TX4955 platform code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors:nickg, jskov +## Date: 2000-05-09 +## Purpose: MIPS REF4955-TX4955 platform code +## Description: Platform specific code for REF4955-TX4955 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + + .set noreorder + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> +#include <cyg/hal/plf_defs.inc> + +##----------------------------------------------------------------------------- +## ISR springboard. +## This routine decodes the interrupt from the various interrupt controllers +## and vectors to it. + + # On entry: + # a0 = MIPS status register interrupt number (1,2 or 3) + # a1 = ISR data value (= interrupt controller reg address) + # a2 = saved reg dump ptr + # s0 = saved reg dump ptr + # s1 = vector table offset + # s2 = interrupt number + # a3,v0,v1 etc available for use + + .text + +FUNC_START(hal_isr_springboard_pci) + lbu v0,0(a1) + nor v0,v0,v0 + la a1,CYGARC_REG_PCI_MASK + lbu a2,0(a1) + and v0,v0,a2 + addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_PCI_base + b hal_isr_springboard + nop +FUNC_END(hal_isr_springboard_pci) + +FUNC_START(hal_isr_springboard_io) + lbu v0,0(a1) + nor v0,v0,v0 + la a1,CYGARC_REG_IO_MASK + lbu a2,0(a1) + and v0,v0,a2 + addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_IO_base + b hal_isr_springboard + nop +FUNC_END(hal_isr_springboard_io) + +hal_isr_springboard_v320usc: + lw v0,0(a1) + la a1,CYGARC_REG_INT_CFG0 + lw v1,0(a1) + lw a2,4(a1) # CFG1 + or v1,v1,a2 + lw a2,8(a1) # CFG2 + or v1,v1,a2 + la a1,CYGARC_REG_INT_CFG3 + lw a2,0(a1) + or v1,v1,a2 + and v0,v0,v1 + addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_V320USC_base + +FUNC_START(hal_isr_springboard) + + # The following code implements an ls bit index algorithm similar + # to that in hal_lsbit_index() in hal_misc.c. + negu v1,v0 # v1 = -v0 + and v1,v1,v0 # v1 &= v0 [isolate ls bit] + sll v0,v1,16 # v0 = v1<<16 + subu v1,v0,v1 # v1 = v0 - v1 + sll a0,v1,6 # a0 = v1<<6 + addu v1,v1,a0 # v1 += a0 + sll a1,v1,4 # a1 = v1<<4 + addu v1,v1,a1 # v1 += a1 + la v0,hal_isr_springboard_table # v0 = table address + srl v1,v1,26 # v1 = v1>>26 + addu v1,v1,v0 # v1 = table entry address + lb a0,0(v1) # a0 = intc isr number + + add s2,a0,a2 # s2 = eCos isr number +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN +hal_isr_springboard_chaining: + # This serves as the __default_interrupt_isr entry-point in + # chaning mode, thus ensuring that all interrupts from + # vectors 0-5 eventually end up on the special CHAINING vector. + # (See the hal_interrupt_handlers table) + ori s1,zero,CYGNUM_HAL_INTERRUPT_CHAINING*4 # s1 = chaining isr ix +#else + sll s1,s2,2 # s1 = isr table index +#endif + + la v1,hal_interrupt_handlers + add v1,v1,s1 # v1 = isr handler address + lw v1,0(v1) # v1 = isr handler + + la a1,hal_interrupt_data + add a1,a1,s1 # a1 = address of data ptr + lw a1,0(a1) # a1 = data pointer + + move a0,s2 # pass interrupt number + + jr v1 # jump to handler, return is to + # default vsr already in ra + nop + +FUNC_END(hal_isr_springboard) + + +hal_isr_springboard_table: + .byte -1, 0, 1, 12, 2, 6, 0, 13 + .byte 3, 0, 7, 0, 0, 0, 0, 14 + .byte 10, 4, 0, 0, 8, 0, 0, 25 + .byte 0, 0, 0, 0, 0, 21, 27, 15 + .byte 31, 11, 5, 0, 0, 0, 0, 0 + .byte 9, 0, 0, 24, 0, 0, 20, 26 + .byte 30, 0, 0, 0, 0, 23, 0, 19 + .byte 29, 0, 22, 18, 28, 17, 16, 0 + + +##----------------------------------------------------------------------------- +## MEMC initialization. +## This also initializes the PCI bus and ISA bus bridge, so at the end of this +## we should have full access to all the memory and devices we need. +## This code is table driven, which is somewhat more compact that coding it all. +## Table entries consist of an address and a value to store in that address. +## A zero address terminates the table. Two special address values modify the +## behaviour: +## DELAY_LOOP loops for the number of iterations in the value field. +## WRITE16 treats the next 2 words as an address and value to be written +## with a 16 bit write cycle. + +#if !defined(CYG_HAL_STARTUP_RAM) + +#define DELAY_LOOP 1 +#define WRITE16 2 + +FUNC_START(hal_memc_setup) + + lar t0,hal_memc_setup_table + la t1,0xbfc00000 + la t2,DELAY_LOOP + la t3,WRITE16 +1: + lw a0,0(t0) # next table entry + lw a1,4(t0) # value to write + addiu t0,8 # go to next entry + beq a0,t2,2f # Check for delay + nop + beq a0,t3,3f # Check for 16 bit write + nop + beqz a0,9f # zero terminates loop + nop + sw a1,0(a0) # write it + lw zero,0(t1) # uncached read to flush write buffer + b 1b + nop +2: + lw zero,0(t1) # uncached read to flush write buffer + bnez a1,2b # count down by value in a1 + addiu a1,-1 # decrement in delay slot + b 1b # go back to loop + nop +3: + lw a3,0(t0) # get next word + addiu t0,4 # skip it + sh a3,0(a1) # store halfword + lw zero,0(t1) # uncached read to flush write buffer + b 1b + nop +9: + jr ra + nop + +FUNC_END(hal_memc_setup) + + +##----------------------------------------------------------------------------- +## The initialization table + +#define USC_LB_BUS_CFG 0xb800007c +#define USC_SDRAM_MA_CMD 0xb8000088 + +hal_memc_setup_table: + + .long DELAY_LOOP, 10000 # Wait for HW to settle + +#ifdef CYGPKG_HAL_MIPS_MSBFIRST + # V320SC : big-endian, max bus watch timer + .long USC_LB_BUS_CFG, 0x04010ff0 +#else + .long USC_LB_BUS_CFG, 0x04000ff0 +#endif + .long USC_SDRAM_MA_CMD, 0x00a70000 + .long USC_SDRAM_MA_CMD, 0x00e70220 + + .long 0, 0 + +#endif // !CYG_HAL_STARTUP_RAM + +##----------------------------------------------------------------------------- +## ISR tables. + + .extern hal_default_isr + + .data + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + .globl hal_interrupt_handlers +hal_interrupt_handlers: + # These first 6 vectors all go through a springboard for further + # interrupt controller vector decoding before ending up on the + # special chaining vector below. + .long hal_isr_springboard_v320usc + .long hal_isr_springboard_pci + .long hal_isr_springboard_chaining + .long hal_isr_springboard_chaining + .long hal_isr_springboard_io + .long hal_isr_springboard_chaining + + .long hal_default_isr # chaining vector + + .globl hal_interrupt_data +hal_interrupt_data: + .long CYGARC_REG_INT_STAT + .long CYGARC_REG_PCI_STAT + .long 0 + .long 0 + .long CYGARC_REG_IO_STAT + .long 0 + + .long 0 # chaining vector data + + .globl hal_interrupt_objects +hal_interrupt_objects: + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + + .long 0 # chaining vector object + + .globl cyg_hal_interrupt_level +cyg_hal_interrupt_level: + .rept CYGNUM_HAL_ISR_COUNT + .byte 0 + .endr + +#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_isr_springboard_v320usc + .long hal_isr_springboard_pci + .long hal_default_isr + .long hal_default_isr + .long hal_isr_springboard_io + .long hal_default_isr + + .rept CYGNUM_HAL_ISR_COUNT-6 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .long CYGARC_REG_INT_STAT + .long CYGARC_REG_PCI_STAT + .long 0 + .long 0 + .long CYGARC_REG_IO_STAT + .long 0 + + .rept CYGNUM_HAL_ISR_COUNT-6 + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + + .globl cyg_hal_interrupt_level +cyg_hal_interrupt_level: + .rept CYGNUM_HAL_ISR_COUNT + .byte 0 + .endr + +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + +##----------------------------------------------------------------------------- +## end of platform.S
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/plf_misc.c @@ -0,0 +1,114 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour, jskov +// Date: 2000-05-15 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/hal_if.h> // Calling interface definitions +#include <cyg/hal/hal_misc.h> // Helper functions + +//-------------------------------------------------------------------------- + +#define CYGARC_REG_SUPERIO_IREG 0xb4000398 +#define CYGARC_REG_SUPERIO_DREG 0xb4000399 + +#define CYGARC_REG_SUPERIO_FER 0x00 // function enable +#define CYGARC_REG_SUPERIO_FAR 0x01 // function address +#define CYGARC_REG_SUPERIO_PTR 0x02 // power and test +#define CYGARC_REG_SUPERIO_CLK 0x51 // clock controller + + +#define CYGARC_REG_SUPERIO_FER_PAR 0x01 +#define CYGARC_REG_SUPERIO_FER_SCC1 0x02 +#define CYGARC_REG_SUPERIO_FER_SCC2 0x04 + +#define CYGARC_REG_SUPERIO_CLK_14M 0x00 // 14MHz source +#define CYGARC_REG_SUPERIO_CLK_CME 0x04 // clock multiplier enabled + +#define CYGARC_REG_SUPERIO_PTR_PPEXT 0x80 // extended + + + + +static void write_super_io(cyg_uint8 offset, cyg_uint8 data) +{ + HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_IREG, offset); + HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data); + HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data); +} + +void hal_platform_init(void) +{ + hal_if_init(); + + // Configure the SuperIO chip + write_super_io(CYGARC_REG_SUPERIO_FER, + CYGARC_REG_SUPERIO_FER_SCC1|CYGARC_REG_SUPERIO_FER_SCC2); + write_super_io(CYGARC_REG_SUPERIO_FAR, 0x10); + write_super_io(CYGARC_REG_SUPERIO_CLK, + CYGARC_REG_SUPERIO_CLK_14M|CYGARC_REG_SUPERIO_CLK_CME); + + // Set up VSC320 interrupt controller. INT1 must merge INT2 and + // INT3 according to the platform specification. + HAL_WRITE_UINT32(CYGARC_REG_INT_CFG1, + CYGARC_REG_INT_CFG_INT2|CYGARC_REG_INT_CFG_INT3); + + // Unmask vectors which are entry points for interrupt controllers + HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT0); + HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT1); + HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_IO); +} + +//-------------------------------------------------------------------------- +// End of plf_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/plf_mk_defs.c @@ -0,0 +1,97 @@ +//========================================================================== +// +// plf_mk_defs.c +// +// HAL (platform) "make defs" program +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Date: 2000-05-11 +// Purpose: Platform dependent definition generator +// Description: This file contains code that can be compiled by the target +// compiler and used to generate machine specific definitions +// suitable for use in assembly code. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_cache.h> // HAL header +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +# include <cyg/kernel/instrmnt.h> +#endif + +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * This technique was first used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + */ + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + // Some other exception related definitions + DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT); + DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT); + DEFINE(CYGNUM_HAL_VECTOR_INTERRUPT, CYGNUM_HAL_VECTOR_INTERRUPT); + DEFINE(CYGNUM_HAL_VECTOR_BREAKPOINT, CYGNUM_HAL_VECTOR_BREAKPOINT); + + // Interrupt details + DEFINE(CYGNUM_HAL_INTERRUPT_INTC_V320USC_base, CYGNUM_HAL_INTERRUPT_INTC_V320USC_base); + DEFINE(CYGNUM_HAL_INTERRUPT_INTC_PCI_base, CYGNUM_HAL_INTERRUPT_INTC_PCI_base); + DEFINE(CYGNUM_HAL_INTERRUPT_INTC_IO_base, CYGNUM_HAL_INTERRUPT_INTC_IO_base); + DEFINE(CYGARC_REG_INT_STAT, CYGARC_REG_INT_STAT); + DEFINE(CYGARC_REG_PCI_STAT, CYGARC_REG_PCI_STAT); + DEFINE(CYGARC_REG_IO_STAT, CYGARC_REG_IO_STAT); + DEFINE(CYGARC_REG_PCI_MASK, CYGARC_REG_PCI_MASK); + DEFINE(CYGARC_REG_IO_MASK, CYGARC_REG_IO_MASK); + DEFINE(CYGARC_REG_INT_CFG0, CYGARC_REG_INT_CFG0); + DEFINE(CYGARC_REG_INT_CFG3, CYGARC_REG_INT_CFG3); +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) + DEFINE(CYGNUM_HAL_INTERRUPT_CHAINING, CYGNUM_HAL_INTERRUPT_CHAINING); +#endif + + return 0; +} + +//-------------------------------------------------------------------------- +// EOF plf_mk_defs.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/ref4955/current/src/plf_stub.c @@ -0,0 +1,61 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-05-15 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_io.h> // HAL IO macros + +//----------------------------------------------------------------------------- +// Stub init + +void +hal_plf_stub_init(void) +{ +} + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +// End of plf_stub.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/ChangeLog @@ -0,0 +1,117 @@ +2000-09-12 Jesper Skov <jskov@redhat.com> + + * include/variant.inc: Enable div-by-zero FPU exceptions. + +2000-09-06 Jesper Skov <jskov@redhat.com> + + * include/variant.inc: Enable the cache after clearing it. + +2000-09-01 Jonathan Larmour <jlarmour@redhat.com> + + * include/var_arch.h: tx49 GDB stubs now use 32-bits internally to + represent registers + +2000-08-31 Jonathan Larmour <jlarmour@redhat.com> + + * src/mips_tx49.ld: Use HAL table sections instead of devtab sections + +2000-06-06 Jesper Skov <jskov@redhat.com> + + * include/var_cache.h: Define HAL_ICACHE_INVALIDATE_ALL which + disables cache during operation. + +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_tx49.cdl: Use FPU double-LE layout in 32bit mode. + +2000-05-24 Jesper Skov <jskov@redhat.com> + + * src/mips_tx49.ld: Application contructors run after eCos + constructors. + +2000-05-22 Jesper Skov <jskov@redhat.com> + + * include/variant.inc: Flush all ways of cache on startup. + + * include/var_cache.h: + * cdl/hal_mips_tx49.cdl: Comment cleanups. + + * include/var_cache.h: Cleaned up. Use arch macros. + +2000-05-18 Jesper Skov <jskov@redhat.com> + + * src/mips_tx49.ld: Exclude libgcc constructors from CTOR list. + + * cdl/hal_mips_tx49.cdl: Set cache size to 32kB. + +2000-05-17 Jesper Skov <jskov@redhat.com> + + * src/mips_tx49.ld (hal_virtual_vector_table): Added. + +2000-05-16 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_tx49.cdl: Platform can select FPU mode. + +2000-05-15 Jesper Skov <jskov@redhat.com> + + * include/variant.inc: + * include/var_cache.h: + The cache-enable bits must be 0 to enable. Enable + caching/writeback for kseg0. + + * src/variant.S: + * include/var_arch.h: + Cleanup. + + * include/variant.inc: Copied in various stuff from VR4300 file. + + * include/var_cache.h: Cleanup. Added enabled macros. + + * cdl/hal_mips_tx49.cdl: Cleanup. Enable FPU. + +2000-05-11 Jesper Skov <jskov@redhat.com> + + * src/mips_tx49.ld: Workaround minor tool problem. + + * src/variant.S: Emptied. + + * src/mips_tx49.ld: Move vsr to avoid conflict with 'other' + exception entry having vectors in RAM. + + * include/var_arch.h: GDB expects 64 bit registers. + + * cdl/hal_mips_tx49.cdl: Add (disabled) 64 bit related options. + + * src/mips_tx49.ld: Workaround for linker buglet. + + * include/var_cache.h: Minor tweaks. + +2000-05-09 Jesper Skov <jskov@redhat.com> + + * Cloned from hal/mips/tx39 + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/cdl/hal_mips_tx49.cdl @@ -0,0 +1,142 @@ +# ==================================================================== +# +# hal_mips_tx49.cdl +# +# MIPS/TX49 variant architectural HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: bartv, nickg +# Contributors: +# Date: 2000-05-15 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_MIPS_TX49 { + display "TX49 variant" + parent CYGPKG_HAL_MIPS + hardware + include_dir cyg/hal + define_header hal_mips_tx49.h + description " + The TX49 architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + + cdl_component CYGPKG_HAL_MIPS_TX4955 { + display "TX4955 microprocessor" + default_value 1 + implements CYGINT_HAL_MIPS_VARIANT + description " + The TMPR4955F microprocessor. This is an embedded part that in + addition to the TX49 processor core has built in peripherals + such as memory controllers, DMA controllers, serial ports and + timers/counters." + + define_proc { + # Sizes are configurable (on the core). Should be configurable. + puts $::cdl_header "#define CYGHWR_HAL_DCACHE_SIZE 32768" + puts $::cdl_header "#define CYGHWR_HAL_ICACHE_SIZE 32768" + } + + cdl_option CYGHWR_HAL_MIPS_64BIT { + display "Variant 64 bit architecture support" + description " + While the TX49 is a 64bit CPU, only its 32bit mode is + currently supported in eCos." + calculated 0 + } + + # This is optional (on the core). Should be configurable. + cdl_option CYGHWR_HAL_MIPS_FPU { + display "Variant FPU support" + calculated 1 + } + + cdl_interface CYGINT_HAL_MIPS_FPU_64BIT { + display "Variant 64 bit FPU support interface" + } + + cdl_option CYGHWR_HAL_MIPS_FPU_64BIT { + display "Variant 64 bit FPU support" + calculated { CYGINT_HAL_MIPS_FPU_64BIT == 1 ? 1 : 0 } + } + + cdl_option CYGHWR_HAL_MIPS_FPU_32BIT { + display "Variant 32 bit FPU support" + calculated { CYGINT_HAL_MIPS_FPU_64BIT == 0 ? 1 : 0 } + } + + # FGRn+1 is most significant part of the FGRn&FGRn+1 pair of FPRn/2 + # This is true for BE mips2 mode at least. Not sure about fp64 mode + cdl_option CYGPKG_HAL_MIPS_DOUBLE_LSBFIRST { + active_if CYGHWR_HAL_MIPS_FPU_32BIT + calculated 1 + } + + cdl_interface CYGINT_HAL_MIPS_MSBFIRST { + no_define + display "CPU Variant big-endian interface" + } + + cdl_option CYGPKG_HAL_MIPS_MSBFIRST { + display "CPU Variant big-endian" + calculated { CYGINT_HAL_MIPS_MSBFIRST == 0 ? 0 : 1 } + } + + cdl_option CYGPKG_HAL_MIPS_LSBFIRST { + display "CPU Variant little-endian" + calculated { CYGINT_HAL_MIPS_MSBFIRST != 0 ? 0 : 1 } + } + } + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_mips.h>" + } + + compile var_misc.c variant.S + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/mips_tx49.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/mips_tx49.ld" } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/include/var_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//========================================================================== +// +// var_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov +// Date: 2000-05-15 +// Purpose: Define architecture abstractions +// Description: This file contains any extra or modified definitions for +// this variant of the architecture. +// Usage: #include <cyg/hal/var_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// ------------------------------------------------------------------------- +// Although the TX49 is really a 64 bit CPU, we have defined +// target_register_t elsewhere to be 32-bits because we only support +// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's +// not relevant for CYG_HAL_GDB_REG. + +#define CYG_HAL_GDB_REG CYG_WORD32 + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// End of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/include/var_cache.h @@ -0,0 +1,202 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H + +//============================================================================= +// +// var_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-05-09 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/imp_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/mips-regs.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= +// Toshiba TX4955 + +#ifdef CYGPKG_HAL_MIPS_TX4955 + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes +#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line +#define HAL_DCACHE_WAYS 4 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes +#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line +#define HAL_ICACHE_WAYS 4 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Cache controls + +// Register $16 is Config register (controls cache state) + +// Config Register fields +#define CYGARC_REG_CONFIG_ICE 0x00020000 // Instruction cache enable +#define CYGARC_REG_CONFIG_DCE 0x00010000 // Data cache enable + + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +// This uses a bit in the config register, which is TX49 specific. +#define HAL_DCACHE_ENABLE_DEFINED +#define HAL_DCACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp; \ + asm volatile ("mfc0 %0,$16;" \ + "and %0,%0,%1;" \ + "mtc0 %0,$16;" \ + : "=&r" (tmp) \ + : "r" (~CYGARC_REG_CONFIG_DCE) \ + ); \ + CYG_MACRO_END + +// Disable the data cache +#define HAL_DCACHE_DISABLE_DEFINED +#define HAL_DCACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp; \ + asm volatile ("mfc0 %0,$16;" \ + "or %0,%0,%1;" \ + "mtc0 %0,$16;" \ + : "=&r" (tmp) \ + : "r" (CYGARC_REG_CONFIG_DCE) \ + ); \ + CYG_MACRO_END + +#define HAL_DCACHE_IS_ENABLED_DEFINED +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + cyg_uint32 _cstate_; \ + asm volatile ( "mfc0 %0,$16\n" \ + : "=r"(_cstate_) \ + ); \ + if( _cstate_ & CYGARC_REG_CONFIG_DCE) \ + _state_ = 0; \ + else \ + _state_ = 1; \ + CYG_MACRO_END + +// Architecture HAL defines other operations + + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE_DEFINED +#define HAL_ICACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp; \ + asm volatile ("mfc0 %0,$16;" \ + "and %0,%0,%1;" \ + "mtc0 %0,$16;" \ + : "=&r" (tmp) \ + : "r" (~CYGARC_REG_CONFIG_ICE) \ + ); \ + CYG_MACRO_END + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE_DEFINED +#define HAL_ICACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp; \ + asm volatile ("mfc0 %0,$16;" \ + "or %0,%0,%1;" \ + "mtc0 %0,$16;" \ + : "=&r" (tmp) \ + : "r" (CYGARC_REG_CONFIG_ICE) \ + ); \ + CYG_MACRO_END + +#define HAL_ICACHE_IS_ENABLED_DEFINED +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + cyg_uint32 _cstate_; \ + asm volatile ( "mfc0 %0,$16\n" \ + : "=r"(_cstate_) \ + ); \ + if( _cstate_ & CYGARC_REG_CONFIG_ICE) \ + _state_ = 0; \ + else \ + _state_ = 1; \ + CYG_MACRO_END + +// TX49 cache instruction must not affect the line it executes out of, +// so disable instruction cache before invalidating it. +#define HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + _HAL_ASM_SET_MIPS_ISA(3); \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ + _HAL_ASM_SET_MIPS_ISA(0); \ + CYG_MACRO_END + +// Architecture HAL defines other operations + +#endif // CYGPKG_HAL_MIPS_TX4955 + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/include/var_intr.h @@ -0,0 +1,72 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// imp_intr.h +// +// TX49 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-05-09 +// Purpose: TX49 Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for variants of the TX49 MIPS +// architecture. +// +// Usage: +// #include <cyg/hal/var_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/plf_intr.h> + + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +// Vectors and handling of these are defined in platform HALs since the +// CPU itself does not have a builtin interrupt controller. + +//-------------------------------------------------------------------------- +// Clock control + +// This is handled by the default code + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/include/variant.inc @@ -0,0 +1,160 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## TX49 family assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors:nickg, jskov +## Date: 2000-05-10 +## Purpose: TX49 family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the TX49 CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/platform.inc> + +##----------------------------------------------------------------------------- +## Define CPU variant for architecture HAL. + +#define CYG_HAL_MIPS_R4900 + +#------------------------------------------------------------------------------ +# Set up initial value for config register. Sets endian mode and +# enable the cache on kseg0. + +#if defined(CYGPKG_HAL_MIPS_MSBFIRST) +# define INITIAL_CONFIG0 0x00008000 +#elif defined(CYGPKG_HAL_MIPS_LSBFIRST) +# define INITIAL_CONFIG0 0x00000000 +#else +# error MIPS endianness not set by configuration +#endif + +#------------------------------------------------------------------------------ +# Set up initial value for FPU FCR31 register. We set the FS bit to flush +# denormalized results to zero and enable div-by-zero exceptions. + +#ifndef CYG_HAL_MIPS_FCSR_INIT +#define CYG_HAL_MIPS_FCSR_INIT 0x01000400 +#endif + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED + + .macro hal_cache_init + + mfc0 v0,config0 # disable caches, but allow caching + nop # on kseg0 so cache macros can just + nop # fiddle ICE/IDE later on. + la v1,0xfffffff8 + and v0,v0,v1 + ori v0,v0,3 # kseg0 is writeback cache enabled + lui v1,3 + or v0,v0,v1 # set ICE&IDE (disables caches) + mtc0 v0,config0 + nop + nop + nop + + .set mips3 # Set ISA to MIPS 3 to allow cache insns + + # Now ensure the caches are invalidated. The caches are NOT cleared or + # invalidated on non-power-up resets and may come up in a random state + # on power-up. Hence they may contain stale or randomly bogus data. + # Here we use the index-store-tag cache operation to clear all the + # cache tags and states to zero. This will render them all invalid on + # the TX49. + + # D-cache: + la t0,0x80000000 + ori t1,t0,0x8000 +1: + mtc0 zero,$28 + mtc0 zero,$29 + cache 0x09,0(t0) + cache 0x09,1(t0) + cache 0x09,2(t0) + cache 0x09,3(t0) + addi t0,t0,0x20 + sub v0,t1,t0 + bgez v0,1b + nop # delay slot + + # I-cache: + la a0,0x80000000 + ori a1,a0,0x8000 +1: + mtc0 zero,$28 + mtc0 zero,$29 + cache 0x08,0(a0) + cache 0x08,1(a0) + cache 0x08,2(a0) + cache 0x08,3(a0) + addi a0,a0,0x20 + sub v0,a1,a0 + bgez v0,1b + nop # delay slot + + .set mips0 # reset ISA to default + + # Now enable caches + mfc0 v0,config0 + nop + nop + la v1,0xfffcffff # clear ICE&IDE (enables caches) + and v0,v0,v1 + mtc0 v0,config0 + nop + nop + nop + + .endm + +#define CYGPKG_HAL_MIPS_CACHE_DEFINED + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/src/mips_tx49.ld @@ -0,0 +1,359 @@ +//=========================================================================== +// +// MLT linker script for MIPS TX49 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +#include <pkgconf/system.h> + +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", + "elf32-littlemips") +/* The preprocessor defines mips, but we know we're mips :-) */ +#undef mips +OUTPUT_ARCH(mips:4900) + +STARTUP(vectors.o) +ENTRY(reset_vector) +#if defined(EXTRAS) && defined(CYGPKG_IO) +INPUT(extras.o) +#endif +GROUP(libtarget.a libgcc.a) + +/* FIXME: The MLT should pass in the required alignment since it must be + * the same as the VMA's alignment. As a result of this bug, all the REF4955 + * ROM mlt files have alignment 8, when some should have alignment 4 + * (902557-CR) + */ +#define ALIGN_LMA 8 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#if defined(CYG_HAL_STARTUP_RAM) + +/* this version for RAM startup */ +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { KEEP (*(.utlb_vector)) \ + . = ALIGN(0x80); KEEP(*(.other_vector)) \ + /* debug and reset vector not used in RAM version */ \ + KEEP(*(.debug_vector)) \ + KEEP (*(.reset_vector)) } \ + > _region_ + +#elif defined(CYG_HAL_STARTUP_ROM) + +/* this version for ROM startup */ +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { KEEP (*(.reset_vector)) \ + . = ALIGN(0x100); KEEP (*(.utlb_vector)) \ + . = ALIGN(0x80); KEEP(*(.other_vector)) \ + . = ALIGN(0x100); KEEP(*(.debug_vector)) } \ + > _region_ + +#endif /* ROM startup version of ROM vectors */ + +#define SECTION_ROMISC(_region_, _vma_, _lma_) \ + .interp _vma_ : _lma_ { *(.interp) } > _region_ \ + .hash : FOLLOWING(.interp) { *(.hash) } > _region_ \ + .dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \ + .dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \ + .gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \ + .gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \ + .gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \ + .plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_ + +#define SECTION_RELOCS(_region_, _vma_, _lma_) \ + .rel.text : \ + { \ + *(.rel.text) \ + *(.rel.text.*) \ + *(.rel.gnu.linkonce.t*) \ + } > _region_ \ + .rela.text : \ + { \ + *(.rela.text) \ + *(.rela.text.*) \ + *(.rela.gnu.linkonce.t*) \ + } > _region_ \ + .rel.data : \ + { \ + *(.rel.data) \ + *(.rel.data.*) \ + *(.rel.gnu.linkonce.d*) \ + } > _region_ \ + .rela.data : \ + { \ + *(.rela.data) \ + *(.rela.data.*) \ + *(.rela.gnu.linkonce.d*) \ + } > _region_ \ + .rel.rodata : \ + { \ + *(.rel.rodata) \ + *(.rel.rodata.*) \ + *(.rel.gnu.linkonce.r*) \ + } > _region_ \ + .rela.rodata : \ + { \ + *(.rela.rodata) \ + *(.rela.rodata.*) \ + *(.rela.gnu.linkonce.r*) \ + } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .rela.got : { *(.rela.got) } > _region_ \ + .rel.ctors : { *(.rel.ctors) } > _region_ \ + .rela.ctors : { *(.rela.ctors) } > _region_ \ + .rel.dtors : { *(.rel.dtors) } > _region_ \ + .rela.dtors : { *(.rela.dtors) } > _region_ \ + .rel.init : { *(.rel.init) } > _region_ \ + .rela.init : { *(.rela.init) } > _region_ \ + .rel.fini : { *(.rel.fini) } > _region_ \ + .rela.fini : { *(.rela.fini) } > _region_ \ + .rel.bss : { *(.rel.bss) } > _region_ \ + .rela.bss : { *(.rela.bss) } > _region_ \ + .rel.plt : { *(.rel.plt) } > _region_ \ + .rela.plt : { *(.rela.plt) } > _region_ \ + .rel.dyn : { *(.rel.dyn) } > _region_ + +#define SECTION_init(_region_, _vma_, _lma_) \ + .init _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; KEEP (*(.init)) \ + } > _region_ =0 + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { \ + _stext = .; _ftext = . ; \ + *(.text) \ + *(.text.*) \ + *(.stub) \ + *(.gnu.warning) \ + *(.gnu.linkonce.t*) \ + *(.mips16.fn.*) *(.mips16.call.*) \ + } > _region_ =0 \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; KEEP (*(.fini)) \ + } > _region_ =0 + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \ + } > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \ + } > _region_ + +#define SECTION_vsr_table(_region_, _vma_, _lma_) \ + .vsr_table _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.vsr_table) \ + } > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { \ + __ram_data_start = ABSOLUTE (.); _fdata = . ; \ + *(.data) *(.data.*) *(.gnu.linkonce.d*) \ + . = ALIGN (8); \ + SORT(CONSTRUCTORS) \ + } > _region_ \ + __rom_data_start = LOADADDR(.data); + +#define SECTION_data1(_region_, _vma_, _lma_) \ + .data1 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.data1) *(.data1.*) \ + } > _region_ + +#define SECTION_eh_frame(_region_, _vma_, _lma_) \ + .eh_frame _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.eh_frame) \ + } > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.gcc_except_table) \ + } > _region_ + + +/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__ + and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines. + However this doesn't work for old (99r1-era) toolchains, so + leave it for now. */ + +/* The KEEP(*_ctors.o(.ctors)) rule is included to prevent + constructors from libgcc.a from turning up in the image. + They are NULL anyway. */ + +#define SECTION_ctors(_region_, _vma_, _lma_) \ + .ctors _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP (*crtbegin.o(.ctors)) \ + KEEP (*_ctors.o(.ctors)) \ + __CTOR_LIST__ = .; \ + PROVIDE (__CTOR_LIST__ = .); \ + KEEP (*(.ctors)); \ + KEEP (*(SORT(.ctors.*))) \ + __CTOR_END__ = .; \ + PROVIDE (__CTOR_END__ = .); \ + } > _region_ + +#define SECTION_dtors(_region_, _vma_, _lma_) \ + .dtors _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP (*crtbegin.o(.dtors)) \ + __DTOR_LIST__ = .; \ + PROVIDE (__DTOR_LIST__ = .); \ + KEEP (*(SORT(.dtors.*))) \ + __DTOR_END__ = .; \ + KEEP (*(.dtors)); \ + PROVIDE (__DTOR_END__ = .); \ + } > _region_ + +#define SECTION_devtab(_region_, _vma_, _lma_) \ + .devtab _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP(*( SORT (.ecos.table.*))) ; \ + } > _region_ + +#define SECTION_got(_region_, _vma_, _lma_) \ + _gp = ALIGN(16) + 0x7ff0; \ + .got _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.got.plt) *(.got) \ + } > _region_ + +#define SECTION_dynamic(_region_, _vma_, _lma_) \ + .dynamic _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.dynamic) \ + } > _region_ + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + +#define SECTION_sdata(_region_, _vma_, _lma_) \ + .sdata _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnulinkonce.s*) \ + } > _region_ + +#define SECTION_lit8(_region_, _vma_, _lma_) \ + .lit8 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.lit8) \ + } > _region_ + +#define SECTION_lit4(_region_, _vma_, _lma_) \ + .lit4 : FOLLOWING(.lit8) \ + { \ + FORCE_OUTPUT; *(.lit4) \ + } > _region_ \ + __ram_data_end = .; _edata = . ; \ + PROVIDE (edata = .); + +#define SECTION_sbss(_region_, _vma_, _lma_) \ + __bss_start = .; _fbss = .; \ + .sbss _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.scommon) \ + } > _region_ + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { \ + *(.dynbss) *(.bss) *(.bss.*) *(COMMON) \ + } > _region_ \ + __bss_end = .; + +/* The /DISCARD/ section ensures that the output will not contain a + * .mdebug section as it confuses GDB. This is a workaround for CR 100804. + */ + +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ + /* Stabs debugging sections. */ \ + .stab 0 : { *(.stab) } \ + .stabstr 0 : { *(.stabstr) } \ + .stab.excl 0 : { *(.stab.excl) } \ + .stab.exclstr 0 : { *(.stab.exclstr) } \ + .stab.index 0 : { *(.stab.index) } \ + .stab.indexstr 0 : { *(.stab.indexstr) } \ + .comment 0 : { *(.comment) } \ + /* DWARF debug sections. \ + Symbols in the DWARF debugging sections are relative to \ + the beginning of the section so we begin them at 0. */ \ + /* DWARF 1 */ \ + .debug 0 : { *(.debug) } \ + .line 0 : { *(.line) } \ + /* GNU DWARF 1 extensions */ \ + .debug_srcinfo 0 : { *(.debug_srcinfo) } \ + .debug_sfnames 0 : { *(.debug_sfnames) } \ + /* DWARF 1.1 and DWARF 2 */ \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + /* DWARF 2 */ \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + /* SGI/MIPS DWARF 2 extensions */ \ + .debug_weaknames 0 : { *(.debug_weaknames) } \ + .debug_funcnames 0 : { *(.debug_funcnames) } \ + .debug_typenames 0 : { *(.debug_typenames) } \ + .debug_varnames 0 : { *(.debug_varnames) } \ + /* These must appear regardless of . */ \ + .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \ + .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \ + /DISCARD/ 0 : { *(.mdebug) } + +#include CYGHWR_MEMORY_LAYOUT_LDI + +// 0-0x200 reserved for vectors +hal_vsr_table = 0x80000200; +hal_virtual_vector_table = 0x80000300;
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/src/var_misc.c @@ -0,0 +1,66 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_intr.h> + +/*------------------------------------------------------------------------*/ +// Array which stores the configured priority levels for the configured +// interrupts. + +volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + +/*------------------------------------------------------------------------*/ + +void hal_variant_init(void) +{ +} + +/*------------------------------------------------------------------------*/ +/* End of var_misc.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx49/current/src/variant.S @@ -0,0 +1,48 @@ +##============================================================================= +## +## variant.S +## +## MIPS REF4955/TX4955 variant code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors:nickg +## Date: 2000-05-15 +## Purpose: MIPS REF4955/TX4955 variant code +## Description: Variant specific code for REF4955 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +# Nothing at the moment. + +##----------------------------------------------------------------------------- +## end of variant.S +
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,9 @@ +2000-10-31 Jonathan Larmour <jlarmour@redhat.com> + + * src/powerpc.ld: Use .sdata.* rather than .sdata* so that .sdata2 + doesn't get matched so that the linker script symbols are still valid. + Ditto for .sbss*. + 2000-10-24 Jonathan Larmour <jlarmour@redhat.com> * src/powerpc.ld: Match multiple sections where relevant (.bss*,
--- a/packages/hal/powerpc/arch/current/src/powerpc.ld +++ b/packages/hal/powerpc/arch/current/src/powerpc.ld @@ -111,7 +111,7 @@ GROUP(libtarget.a libgcc.a) /* We want the small data sections together, so single-instruction */ \ /* offsets can access them all, and initialized data all before */ \ /* uninitialized, so we can shorten the on-disk segment size. */ \ - __SDATA_START__ = ABSOLUTE(.); *(.sdata*) \ + __SDATA_START__ = ABSOLUTE(.); *(.sdata.*) \ __SDATA2_START__ = ABSOLUTE(.); *(.sdata2*) } \ > _region_ \ __rom_data_start = LOADADDR(.data); \ @@ -121,7 +121,7 @@ GROUP(libtarget.a libgcc.a) #define SECTION_sbss(_region_, _vma_, _lma_) \ .sbss _vma_ : _lma_ \ { __sbss_start = ABSOLUTE (.); \ - __SBSS_START__ = ABSOLUTE(.); *(.sbss*) __SBSS_END__ = ABSOLUTE(.); \ + __SBSS_START__ = ABSOLUTE(.); *(.sbss.*) __SBSS_END__ = ABSOLUTE(.); \ __SBSS2_START__ = ABSOLUTE(.); *(.sbss2*) __SBSS2_END__ = ABSOLUTE(.);\ *(.scommon*) \ __sbss_end = ABSOLUTE (.); } \
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--- a/packages/hal/powerpc/mbx/current/misc/redboot_ROM.cfg +++ b/packages/hal/powerpc/mbx/current/misc/redboot_ROM.cfg @@ -49,12 +49,6 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SU inferred_value 0 }; -cdl_component CYGBLD_BUILD_REDBOOT { - user_value 1 -}; - - - cdl_option CYGSEM_HAL_ROM_MONITOR { user_value 1 }; @@ -62,3 +56,9 @@ cdl_option CYGSEM_HAL_ROM_MONITOR { cdl_component CYG_HAL_STARTUP { user_value ROM }; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/ChangeLog @@ -0,0 +1,25 @@ +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/cdl/hal_powerpc_ppc40x.cdl @@ -0,0 +1,82 @@ +# ==================================================================== +# +# hal_powerpc_ppc40x.cdl +# +# PowerPC/PPC40x variant architectural HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: gthomas +# Date: 2000-08-27 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_POWERPC_PPC40x { + display "PowerPC 40x variant HAL" + parent CYGPKG_HAL_POWERPC + hardware + include_dir cyg/hal + define_header hal_powerpc_ppc40x.h + description " + The PowerPC 40x variant HAL package provides generic support + for this processor variant. It is also necessary to + select a specific target platform HAL package." + + # Note: This should be sub-variant specific to reduce memory use. + define_proc { + puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)" + puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)" + } + + cdl_component CYGPKG_HAL_POWERPC_PPC403 { + display "PowerPC 403 microprocessor" + default_value 1 + implements CYGINT_HAL_POWERPC_VARIANT + description " + The PowerPC 403 microprocessor." + + cdl_option CYGHWR_HAL_POWERPC_FPU { + display "Variant FPU support" + calculated 1 + } + + cdl_option CYGPKG_HAL_POWERPC_MSBFIRST { + display "CPU Variant big-endian" + calculated 1 + } + } + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_powerpc.h>" + } + + compile var_intr.c var_misc.c variant.S +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/include/var_cache.h @@ -0,0 +1,192 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-04-02 +// Purpose: Variant cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations on the PPC60x variant CPUs. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/ppc_regs.h> + +#include <cyg/hal/plf_cache.h> + + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache - this is implicit whenever the MMU is turned on +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + int _i_, _indx_; \ + _indx_ = 0; \ + for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \ + asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \ + _indx_ += HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/include/var_intr.h @@ -0,0 +1,54 @@ +#ifndef CYGONCE_VAR_INTR_H +#define CYGONCE_VAR_INTR_H +//============================================================================= +// +// var_intr.h +// +// Variant HAL interrupt and clock support +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov, jlarmour, hmt +// Date: 2000-04-02 +// Purpose: Variant interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock on the PPC60x variant CPUs. +// Usage: Is included via the architecture interrupt header: +// #include <cyg/hal/hal_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// No builtin interrupt controller in the PPC40x CPUs. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/include/var_regs.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H + +//========================================================================== +// +// var_regs.h +// +// PowerPC 40x variant CPU definitions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov,gthomas +// Date: 2000-08-27 +// Purpose: Provide PPC40x register definitions +// Description: Provide PPC40x register definitions +// The short difinitions (sans CYGARC_REG_) are exported only +// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined. +// Usage: Included via the acrhitecture register header: +// #include <cyg/hal/ppc_regs.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Cache +#define CYGARC_REG_HID0 1008 + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define HID0 CYGARC_REG_HID0 +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +// MMU control. +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#define EVPR 982 // Exception vector prefix +#define M_PID 945 // Process ID + +#define M_EPN_EPNMASK 0xfffff000 // effective page no mask +#define M_EPN_EV 0x00000040 // entry valid +#define M_EPN_SIZE(n) (n<<7) // entry size (0=1K, 1=4K, ... 7=16M) + +#define M_RPN_RPNMASK 0xfffff000 // real page no mask +#define M_RPN_EX 0x00000200 // execute enable +#define M_RPN_WR 0x00000100 // write enable +#define M_RPN_W 0x00000008 // write-through (when cache enabled) +#define M_RPN_I 0x00000004 // cache inhibited +#define M_RPN_M 0x00000002 // memory coherent (not implemented) +#define M_RPN_G 0x00000001 // guarded + +#define CYGARC_TLBWE(_id_, _hi_, _lo_) \ + asm volatile ("tlbwe %1,%0,0; tlbwe %2,%0,1" :: "r"(_id_), "r"(_hi_), "r"(_lo_)); + +#define CYGARC_TLBRE(_id_, _hi_, _lo_) \ + asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_)); + +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//----------------------------------------------------------------------------- +#endif // ifdef CYGONCE_HAL_VAR_REGS_H +// End of var_regs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/include/variant.inc @@ -0,0 +1,176 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## PPC40x family assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov, gthomas +## Date: 2000-08-27 +## Purpose: MPCxxx family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the PPC40x CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#undef CYG_MSR_COMMON +#define CYG_MSR_COMMON (MSR_ME | MSR_RI) + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- +## PPC40x defined vectors + + .macro hal_extra_vectors + .endm + +##----------------------------------------------------------------------------- +## PPC40x CPU initialization +## +## Initialize CPU to a post-reset state, ensuring the ground doesn''t +## shift under us while we try to set things up. + + .macro hal_cpu_init + # Set up MSR (disable MMU for now) + lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) + sync + mfmsr r4 + mtmsr r3 + sync + .endm + +##----------------------------------------------------------------------------- +## PPC40x monitor initialization + +#ifndef CYGPKG_HAL_PPC_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + .macro hal_mon_init +#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS + # If we are starting up from ROM and want vectors in RAM + # or we are starting in RAM and NOT using a ROM monitor, + # copy exception handler code to 0. + lwi r3,rom_vectors # r3 = rom start + lwi r4,0 # r4 = ram start + lwi r5,rom_vectors_end # r5 = rom end + cmplw r3,r5 # skip if no vectors + beq 2f + + subi r3,r3,4 + subi r4,r4,4 + subi r5,r5,4 +1: + lwzu r0,4(r3) # get word from ROM + stwu r0,4(r4) # store in RAM + cmplw r3,r5 # compare + blt 1b # loop if not yet done +2: + + # Ensure that the vectors will come from 0x0000 + lwi r4,0 + mtspr EVPR,r4 +#endif + + # Next initialize the VSR table. This happens whether the + # vectors were copied to RAM or not. + + # First fill with exception handlers + lwi r3,cyg_hal_default_exception_vsr + lwi r4,hal_vsr_table + subi r4,r4,4 + li r5,CYGNUM_HAL_VSR_COUNT +1: stwu r3,4(r4) + subi r5,r5,1 + cmpwi r5,0 + bne 1b + + # Then fill in the special vectors + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vectors, + # the rest are left to the ROM for now... + + .macro hal_mon_init + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + + +#else + + .macro hal_mon_init + + .endm + +#endif + + +#define CYGPKG_HAL_PPC_MON_DEFINED + +#endif // CYGPKG_HAL_PPC_MON_DEFINED + +##----------------------------------------------------------------------------- +## PPC40x exception state handling + .macro hal_variant_save regs + .endm + + .macro hal_variant_load regs + .endm + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +#define CYG_HAL_PPC_ISR_TABLES_DEFINED + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/src/var_intr.c @@ -0,0 +1,55 @@ +//========================================================================== +// +// var_intr.c +// +// PowerPC variant interrupt handlers +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-11 +// Purpose: PowerPC variant interrupt handlers +// Description: This file contains code to handle interrupt related issues +// on the PowerPC variant. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +externC void +hal_variant_IRQ_init(void) +{ + // No special init required for 40x series. +} + +// ------------------------------------------------------------------------- +// EOF var_intr.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/src/var_misc.c @@ -0,0 +1,136 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-02-04 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_mem.h> + +//-------------------------------------------------------------------------- +void hal_variant_init(void) +{ +} + + +//-------------------------------------------------------------------------- +// Variant specific idle thread action. +bool +hal_variant_idle_thread_action( cyg_uint32 count ) +{ + // Let architecture idle thread action run + return true; +} + +//--------------------------------------------------------------------------- +// Use MMU resources to map memory regions. +// Takes and returns an int used to ID the MMU resource to use. This ID +// is increased as resources are used and should be used for subsequent +// invocations. +// +// The PPC4xx CPUs do not have BATs. Fortunately we don't currently +// use the MMU, so we can simulate BATs by using the TLBs. +int +cyg_hal_map_memory (int id, CYG_ADDRESS virt, CYG_ADDRESS phys, + cyg_int32 size, cyg_uint8 flags) +{ + cyg_uint32 epn, rpn; + int sv, lv, max_tlbs; + + // There are 64 TLBs. + max_tlbs = 64; + + // Use the smallest "size" value which is big enough (round up) + for (sv = 0, lv = 0x400; sv < 8; sv++, lv <<= 2) { + if (lv >= size) break; + } + + // Note: the process ID comes from the PID register (always 0) + epn = (virt & M_EPN_EPNMASK) | M_EPN_EV | M_EPN_SIZE(sv); + rpn = (phys & M_RPN_RPNMASK) | M_RPN_EX | M_RPN_WR; + + if (flags & CYGARC_MEMDESC_CI) { + rpn |= M_RPN_I; + } + + if (flags & CYGARC_MEMDESC_GUARDED) + rpn |= M_RPN_G; + + CYGARC_TLBWE(id, epn, rpn); + id++; + + // Make caches default disabled when MMU is disabled. + + return id; +} + + +// Initialize MMU to a sane (NOP) state. +// +// Initialize TLBs with 0, Valid bits unset. +void +cyg_hal_clear_MMU (void) +{ + cyg_uint32 tlbhi = 0; + cyg_uint32 tlblo = 0; + int id, max_tlbs; + cyg_uint32 tlb[64][2]; + + // There are 64 TLBs. + max_tlbs = 64; + + CYGARC_MTSPR (M_PID, 0); + + for (id = 0; id < max_tlbs; id++) { + CYGARC_TLBRE(id, tlb[id][0], tlb[id][1]); + CYGARC_TLBWE(id, tlbhi, tlblo); + } + + // Make caches default disabled when MMU is disabled. +} + +//-------------------------------------------------------------------------- +// End of var_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ppc40x/current/src/variant.S @@ -0,0 +1,77 @@ +##============================================================================= +## +## variant.S +## +## PowerPC PPC40x variant code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov,gthomas +## Date: 2000-08-27 +## Purpose: PowerPC PPC40x variant code +## Description: Variant specific code for PowerPC 40x CPUs. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/variant.inc> + +#--------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + + .data + + .extern hal_default_decrementer_isr + .extern hal_default_isr + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_decrementer_isr + .rept CYGNUM_HAL_ISR_COUNT-1 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S +
--- a/packages/hal/sh/arch/current/ChangeLog +++ b/packages/hal/sh/arch/current/ChangeLog @@ -1,3 +1,26 @@ +2000-10-31 Jesper Skov <jskov@redhat.com> + + + * include/mod_7707a.h: Moved to SH3 HAL. + * include/mod_7708.h: Same. + * include/mod_7709a.h: Same. + * include/mod_7729.h: Same. + * include/sh3_sci.h: Same. + * include/sh3_scif.h: Same. + * src/sh3_sci.c: Same. + * src/sh3_scif.c: Same. + + * include/hal_cache.h: Moved SH3 code out to new SH3 HAL. + * cdl/hal_sh.cdl: Same. + * include/hal_intr.h: Same. + * include/sh_regs.h: Same. + * src/hal_misc.c: Same. + * src/hal_mk_defs.c: Same. + + * src/vectors.S: Changed to support SH4. Moved CPU post-reset init + code to variant HALs. Moved interrupt decoding to variant HAL + macros. Moved cache code to variant HALs. + 2000-10-24 Jesper Skov <jskov@redhat.com> * src/vectors.S (hal_hw_init): Added errata comment.
--- a/packages/hal/sh/arch/current/cdl/hal_sh.cdl +++ b/packages/hal/sh/arch/current/cdl/hal_sh.cdl @@ -52,13 +52,7 @@ cdl_package CYGPKG_HAL_SH { necessary to select a specific target platform HAL package." - cdl_interface CYGINT_HAL_SH_VARIANT { - display "Number of variant implementations in this configuration" - no_define - requires 1 == CYGINT_HAL_SH_VARIANT - } - - compile hal_misc.c context.S sh_stub.c sh3_sci.c sh3_scif.c + compile hal_misc.c context.S sh_stub.c # The "-o file" is a workaround for CR100958 - without it the # output file would end up in the source directory under CygWin. @@ -111,74 +105,12 @@ cdl_package CYGPKG_HAL_SH { description " CPU type and endian mode can be selected using these option." - cdl_option CYGPKG_HAL_SH_7707A { - display "SH 7707A microprocessor" - implements CYGINT_HAL_SH_VARIANT - implements CYGINT_HAL_SH_CPG_V2 - default_value 0 + cdl_interface CYGINT_HAL_SH_VARIANT { + display "Number of variant implementations in this configuration" no_define - define -file=system.h CYGPKG_HAL_SH_7707A - description " - The SH3 7707A microprocessor. This is an embedded part that in - addition to the SH3 processor core has built in peripherals - such as memory controllers, serial ports, LCD controller and - timers/counters." - define_proc { - puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7707a.h>" - } - } - - cdl_option CYGPKG_HAL_SH_7708 { - display "SH 7708 microprocessor" - implements CYGINT_HAL_SH_VARIANT - implements CYGINT_HAL_SH_CPG_V1 - default_value 0 - no_define - define -file=system.h CYGPKG_HAL_SH_7708 - description " - The SH3 7708 microprocessor. This is an embedded part that in - addition to the SH3 processor core has built in peripherals - such as memory controllers, serial ports and - timers/counters." - define_proc { - puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7708.h>" - } + requires 1 == CYGINT_HAL_SH_VARIANT } - - cdl_option CYGPKG_HAL_SH_7709A { - display "SH 7709A microprocessor" - implements CYGINT_HAL_SH_VARIANT - implements CYGINT_HAL_SH_CPG_V3 - default_value 0 - no_define - define -file=system.h CYGPKG_HAL_SH_7709A - description " - The SH3 7709A microprocessor. This is an embedded part that in - addition to the SH3 processor core has built in peripherals - such as memory controllers, DMA controllers, A/D and D/A - converters, serial ports and timers/counters." - define_proc { - puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7709a.h>" - } - } - - cdl_option CYGPKG_HAL_SH_7729 { - display "SH 7729 microprocessor" - implements CYGINT_HAL_SH_VARIANT - implements CYGINT_HAL_SH_CPG_V3 - default_value 0 - no_define - define -file=system.h CYGPKG_HAL_SH_7729 - description " - The SH3 7729 microprocessor. This is an embedded part that in - addition to the SH3 processor core has built in peripherals - such as memory controllers, serial ports, and timers/counters, - and a DSP engine." - define_proc { - puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7729.h>" - } - } - + cdl_option CYGHWR_HAL_SH_BIGENDIAN { display "Use big-endian mode" default_value 1 @@ -187,50 +119,6 @@ cdl_package CYGPKG_HAL_SH { } } - cdl_component CYGPKG_HAL_SH_INTERRUPT { - display "Interrupt controls" - flavor none - no_define - description " - Initial interrupt settings can be specified using these option." - - cdl_option CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS { - display "Handle spurious interrupts" - default_value 0 - description " - The SH3 may generate spurious interrupts with INTEVT = 0 - when changing the BL bit of the status register. Enabling - this option will cause such interrupts to be identified - very early in the interrupt handler and be ignored. Given - that the SH HAL uses the I-mask to control interrupts, - these spurious interrupts should not occur, and so there - should be no reason to include the special handling code." - } - - cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL { - display "Use IRQ0-3 pins as IRL input" - default_value 0 - description " - It is possible for the IRQ0-3 pins to be used as IRL - inputs by enabling this option." - } - - cdl_option CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS { - display "Enable IRLS interrupt pins" - default_value 0 - active_if CYGHWR_HAL_SH_IRQ_USE_IRQLVL - description " - IRLS interrupt pins must be specifically - activated. When they are, they will cause the same - type of interrupt as those caused by the IRL pins. If - IRL and IRLS pins signal an interrupt at the same - time, the highest level interrupt will be generated. - Only available on some cores, and probably share pins - with other interrupt sources (PINT) which cannot be - used in this configuration." - } - } - cdl_component CYGPKG_HAL_SH_CACHE { display "Cache controls" flavor none @@ -244,183 +132,6 @@ cdl_package CYGPKG_HAL_SH { description " Controls whether caches should be enabled on startup." } - - cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 { - display "Select cache mode set for P0/U0/P3 at startup" - default_value { "WRITE_BACK" } - legal_values { "WRITE_BACK" "WRITE_THROUGH" } - flavor data - description " - Controls what cache mode the cache should be put in at - startup for areas P0, U0 and P3. Write-back mode improves - performance by letting dirty data to be kept in the - cache for a period of time, allowing mutiple writes to - the same cache line to be written back to memory in - one memory transaction. In Write-through mode, each - individual write will cause a memory transaction." - } - - cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 { - display "Select cache mode set for P1 at startup" - default_value { "WRITE_BACK" } - legal_values { "WRITE_BACK" "WRITE_THROUGH" } - flavor data - description " - Controls what cache mode the cache should be put in at - startup for area P1. Write-back mode improves - performance by letting dirty data to be kept in the - cache for a period of time, allowing mutiple writes to - the same cache line to be written back to memory in - one memory transaction. In Write-through mode, each - individual write will cause a memory transaction." - } - } - - - cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS { - display "SH on-chip generic clock controls" - description " - The various clocks used by the system are controlled by - these options, some of which are derived from platform - settings." - flavor none - no_define - - cdl_interface CYGINT_HAL_SH_CPG_V1 { - display "Clock pulse generator type 1" - } - - cdl_interface CYGINT_HAL_SH_CPG_V2 { - display "Clock pulse generator type 2" - } - - cdl_interface CYGINT_HAL_SH_CPG_V3 { - display "Clock pulse generator type 3" - } - - - cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 { - display "TMU counter 0 prescaling" - description " - The peripheral clock is driving the counter used for - the real-time clock, prescaled by this factor." - flavor data - legal_values { 4 16 64 256 } - default_value 4 - } - - - cdl_option CYGHWR_HAL_SH_CLOCK_CKIO { - display "CKIO clock" - no_define - flavor data - # CKIO is either XTAL or PLL2 output - calculated { CYGINT_HAL_SH_CPG_V1 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) - ? (CYGHWR_HAL_SH_OOC_XTAL) - : CYGHWR_HAL_SH_PLL2_OUTPUT - ) - : CYGINT_HAL_SH_CPG_V2 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 2) - ? (CYGHWR_HAL_SH_OOC_XTAL) - : CYGHWR_HAL_SH_PLL2_OUTPUT - ) - : CYGINT_HAL_SH_CPG_V3 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) - ? (CYGHWR_HAL_SH_OOC_XTAL) - : CYGHWR_HAL_SH_PLL2_OUTPUT - ) - : 0 } - } - - cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT { - display "The clock output from PLL1" - no_define - flavor data - calculated { CYGHWR_HAL_SH_CLOCK_CKIO * CYGHWR_HAL_SH_OOC_PLL_1 } - } - - cdl_option CYGHWR_HAL_SH_PLL2_OUTPUT { - display "The clock output from PLL2" - no_define - flavor data - calculated { CYGINT_HAL_SH_CPG_V1 ? ( - (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) - ) - : CYGINT_HAL_SH_CPG_V2 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 5) - ? (CYGHWR_HAL_SH_OOC_XTAL / 2) - : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 6) - ? (14745600) - : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) - ? (11075600) - : (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) - ) - : CYGINT_HAL_SH_CPG_V3 ? ( - (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) - ) - : 0 } - } - - - cdl_option CYGHWR_HAL_SH_DIVIDER1_INPUT { - display "The clock input to divider 1" - no_define - flavor data - # DIV1 input is either PLL2 output or PLL1 output - calculated { (CYGHWR_HAL_SH_OOC_PLL_1 == 0) - ? CYGHWR_HAL_SH_PLL2_OUTPUT - : CYGHWR_HAL_SH_PLL1_OUTPUT } - } - - cdl_option CYGHWR_HAL_SH_DIVIDER2_INPUT { - display "The clock input to divider 2" - no_define - flavor data - # DIV2 input is either PLL2 output or PLL1 output - calculated { CYGINT_HAL_SH_CPG_V1 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4) - ? CYGHWR_HAL_SH_PLL2_OUTPUT - : CYGHWR_HAL_SH_PLL1_OUTPUT - ) - : CYGINT_HAL_SH_CPG_V2 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2) - ? CYGHWR_HAL_SH_PLL1_OUTPUT - : CYGHWR_HAL_SH_PLL2_OUTPUT - ) - : CYGINT_HAL_SH_CPG_V3 ? ( - (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4) - ? CYGHWR_HAL_SH_PLL2_OUTPUT - : CYGHWR_HAL_SH_PLL1_OUTPUT - ) - : 0 } - } - - cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED { - display "Processor clock speed (MHz)" - flavor data - calculated { CYGHWR_HAL_SH_DIVIDER1_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_1 } - description " - The core (CPU, cache and MMU) speed is computed from - the input clock speed and the divider 1 setting." - } - - cdl_option CYGHWR_HAL_SH_BOARD_SPEED { - display "Platform bus clock speed (MHz)" - flavor data - calculated { CYGHWR_HAL_SH_CLOCK_CKIO } - description " - The platform bus speed is CKIO." - } - - cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED { - display "Processor on-chip peripheral clock speed (MHz)" - flavor data - calculated { CYGHWR_HAL_SH_DIVIDER2_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_2 } - description " - The peripheral speed is computed from the input clock - speed and the divider 2 settings." - } } # Real-time clock/counter specifics
--- a/packages/hal/sh/arch/current/include/hal_cache.h +++ b/packages/hal/sh/arch/current/include/hal_cache.h @@ -50,246 +50,8 @@ //============================================================================= #include <pkgconf/system.h> -#include <pkgconf/hal.h> -#include <cyg/infra/cyg_type.h> -#include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros - -#include CYGBLD_HAL_CPU_MODULES_H // cache module specs - -#include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions - -//----------------------------------------------------------------------------- -// Cache dimensions - one unified cache - -#define HAL_CACHE_UNIFIED - -#define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE -#define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE -#define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS - -// Cache addressing information -#define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE -#define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP -#define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP - -// Writing this to a cache address entry forces a flush of the line if -// it is dirty. -#define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH - -#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Global control of cache - -// This is all handled in assembly (see vectors.S) due to a requirement about -// not fiddling the cache from cachable memory. - -externC void cyg_hal_cache_enable(void); -externC void cyg_hal_cache_disable(void); -externC void cyg_hal_cache_invalidate_all(void); -externC void cyg_hal_cache_sync(void); -externC void cyg_hal_cache_sync_region(cyg_haladdress base, - cyg_haladdrword len); -externC void cyg_hal_cache_write_mode(int mode); - -// Enable the cache -#define HAL_UCACHE_ENABLE() cyg_hal_cache_enable() - -// Disable the cache -#define HAL_UCACHE_DISABLE() cyg_hal_cache_disable() - -// Invalidate the entire cache -#define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all() - -// Synchronize the contents of the cache with memory. -#define HAL_UCACHE_SYNC() cyg_hal_cache_sync() - -// Query the state of the cache (does not affect the caching) -#define HAL_UCACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \ - (_state_) &= ~CYGARC_REG_CCR_CE; \ - CYG_MACRO_END - -// Set the cache refill burst size -//#define HAL_UCACHE_BURST_SIZE(_size_) - -// Set the cache write mode -#define HAL_UCACHE_WRITE_MODE( _mode_ ) \ - CYG_MACRO_START \ - cyg_uint32 _m_; \ - if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \ - _m_ = CYGARC_REG_CCR_WT; \ - else \ - _m_ = CYGARC_REG_CCR_CB; \ - cyg_hal_cache_write_mode(_m_); \ - CYG_MACRO_END - -#define HAL_UCACHE_WRITETHRU_MODE 0 -#define HAL_UCACHE_WRITEBACK_MODE 1 - -// This macro allows the client to specify separate modes for the two -// regions. -#define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_) - -// Load the contents of the given address range into the cache -// and then lock the cache so that it stays there. -//#define HAL_UCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_UCACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_UCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -#define HAL_UCACHE_FLUSH( _base_ , _size_ ) \ - cyg_hal_cache_sync_region(_base_, _size_) - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) - -// Write dirty cache lines to memory for the given address range. -//#define HAL_UCACHE_STORE( _base_ , _size_ ) - - -// Preread the given range into the cache with the intention of reading -// from it later. -//#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) -// Allocate and zero the cache lines associated with the given range. -//#define HAL_UCACHE_ZERO( _base_ , _size_ ) - - -//----------------------------------------------------------------------------- -// Data and instruction cache macros map onto the both-cache macros - -//----------------------------------------------------------------------------- -// Global control of data cache - -#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE -#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE -#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS -#define HAL_DCACHE_SETS HAL_UCACHE_SETS - -// Enable the data cache -#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() - -// Disable the data cache -#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() - -// Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() - -// Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -//#define HAL_DCACHE_WRITE_MODE( _mode_ ) - -//#define HAL_DCACHE_WRITETHRU_MODE 0 -//#define HAL_DCACHE_WRITEBACK_MODE 1 - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. -//#define HAL_DCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_DCACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_DCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Data cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -#define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ ) +#include <cyg/hal/var_cache.h> // get variant cache handling -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - -// Write dirty cache lines to memory for the given address range. -//#define HAL_DCACHE_STORE( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of reading -// from it later. -//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) - -// Allocate and zero the cache lines associated with the given range. -//#define HAL_DCACHE_ZERO( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE -#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE -#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS -#define HAL_ICACHE_SETS HAL_UCACHE_SETS - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() - -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() - - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() - -// Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. - -//#define HAL_ICACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_ICACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_ICACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - -//----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_CACHE_H // End of hal_cache.h
--- a/packages/hal/sh/arch/current/include/hal_intr.h +++ b/packages/hal/sh/arch/current/include/hal_intr.h @@ -51,13 +51,14 @@ //========================================================================== #include <pkgconf/hal.h> -#include CYGBLD_HAL_CPU_MODULES_H // INTC module selection + +#include <cyg/hal/var_intr.h> // More include statements below. First part of this file must be // usable for both assembly and C files, so only use defines here. //-------------------------------------------------------------------------- -// SH3 exception vectors. These correspond to VSRs and are the values +// SH exception vectors. These correspond to VSRs and are the values // to use for HAL_VSR_GET/SET // // Note that exceptions are decoded - there is a VSR slot for each exception @@ -72,27 +73,29 @@ #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE 6 // TLB prot violation s #define CYGNUM_HAL_VECTOR_DATA_ACCESS 7 // address error (load) #define CYGNUM_HAL_VECTOR_DATA_WRITE 8 // address error (store) -// define CYGNUM_HAL_VECTOR_RESERVED_9 9 -// define CYGNUM_HAL_VECTOR_RESERVED_10 10 +// RESERVED 9-10 #define CYGNUM_HAL_VECTOR_TRAP 11 // unconditional trap #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 12 // reserved instruction #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 13 // illegal instruction in delay slot -// define CYGNUM_HAL_VECTOR_RESERVED_14 14 +#define CYGNUM_HAL_VECTOR_NMI 14 // NMI #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 15 // user breakpoint -#define CYG_VECTOR_IS_INTERRUPT(v) \ - (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v)) - #define CYGNUM_HAL_VECTOR_INTERRUPT 16 // all interrupts +#ifndef CYG_VECTOR_IS_INTERRUPT +# define CYG_VECTOR_IS_INTERRUPT(v) (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v)) +#endif + #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON -#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT +#endif #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) -#define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1) - - +#ifndef CYGNUM_HAL_VSR_EXCEPTION_COUNT +# define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1) +#endif // The decoded interrupts. #define CYGNUM_HAL_INTERRUPT_NMI 0 @@ -128,74 +131,24 @@ #define CYGNUM_HAL_INTERRUPT_REF_RCMI 30 #define CYGNUM_HAL_INTERRUPT_REF_ROVI 31 -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI +#ifndef CYGNUM_HAL_ISR_MAX +# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI +#endif -//---------------------------------------------------------------------------- -// Additional vectors provided by INTC V2 +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI +#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1 ) -//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME -#define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32 -#define CYGNUM_HAL_INTERRUPT_HUDI_HUDI 33 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 34 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 35 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 36 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 37 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 38 -#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 39 -#define CYGNUM_HAL_INTERRUPT_RESERVED_6C0 40 -#define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41 -#define CYGNUM_HAL_INTERRUPT_PINT_PINT07 42 -#define CYGNUM_HAL_INTERRUPT_PINT_PINT8F 43 -#define CYGNUM_HAL_INTERRUPT_RESERVED_740 44 -#define CYGNUM_HAL_INTERRUPT_RESERVED_760 45 -#define CYGNUM_HAL_INTERRUPT_RESERVED_780 46 -#define CYGNUM_HAL_INTERRUPT_RESERVED_7A0 47 -#define CYGNUM_HAL_INTERRUPT_RESERVED_7C0 48 -#define CYGNUM_HAL_INTERRUPT_RESERVED_7E0 59 -#define CYGNUM_HAL_INTERRUPT_DMAC_DEI0 50 -#define CYGNUM_HAL_INTERRUPT_DMAC_DEI1 51 -#define CYGNUM_HAL_INTERRUPT_DMAC_DEI2 52 -#define CYGNUM_HAL_INTERRUPT_DMAC_DEI3 53 -#define CYGNUM_HAL_INTERRUPT_IRDA_ERI1 54 -#define CYGNUM_HAL_INTERRUPT_IRDA_RXI1 55 -#define CYGNUM_HAL_INTERRUPT_IRDA_BRI1 56 -#define CYGNUM_HAL_INTERRUPT_IRDA_TXI1 57 -#define CYGNUM_HAL_INTERRUPT_SCIF_ERI2 58 -#define CYGNUM_HAL_INTERRUPT_SCIF_RXI2 59 -#define CYGNUM_HAL_INTERRUPT_SCIF_BRI2 60 -#define CYGNUM_HAL_INTERRUPT_SCIF_TXI2 61 -#define CYGNUM_HAL_INTERRUPT_ADC_ADI 62 +// The vector used by the Real time clock +#ifndef CYGNUM_HAL_INTERRUPT_RTC +# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 +#endif -#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME - -#undef CYGNUM_HAL_ISR_MAX -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC_ADI - -#endif // CYGARC_SH_MOD_INTC_V2 - -//---------------------------------------------------------------------------- -// Additional vectors provided by INTC V3 - -//#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME -#define CYGNUM_HAL_INTERRUPT_LCDC_LCDI 63 -#define CYGNUM_HAL_INTERRUPT_PCC_PCC0 64 -#define CYGNUM_HAL_INTERRUPT_PCC_PCC1 65 - -#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME - -#undef CYGNUM_HAL_ISR_MAX -#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PCC_PCC1 - -#endif // CYGARC_SH_MOD_INTC_V3 - -// CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S. -#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI -#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) - +//-------------------------------------------------------------------------- // Exception vectors. These are the values used when passed out to an // external exception handler using cyg_hal_deliver_exception() -// The exception indexes are EXPEVT/0x20 +// The exception indexes are EXPEVT/0x20. Variants may define additional +// exception vectors. #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on #define CYGNUM_HAL_EXCEPTION_RESET 1 // reset @@ -206,23 +159,21 @@ #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE 6 // TLB prot violation s #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 7 // address error (load) #define CYGNUM_HAL_EXCEPTION_DATA_WRITE 8 // address error (store) -// define CYGNUM_HAL_EXCEPTION_RESERVED_9 9 -// define CYGNUM_HAL_EXCEPTION_RESERVED_10 10 #define CYGNUM_HAL_EXCEPTION_TRAP 11 // unconditional trap #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 12 // reserved instruction #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 13 // illegal instruction in delay slot -// define CYGNUM_HAL_EXCEPTION_RESERVED_14 14 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 15 // user breakpoint #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON -#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP + +#ifndef CYGNUM_HAL_EXCEPTION_MAX +# define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP +#endif + #define CYGNUM_HAL_EXCEPTION_COUNT \ ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) -// The vector used by the Real time clock -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 - #ifndef __ASSEMBLER__ #include <cyg/infra/cyg_type.h>
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/mod_7707a.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef CYGONCE_HAL_MOD_77xx_H -#define CYGONCE_HAL_MOD_77xx_H - -//============================================================================= -// -// mod_7707a.h -// -// List modules available on CPU -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-06-08 -// Purpose: Define modules (and versions) available on this CPU. -// Usage: Included from <cyg/hal/sh_regs.h> -// -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -//----------------------------------------------------------------------------- -// Modules provided by the CPU - -#define CYGARC_SH_MOD_BCN_V2 -#define CYGARC_SH_MOD_INTC_V2 -#define CYGARC_SH_MOD_INTC_V3 -#define CYGARC_SH_MOD_IRDA -#define CYGARC_SH_MOD_SCIF -#define CYGARC_SH_MOD_PFC -#define CYGARC_SH_MOD_UBC_V1 -#define CYGARC_SH_MOD_CPG_V2 - -//----------------------------------------------------------------------------- -// Extra details for Cache Module (CAC) - -// Cache dimenions - one unified cache -#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes -#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line -#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache - -// Cache addressing information -// way: bits 13 - 12 -// entry: bits 11 - 4 -#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 -#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 -#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 -// U : bit 1 -// V : bit 0 -// Writing zero to both forces a flush of the line if it is dirty. -#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 - -//----------------------------------------------------------------------------- -// Extra details for interrupt handling -#define CYGARC_SH_SOFTWARE_IP_UPDATE - -#endif // CYGONCE_HAL_MOD_77xx_H
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/mod_7708.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef CYGONCE_HAL_MOD_77xx_H -#define CYGONCE_HAL_MOD_77xx_H - -//============================================================================= -// -// mod_7708.h -// -// List modules available on CPU -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-03-16 -// Purpose: Define modules (and versions) available on this CPU. -// Usage: Included from <cyg/hal/sh_regs.h> -// -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -//----------------------------------------------------------------------------- -// Modules provided by the CPU - -#define CYGARC_SH_MOD_SCI_V2 -#define CYGARC_SH_MOD_UBC_V1 -#define CYGARC_SH_MOD_CPG_V1 - - -//----------------------------------------------------------------------------- -// Extra details for Cache Module (CAC) - -// Cache dimenions - one unified cache -#define CYGARC_SH_MOD_CAC_SIZE 8192 // Size of cache in bytes -#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line -#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache - -// Cache addressing information -// way: bits 12 - 11 -// entry: bits 10 - 4 -#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 -#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0002000 -#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 -// U : bit 1 -// V : bit 0 -// Writing zero to both forces a flush of the line if it is dirty. -#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 - -//----------------------------------------------------------------------------- -// Extra details for interrupt handling -#define CYGARC_SH_SOFTWARE_IP_UPDATE - -#endif // CYGONCE_HAL_MOD_77xx_H
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/mod_7709a.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef CYGONCE_HAL_MOD_77xx_H -#define CYGONCE_HAL_MOD_77xx_H - -//============================================================================= -// -// mod_7709a.h -// -// List modules available on CPU -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-03-16 -// Purpose: Define modules (and versions) available on this CPU. -// Usage: Included from <cyg/hal/sh_regs.h> -// -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -//----------------------------------------------------------------------------- -// Modules provided by the CPU - -#define CYGARC_SH_MOD_BCN_V2 -#define CYGARC_SH_MOD_INTC_V2 -#define CYGARC_SH_MOD_IRDA -#define CYGARC_SH_MOD_SCIF -#define CYGARC_SH_MOD_PFC -#define CYGARC_SH_MOD_UBC_V2 -#define CYGARC_SH_MOD_DMAC -#define CYGARC_SH_MOD_CPG_V3 - -//----------------------------------------------------------------------------- -// Extra details for Cache Module (CAC) - -// Cache dimenions - one unified cache -#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes -#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line -#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache - -// Cache addressing information -// way: bits 13 - 12 -// entry: bits 11 - 4 -#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 -#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 -#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 -// U : bit 1 -// V : bit 0 -// Writing zero to both forces a flush of the line if it is dirty. -#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 - -//----------------------------------------------------------------------------- -// Extra details for interrupt handling -#define CYGARC_SH_SOFTWARE_IP_UPDATE - -#endif // CYGONCE_HAL_MOD_77xx_H
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/mod_7729.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef CYGONCE_HAL_MOD_77xx_H -#define CYGONCE_HAL_MOD_77xx_H - -//============================================================================= -// -// mod_7729.h -// -// List modules available on CPU -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-08-29 -// Purpose: Define modules (and versions) available on this CPU. -// Usage: Included from <cyg/hal/sh_regs.h> -// -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -//----------------------------------------------------------------------------- -// Modules provided by the CPU - -#define CYGARC_SH_MOD_BCN_V2 -#define CYGARC_SH_MOD_INTC_V2 -#define CYGARC_SH_MOD_INTC_V3 -#define CYGARC_SH_MOD_PFC -#define CYGARC_SH_MOD_IRDA -#define CYGARC_SH_MOD_SCIF -#define CYGARC_SH_MOD_UBC_V3 -#define CYGARC_SH_MOD_CPG_V3 - -//----------------------------------------------------------------------------- -// Extra details for Cache Module (CAC) - -// Cache dimenions - one unified cache -#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes -#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line -#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache - -// Cache addressing information -// way: bits 13 - 12 -// entry: bits 11 - 4 -#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 -#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 -#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 -// U : bit 1 -// V : bit 0 -// Writing zero to both forces a flush of the line if it is dirty. -#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 - -//----------------------------------------------------------------------------- -// Extra details for interrupt handling -#define CYGARC_SH_SOFTWARE_IP_UPDATE - -#endif // CYGONCE_HAL_MOD_77xx_H
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/sh3_sci.h +++ /dev/null @@ -1,81 +0,0 @@ -//============================================================================= -// -// sh3_sci.h -// -// Simple driver for the SH Serial Communication Interface (SCI) -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 1999-05-17 -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGNUM_HAL_SH_SH3_SCI_PORTS - -//-------------------------------------------------------------------------- -// SCI register offsets -#ifdef CYGARC_SH_MOD_SCI_V2 -# define _REG_SCSPTR -0x4 // serial port register -#endif -#define _REG_SCSMR 0x0 // serial mode register -#define _REG_SCBRR 0x2 // bit rate register -#define _REG_SCSCR 0x4 // serial control register -#define _REG_SCTDR 0x6 // transmit data register -#define _REG_SCSSR 0x8 // serial status register -#define _REG_SCRDR 0xa // receive data register - -//-------------------------------------------------------------------------- - -typedef struct { - cyg_uint8* base; - cyg_int32 msec_timeout; - int isr_vector; -} channel_data_t; - -//-------------------------------------------------------------------------- - -#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) -// This one should only be used by old-stub compatibility code! -externC void cyg_hal_plf_sci_init_channel(const channel_data_t* chan); -#endif - -externC cyg_uint8 cyg_hal_plf_sci_getc(void* __ch_data); -externC void cyg_hal_plf_sci_putc(void* __ch_data, cyg_uint8 c); -externC void cyg_hal_plf_sci_init(int sci_index, int comm_index, - int rcv_vect, cyg_uint8* base); - - -#endif // CYGNUM_HAL_SH_SH3_SCI_PORTS -//----------------------------------------------------------------------------- -// end of sh3_sci.h
deleted file mode 100644 --- a/packages/hal/sh/arch/current/include/sh3_scif.h +++ /dev/null @@ -1,88 +0,0 @@ -//============================================================================= -// -// sh3_scif.h -// -// Simple driver for the SH3 Serial Communication Interface with FIFO -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-03-30 -// Description: Simple driver for the SH Serial Communication Interface -// The driver can be used for either the SCIF or the IRDA -// modules (the latter can act as the former). -// Clients of this file can configure the behavior with: -// CYGNUM_SCIF_PORTS: number of SCI ports -// -// Note: It should be possible to configure a channel to IRDA mode. -// Worry about that when some board needs it. -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGNUM_HAL_SH_SH3_SCIF_PORTS - -//-------------------------------------------------------------------------- -// SCIF register offsets -#define _REG_SCSMR 0x00 -#define _REG_SCBRR 0x02 -#define _REG_SCSCR 0x04 -#define _REG_SCFTDR 0x06 -#define _REG_SCSSR 0x08 -#define _REG_SCFRDR 0x0a -#define _REG_SCFCR 0x0c -#define _REG_SCFDR 0x0e - -//-------------------------------------------------------------------------- - -typedef struct { - cyg_uint8* base; - cyg_int32 msec_timeout; - int isr_vector; -} channel_data_t; - -//-------------------------------------------------------------------------- - -#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) -// This one should only be used by old-stub compatibility code! -externC void cyg_hal_plf_scif_init_channel(const channel_data_t* chan); -#endif - -externC cyg_uint8 cyg_hal_plf_scif_getc(void* __ch_data); -externC void cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c); -void cyg_hal_plf_scif_init(int scif_index, int comm_index, - int rcv_vect, cyg_uint8* base); - - -#endif // CYGNUM_HAL_SH_SH3_SCIF_PORTS -//----------------------------------------------------------------------------- -// end of sh3_scif.h
--- a/packages/hal/sh/arch/current/include/sh_regs.h +++ b/packages/hal/sh/arch/current/include/sh_regs.h @@ -40,7 +40,7 @@ // Usage: #include <cyg/hal/sh_regs.h> // Notes: // This file describes registers for on-core modules found in all -// the SH3 CPUs supported by the HAL. For each CPU is defined a +// the SH CPUs supported by the HAL. For each CPU is defined a // module specification file (mod_<CPU model number>.h) which lists // modules (and their version if applicable) included in that // particular CPU model. Note that the versioning is ad hoc; @@ -50,1026 +50,7 @@ // //============================================================================= -// Find out which modules are supported by the chosen CPU -// Note: At them moment only some modules are conditionalized (the ones -// not in the 7708). For consistency, all modules should be treated -// the same. #include <pkgconf/system.h> -#include CYGBLD_HAL_CPU_MODULES_H - -//========================================================================== -// CPU Definitions -//========================================================================== - -//-------------------------------------------------------------------------- -// Status register -#define CYGARC_REG_SR_MD 0x40000000 -#define CYGARC_REG_SR_RB 0x20000000 -#define CYGARC_REG_SR_BL 0x10000000 -#define CYGARC_REG_SR_M 0x00000200 -#define CYGARC_REG_SR_Q 0x00000100 -#define CYGARC_REG_SR_IMASK 0x000000f0 -#define CYGARC_REG_SR_I3 0x00000080 -#define CYGARC_REG_SR_I2 0x00000040 -#define CYGARC_REG_SR_I1 0x00000020 -#define CYGARC_REG_SR_I0 0x00000010 -#define CYGARC_REG_SR_S 0x00000002 -#define CYGARC_REG_SR_T 0x00000001 - - -//========================================================================== -// Memory Mapped Registers -//========================================================================== - -//++++++ Module MMU ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// MMU control registers -#define CYGARC_REG_MMUCR 0xffffffe0 - -#define CYGARC_REG_MMUCR_SV 0x00000100 -#define CYGARC_REG_MMUCR_RC_MASK 0x000000c0 -#define CYGARC_REG_MMUCR_TF 0x00000004 -#define CYGARC_REG_MMUCR_IX 0x00000002 -#define CYGARC_REG_MMUCR_AT 0x00000001 - -//++++++ Module CAC ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// Cache registers -#define CYGARC_REG_CCR 0xffffffec - -#define CYGARC_REG_CCR_RA 0x00000020 -#define CYGARC_REG_CCR_CF 0x00000008 -#define CYGARC_REG_CCR_CB 0x00000004 -#define CYGARC_REG_CCR_WT 0x00000002 -#define CYGARC_REG_CCR_CE 0x00000001 - -//-------------------------------------------------------------------------- -// Cache registers -#define CYGARC_REG_CCR 0xffffffec - -#define CYGARC_REG_CCR_RA 0x00000020 -#define CYGARC_REG_CCR_CF 0x00000008 -#define CYGARC_REG_CCR_CB 0x00000004 -#define CYGARC_REG_CCR_WT 0x00000002 -#define CYGARC_REG_CCR_CE 0x00000001 - - -//-------------------------------------------------------------------------- -// Address array access -// Address part (base/top/step specified in mod file) -#define CYGARC_REG_CACHE_ADDRESS_ADDRESS 0x00000008 // compare address - -// Data part -#define CYGARC_REG_CACHE_ADDRESS_TAG_Mask 0x1ffffc00 -#define CYGARC_REG_CACHE_ADDRESS_U 0x00000002 // updated (contains dirty data) -#define CYGARC_REG_CACHE_ADDRESS_V 0x00000001 // valid - - -//++++++ Module BSC ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// Bus State Control -#define CYGARC_REG_BCR1 0xffffff60 -#define CYGARC_REG_BCR2 0xffffff62 -#define CYGARC_REG_WCR1 0xffffff64 -#define CYGARC_REG_WCR2 0xffffff66 -#define CYGARC_REG_MCR 0xffffff68 -#define CYGARC_REG_DCR 0xffffff6a -#define CYGARC_REG_PCR 0xffffff6c -#define CYGARC_REG_RTCSR 0xffffff6e -#define CYGARC_REG_RTCNT 0xffffff70 -#define CYGARC_REG_RTCOR 0xffffff72 -#define CYGARC_REG_RFCR 0xffffff74 - -#ifdef CYGARC_SH_MOD_BCN_V2 -# define CYGARC_REG_BCR3 0xffffff7e -#endif - -#define CYGARC_REG_SDMR_AREA2_BASE 0xffffd000 -#define CYGARC_REG_SDMR_AREA3_BASE 0xffffe000 - -#define CYGARC_REG_BCR1_DRAMTP2 0x0010 -#define CYGARC_REG_BCR1_DRAMTP1 0x0008 -#define CYGARC_REG_BCR1_DRAMTP0 0x0004 - -// Bus widths for areas -#define CYGARC_REG_BCR2_A6_8 0x1000 -#define CYGARC_REG_BCR2_A6_16 0x2000 -#define CYGARC_REG_BCR2_A6_32 0x3000 -#define CYGARC_REG_BCR2_A5_8 0x0400 -#define CYGARC_REG_BCR2_A5_16 0x0800 -#define CYGARC_REG_BCR2_A5_32 0x0c00 -#define CYGARC_REG_BCR2_A4_8 0x0100 -#define CYGARC_REG_BCR2_A4_16 0x0200 -#define CYGARC_REG_BCR2_A4_32 0x0300 -#define CYGARC_REG_BCR2_A3_8 0x0040 -#define CYGARC_REG_BCR2_A3_16 0x0080 -#define CYGARC_REG_BCR2_A3_32 0x00c0 -#define CYGARC_REG_BCR2_A2_8 0x0010 -#define CYGARC_REG_BCR2_A2_16 0x0020 -#define CYGARC_REG_BCR2_A2_32 0x0030 - -// Memory type selection and other IO behavior controls -#define CYGARC_REG_BCR1_PULA 0x8000 // Pin A25 to A0 Pull-Up -#define CYGARC_REG_BCR1_PULD 0x4000 // Pin D31 to D0 Pull-Up -#define CYGARC_REG_BCR1_HIZMEM 0x2000 // Hi-Z memory control -#define CYGARC_REG_BCR1_HIZCNT 0x1000 // High-Z Control -#define CYGARC_REG_BCR1_ENDIAN 0x0800 // Endian Flag -#define CYGARC_REG_BCR1_A0_BST_MASK 0x0600 // Area 0 Burst ROM Control -#define CYGARC_REG_BCR1_A0_BST_4 0x0200 -#define CYGARC_REG_BCR1_A0_BST_8 0x0400 -#define CYGARC_REG_BCR1_A0_BST_16 0x0600 -#define CYGARC_REG_BCR1_A5_BST_MASK 0x0180 // Area 5 Burst ROM Control -#define CYGARC_REG_BCR1_A5_BST_4 0x0080 -#define CYGARC_REG_BCR1_A5_BST_8 0x0100 -#define CYGARC_REG_BCR1_A5_BST_16 0x0180 -#define CYGARC_REG_BCR1_A6_BST_MASK 0x0060 // Area 6 Burst ROM Control -#define CYGARC_REG_BCR1_A6_BST_4 0x0020 -#define CYGARC_REG_BCR1_A6_BST_8 0x0040 -#define CYGARC_REG_BCR1_A6_BST_16 0x0060 -#define CYGARC_REG_BCR1_DRAMTP_MASK 0x001c // Area 2, Area 3 Memory Type -#define CYGARC_REG_BCR1_A5PCM 0x0002 // Area 5 Bus Type -#define CYGARC_REG_BCR1_A6PCM 0x0001 // Area 6 Bus Type - -// Intercycle wait states -#define CYGARC_REG_WCR1_WAITSEL 0x8000 // WAIT Sampling Timing Select -#define CYGARC_REG_WCR1_A6I_MASK 0x3000 // Intercycle Idle Specification -#define CYGARC_REG_WCR1_A6I_SHIFT 12 -#define CYGARC_REG_WCR1_A5I_MASK 0x0c00 -#define CYGARC_REG_WCR1_A5I_SHIFT 10 -#define CYGARC_REG_WCR1_A4I_MASK 0x0300 -#define CYGARC_REG_WCR1_A4I_SHIFT 8 -#define CYGARC_REG_WCR1_A3I_MASK 0x00c0 -#define CYGARC_REG_WCR1_A3I_SHIFT 6 -#define CYGARC_REG_WCR1_A2I_MASK 0x0030 -#define CYGARC_REG_WCR1_A2I_SHIFT 4 -#define CYGARC_REG_WCR1_A0I_MASK 0x0003 -#define CYGARC_REG_WCR1_A0I_SHIFT 0 - -#define CYGARC_REG_WCR1_0WS 0 -#define CYGARC_REG_WCR1_1WS 1 -#define CYGARC_REG_WCR1_2WS 2 -#define CYGARC_REG_WCR1_3WS 3 - - -// Wait states -#define CYGARC_REG_WCR2_A6_MASK 0xe000 // Wait states + burst pitch -#define CYGARC_REG_WCR2_A6_SHIFT 13 -#define CYGARC_REG_WCR2_A5_MASK 0x1c00 // Wait states + burst pitch -#define CYGARC_REG_WCR2_A5_SHIFT 10 -#define CYGARC_REG_WCR2_A4_MASK 0x0380 // Wait states -#define CYGARC_REG_WCR2_A4_SHIFT 7 -#define CYGARC_REG_WCR2_A3_MASK 0x0060 // Wait states / CAS latency -#define CYGARC_REG_WCR2_A3_SHIFT 5 -#define CYGARC_REG_WCR2_A2_MASK 0x0018 // Wait states / CAS latency -#define CYGARC_REG_WCR2_A2_SHIFT 3 -#define CYGARC_REG_WCR2_A0_MASK 0x0007 // Wait states + burst pitch -#define CYGARC_REG_WCR2_A0_SHIFT 0 - -#define CYGARC_REG_WCR2_0WS 0 -#define CYGARC_REG_WCR2_1WS 1 -#define CYGARC_REG_WCR2_2WS 2 -#define CYGARC_REG_WCR2_3WS 3 -#define CYGARC_REG_WCR2_4WS 4 -#define CYGARC_REG_WCR2_6WS 5 -#define CYGARC_REG_WCR2_8WS 6 -#define CYGARC_REG_WCR2_10WS 7 - - -//----------------------------------------------------------------------------- -// Calculate constants needed to drive the proper SDRAM refresh rate. Argument -// is delay between required refresh events in microseconds (us). Should be -// available off the SDRAM spec sheet. -// These should be a part of a fully CDLicized memory controller setup. -#define CYGARC_RTCSR_PRESCALE(_r_) \ -(((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \ - ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \ - ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \ - ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \ - ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \ - ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096) - -// These two macros provide the static values we need to stuff into the -// registers. -#define CYGARC_RTCSR_CKSx(_r_) \ - (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \ - ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \ - ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \ - ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \ - (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \ - (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 ) - -#define CYGARC_RTCSR_N(_r_) \ - (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000)) - - -//++++++ Module UBC ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// User Break Control -#define CYGARC_REG_BRCR 0xffffff98 // 16 bit - -#define CYGARC_REG_BARA 0xffffffb0 // 32 bit -#define CYGARC_REG_BAMRA 0xffffffb4 // 8 bit (v1) / 32 bit -#define CYGARC_REG_BBRA 0xffffffb8 // 16 bit -#define CYGARC_REG_BASRA 0xffffffe4 // 8 bit - -#define CYGARC_REG_BARB 0xffffffa0 // 32 bit -#define CYGARC_REG_BAMRB 0xffffffa4 // 8 bit (v1) / 32 bit -#define CYGARC_REG_BASRB 0xffffffe8 // 8 bit -#define CYGARC_REG_BBRB 0xffffffa8 // 16 bit -#define CYGARC_REG_BDRB 0xffffff90 // 32 bit -#define CYGARC_REG_BDMRB 0xffffff94 // 32 bit - -#ifdef CYGARC_SH_MOD_UBC_V3 -#define CYGARC_REG_BETR 0xffffff9c // 16 bit -#define CYGARC_REG_BRSR 0xffffffac // 32 bit -#define CYGARC_REG_BRDR 0xffffffbc // 32 bit -#endif - -#define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A -#define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B -#define CYGARC_REG_BRCR_PCBA 0x0400 // post execute channel A -#define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B -#define CYGARC_REG_BRCR_PCBB 0x0040 // post execute channel B -#define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select - -#ifdef CYGARC_SH_MOD_UBC_V1 -#define CYGARC_REG_BAMRA_BASMA 0x04 // BASRA masked -#define CYGARC_REG_BAMRA_BARA_UNMASKED 0x00 // BARA not masked -#define CYGARC_REG_BAMRA_BARA_10BIT 0x01 // Lowest 10 bit masked -#define CYGARC_REG_BAMRA_BARA_12BIT 0x02 // Lowest 12 bit masked -#define CYGARC_REG_BAMRA_BARA_MASKED 0x03 // All bits masked -#else -// mask is fully configurable in other versions of the UBC -#endif - -#ifdef CYGARC_SH_MOD_UBC_V3 -#define CYGARC_REG_BBRA_DMA 0x0080 // Break on DMAC cycle -#define CYGARC_REG_BBRA_CPU 0x0040 // Break on CPU cycle -#endif -#define CYGARC_REG_BBRA_DFETCH 0x0020 // Break on DFETCH -#define CYGARC_REG_BBRA_IFETCH 0x0010 // Break on IFETCH -#define CYGARC_REG_BBRA_WRITE 0x0008 // Break on WRITE -#define CYGARC_REG_BBRA_READ 0x0004 // Break on READ -#define CYGARC_REG_BBRA_SIZE_LONG 0x0003 // Break on long access -#define CYGARC_REG_BBRA_SIZE_WORD 0x0002 // Break on word access -#define CYGARC_REG_BBRA_SIZE_BYTE 0x0001 // Break on byte access -#define CYGARC_REG_BBRA_SIZE_ANY 0x0000 // Break on any size - - -//++++++ Module CPG ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// Oscillator control registers -#define CYGARC_REG_FRQCR 0xffffff80 -#define CYGARC_REG_WTCNT 0xffffff84 // read 8bit, write 16bit -#define CYGARC_REG_WTCSR 0xffffff86 // read 8bit, write 16bit - -#define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write - -#define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write -#define CYGARC_REG_WTCSR_TME 0x80 // timer enable -#define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0) -#define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0) -#define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow -#define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow -#define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2 -#define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1 -#define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0 -#define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask -// This is the period (in us) between watchdog reset and overflow. -// Note: We use max timeout delay for now. -#define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay - -#define CYGARC_REG_WTCSR_PERIOD ((1000000000/(CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/4096))*256) - -// Translate various CDL clock configurations to register equivalents -// for the various CPG versions -#if defined(CYGARC_SH_MOD_CPG_V1) // ---------------------------- V1 - -// PLL1 -#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 -#else -# error "Unsupported PLL1 setting" -#endif - -// Divider1 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 -#else -# error "Unsupported Divider1 setting" -#endif - -// Divider2 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 -#else -# error "Unsupported Divider1 setting" -#endif - -// CKOEN - set in all modes but 7 -#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 7) -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 -#else -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 -#endif - -#elif defined(CYGARC_SH_MOD_CPG_V2) // ---------------------------- V2 - -// PLL1 -#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 -#else -# error "Unsupported PLL1 setting" -#endif - -// Divider1 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 -#else -# error "Unsupported Divider1 setting" -#endif - -// Divider2 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 -#else -# error "Unsupported Divider1 setting" -#endif - -// CKOEN - set in all modes but 2 -#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 2) -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 -#else -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 -#endif - -#elif defined(CYGARC_SH_MOD_CPG_V3) // ---------------------------- V3 - -// PLL1 -#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 3) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x8000 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x8010 -#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8) -# define CYGARC_REG_FRQCR_INIT_PLL1 0x0030 -#else -# error "Unsupported PLL1 setting" -#endif - -// Divider1 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 3) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x4000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 -#else -# error "Unsupported Divider1 setting" -#endif - -// Divider2 -#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 3) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2000 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 -#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 6) -# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002 -#else -# error "Unsupported Divider2 setting" -#endif - -// CKOEN - set in modes 0-2 -#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2) -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 -#else -# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 -#endif - -#else - -# error "Unsupported CPG version" - -#endif - -// Init value -#define CYGARC_REG_FRQCR_INIT (CYGARC_REG_FRQCR_INIT_PLL1|CYGARC_REG_FRQCR_INIT_DIVIDER1|CYGARC_REG_FRQCR_INIT_DIVIDER2|CYGARC_REG_FRQCR_INIT_CKOEN) - -//++++++ Module TMU ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// TMU registers -#define CYGARC_REG_TOCR 0xfffffe90 // 8 bit -#define CYGARC_REG_TSTR 0xfffffe92 // 8 bit -#define CYGARC_REG_TCOR0 0xfffffe94 // 32 bit -#define CYGARC_REG_TCNT0 0xfffffe98 // 32 bit -#define CYGARC_REG_TCR0 0xfffffe9c // 16 bit -#define CYGARC_REG_TCOR1 0xfffffea0 // 32 bit -#define CYGARC_REG_TCNT1 0xfffffea4 // 32 bit -#define CYGARC_REG_TCR1 0xfffffea8 // 16 bit -#define CYGARC_REG_TCOR2 0xfffffeac // 32 bit -#define CYGARC_REG_TCNT2 0xfffffeb0 // 32 bit -#define CYGARC_REG_TCR2 0xfffffeb4 // 16 bit -#define CYGARC_REG_TCPR2 0xfffffeb8 // 32 bit - -// TSTR -#define CYGARC_REG_TSTR_STR0 0x0001 -#define CYGARC_REG_TSTR_STR1 0x0002 -#define CYGARC_REG_TSTR_STR2 0x0004 - -// TCR0/1/2 -#define CYGARC_REG_TCR_TPSC0 0x0001 -#define CYGARC_REG_TCR_TPSC1 0x0002 -#define CYGARC_REG_TCR_TPSC2 0x0004 -#define CYGARC_REG_TCR_CKEG0 0x0008 -#define CYGARC_REG_TCR_CKEG1 0x0010 -#define CYGARC_REG_TCR_UNIE 0x0020 -#define CYGARC_REG_TCR_UNF 0x0100 - -#define CYGARC_REG_TCR_TPSC_4 (0) -#define CYGARC_REG_TCR_TPSC_16 (CYGARC_REG_TCR_TPSC0) -#define CYGARC_REG_TCR_TPSC_64 (CYGARC_REG_TCR_TPSC1) -#define CYGARC_REG_TCR_TPSC_256 (CYGARC_REG_TCR_TPSC0|CYGARC_REG_TCR_TPSC1) - -// TCR2 additional bits -#define CYGARC_REG_TCR_ICPE0 0x0040 -#define CYGARC_REG_TCR_ICPE1 0x0080 -#define CYGARC_REG_TCR_ICPF 0x0200 - - -//++++++ Module INTC +++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// Interrupt registers -#define CYGARC_REG_EXCEVT 0xffffffd4 -#define CYGARC_REG_INTEVT 0xffffffd8 - -#define CYGARC_REG_ICR 0xfffffee0 -#define CYGARC_REG_IPRA 0xfffffee2 -#define CYGARC_REG_IPRB 0xfffffee4 - -//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these -# define CYGARC_REG_INTEVT2 0xa4000000 -# define CYGARC_REG_IRR0 0xa4000004 -# define CYGARC_REG_IRR1 0xa4000006 -# define CYGARC_REG_IRR2 0xa4000008 -# define CYGARC_REG_ICR0 CYGARC_REG_ICR -# define CYGARC_REG_ICR1 0xa4000010 -# define CYGARC_REG_ICR2 0xa4000012 -# define CYGARC_REG_INTER 0xa4000014 -# define CYGARC_REG_IPRC 0xa4000016 -# define CYGARC_REG_IPRD 0xa4000018 -# define CYGARC_REG_IPRE 0xa400001a -//#endif -//#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these -# define CYGARC_REG_IRR3 0xa400000a -# define CYGARC_REG_IRR4 0xa400000c -# define CYGARC_REG_IPRF 0xa400001c -//#endif - - -#define CYGARC_REG_IPRA_TMU0_MASK 0xf000 -#define CYGARC_REG_IPRA_TMU0_PRI1 0x1000 -#define CYGARC_REG_IPRA_TMU1_MASK 0x0f00 -#define CYGARC_REG_IPRA_TMU1_PRI1 0x0100 -#define CYGARC_REG_IPRA_TMU2_MASK 0x00f0 -#define CYGARC_REG_IPRA_TMU2_PRI1 0x0010 -#define CYGARC_REG_IPRA_RTC_MASK 0x000f -#define CYGARC_REG_IPRA_RTC_PRI1 0x0001 - -#define CYGARC_REG_IPRB_WDT_MASK 0xf000 -#define CYGARC_REG_IPRB_WDT_PRI1 0x1000 -#define CYGARC_REG_IPRB_REF_MASK 0x0f00 -#define CYGARC_REG_IPRB_REF_PRI1 0x0100 -#define CYGARC_REG_IPRB_SCI_MASK 0x00f0 -#define CYGARC_REG_IPRB_SCI_PRI1 0x0010 - -//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these -#define CYGARC_REG_IPRC_IRQ3_MASK 0xf000 -#define CYGARC_REG_IPRC_IRQ3_PRI1 0x1000 -#define CYGARC_REG_IPRC_IRQ2_MASK 0x0f00 -#define CYGARC_REG_IPRC_IRQ2_PRI1 0x0100 -#define CYGARC_REG_IPRC_IRQ1_MASK 0x00f0 -#define CYGARC_REG_IPRC_IRQ1_PRI1 0x0010 -#define CYGARC_REG_IPRC_IRQ0_MASK 0x000f -#define CYGARC_REG_IPRC_IRQ0_PRI1 0x0001 - -#define CYGARC_REG_IPRD_PINT07_MASK 0xf000 -#define CYGARC_REG_IPRD_PINT07_PRI1 0x1000 -#define CYGARC_REG_IPRD_PINT8F_MASK 0x0f00 -#define CYGARC_REG_IPRD_PINT8F_PRI1 0x0100 -#define CYGARC_REG_IPRD_IRQ5_MASK 0x00f0 -#define CYGARC_REG_IPRD_IRQ5_PRI1 0x0010 -#define CYGARC_REG_IPRD_IRQ4_MASK 0x000f -#define CYGARC_REG_IPRD_IRQ4_PRI1 0x0001 - -#define CYGARC_REG_IPRE_DMAC_MASK 0xf000 -#define CYGARC_REG_IPRE_DMAC_PRI1 0x1000 -#define CYGARC_REG_IPRE_IRDA_MASK 0x0f00 -#define CYGARC_REG_IPRE_IRDA_PRI1 0x0100 -#define CYGARC_REG_IPRE_SCIF_MASK 0x00f0 -#define CYGARC_REG_IPRE_SCIF_PRI1 0x0010 -#define CYGARC_REG_IPRE_ADC_MASK 0x000f -#define CYGARC_REG_IPRE_ADC_PRI1 0x0001 - -#define CYGARC_REG_ICR1_MAI 0x8000 -#define CYGARC_REG_ICR1_IRQLVL 0x4000 -#define CYGARC_REG_ICR1_BLMSK 0x2000 -#define CYGARC_REG_ICR1_IRLSEN 0x1000 -#define CYGARC_REG_ICR1_SENSE_IRQ5_shift 10 -#define CYGARC_REG_ICR1_SENSE_IRQ4_shift 8 -#define CYGARC_REG_ICR1_SENSE_IRQ3_shift 6 -#define CYGARC_REG_ICR1_SENSE_IRQ2_shift 4 -#define CYGARC_REG_ICR1_SENSE_IRQ1_shift 2 -#define CYGARC_REG_ICR1_SENSE_IRQ0_shift 0 -#define CYGARC_REG_ICR1_SENSE_LEVEL 0x2 -#define CYGARC_REG_ICR1_SENSE_UP 0x1 - -// The (initial) IRQ mode is controlled by configuration. -#ifdef CYGHWR_HAL_SH_IRQ_USE_IRQLVL -# ifdef CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS -# define CYGARC_REG_ICR1_INIT (CYGARC_REG_ICR1_IRLSEN|CYGARC_REG_ICR1_IRQLVL) -# else -# define CYGARC_REG_ICR1_INIT (CYGARC_REG_ICR1_IRQLVL) -# endif -#else -# define CYGARC_REG_ICR1_INIT 0x0000 -#endif - -#define CYGARC_REG_IRR0_PINT07 0x80 -#define CYGARC_REG_IRR0_PINT8F 0x40 -#define CYGARC_REG_IRR0_IRQ5 0x20 -#define CYGARC_REG_IRR0_IRQ4 0x10 -#define CYGARC_REG_IRR0_IRQ3 0x08 -#define CYGARC_REG_IRR0_IRQ2 0x04 -#define CYGARC_REG_IRR0_IRQ1 0x02 -#define CYGARC_REG_IRR0_IRQ0 0x01 - -//#endif - -//#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these -#define CYGARC_REG_IPRF_LCDI_MASK 0x0f00 -#define CYGARC_REG_IPRF_LCDI_PRI1 0x0100 -#define CYGARC_REG_IPRF_PCC0_MASK 0x00f0 -#define CYGARC_REG_IPRF_PCC0_PRI1 0x0010 -#define CYGARC_REG_IPRF_PCC1_MASK 0x000f -#define CYGARC_REG_IPRF_PCC1_PRI1 0x0001 - -//#endif - -//++++++ Module RTC ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// RealTime Clock - -#define CYGARC_REG_RC64CNT 0xfffffec0 -#define CYGARC_REG_RSECCNT 0xfffffec2 -#define CYGARC_REG_RMINCNT 0xfffffec4 -#define CYGARC_REG_RHRCNT 0xfffffec6 -#define CYGARC_REG_RWKCNT 0xfffffec8 -#define CYGARC_REG_RDAYCNT 0xfffffeca -#define CYGARC_REG_RMONCNT 0xfffffecc -#define CYGARC_REG_RYRCNT 0xfffffece -#define CYGARC_REG_RSECAR 0xfffffed0 -#define CYGARC_REG_RMINAR 0xfffffed2 -#define CYGARC_REG_RHRAR 0xfffffed4 -#define CYGARC_REG_RWKAR 0xfffffed6 -#define CYGARC_REG_RDAYAR 0xfffffed8 -#define CYGARC_REG_RMONAR 0xfffffeda -#define CYGARC_REG_RCR1 0xfffffedc -#define CYGARC_REG_RCR2 0xfffffede - - -#define CYGARC_REG_RCR1_CF 0x80 // carry flag -#define CYGARC_REG_RCR1_CIE 0x10 // carry interrupt enable -#define CYGARC_REG_RCR1_AIE 0x08 // alarm interrupt enable -#define CYGARC_REG_RCR1_AF 0x01 // alarm flag - -#define CYGARC_REG_RCR2_PEF 0x80 // periodic interrupt flag -#define CYGARC_REG_RCR2_PES2 0x40 // periodic interrupt setting -#define CYGARC_REG_RCR2_PES1 0x20 -#define CYGARC_REG_RCR2_PES0 0x10 -#define CYGARC_REG_RCR2_RTCEN 0x08 // RTC enable -#define CYGARC_REG_RCR2_ADJ 0x04 // second adjustment -#define CYGARC_REG_RCR2_RESET 0x02 // reset -#define CYGARC_REG_RCR2_START 0x01 // start - - - -//++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//-------------------------------------------------------------------------- -// Serial registers. All 8 bit registers. -#define CYGARC_REG_SCSMR 0xfffffe80 // serial mode register -#define CYGARC_REG_SCBRR 0xfffffe82 // bit rate register -#define CYGARC_REG_SCSCR 0xfffffe84 // serial control register -#define CYGARC_REG_SCTDR 0xfffffe86 // transmit data register -#define CYGARC_REG_SCSSR 0xfffffe88 // serial status register -#define CYGARC_REG_SCRDR 0xfffffe8a // receive data register - -#ifdef CYGARC_SH_MOD_SCI_V2 -# define CYGARC_REG_SCSPTR 0xfffffe7c // serial port register -#endif - -// Serial Mode Register -#define CYGARC_REG_SCSMR_CA 0x80 // communication mode -#define CYGARC_REG_SCSMR_CHR 0x40 // character length (7 if set) -#define CYGARC_REG_SCSMR_PE 0x20 // parity enable -#define CYGARC_REG_SCSMR_OE 0x10 // parity mode -#define CYGARC_REG_SCSMR_STOP 0x08 // stop bit length -#define CYGARC_REG_SCSMR_MP 0x04 // multiprocessor mode -#define CYGARC_REG_SCSMR_CKS1 0x02 // clock select 1 -#define CYGARC_REG_SCSMR_CKS0 0x01 // clock select 0 -#define CYGARC_REG_SCSMR_CKSx_MASK 0x03 // mask - -// Serial Control Register -#define CYGARC_REG_SCSCR_TIE 0x80 // transmit interrupt enable -#define CYGARC_REG_SCSCR_RIE 0x40 // receive interrupt enable -#define CYGARC_REG_SCSCR_TE 0x20 // transmit enable -#define CYGARC_REG_SCSCR_RE 0x10 // receive enable -#define CYGARC_REG_SCSCR_MPIE 0x08 // multiprocessor interrupt enable -#define CYGARC_REG_SCSCR_TEIE 0x04 // transmit-end interrupt enable -#define CYGARC_REG_SCSCR_CKE1 0x02 // clock enable 1 -#define CYGARC_REG_SCSCR_CKE0 0x01 // clock enable 0 - -// Serial Status Register -#define CYGARC_REG_SCSSR_TDRE 0x80 // transmit data register empty -#define CYGARC_REG_SCSSR_RDRF 0x40 // receive data register full -#define CYGARC_REG_SCSSR_ORER 0x20 // overrun error -#define CYGARC_REG_SCSSR_FER 0x10 // framing error -#define CYGARC_REG_SCSSR_PER 0x08 // parity error -#define CYGARC_REG_SCSSR_TEND 0x04 // transmit end -#define CYGARC_REG_SCSSR_MPB 0x02 // multiprocessor bit -#define CYGARC_REG_SCSSR_MPBT 0x01 // multiprocessor bit transfer - -// When clearing the status register, always write the value: -// CYGARC_REG_SCSSR_CLEARMASK & ~bit -// to prevent other bits than the one of interest to be cleared. -#define CYGARC_REG_SCSSR_CLEARMASK 0xf8 - -// Baud rate values calculation, depending on peripheral clock (Pf) -// n is CKS setting (0-3) -// N = (Pf/(64*2^(2n-1)*B))-1 -// With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get -// N = (Pf/(32*_CKS*B))-1 -// -// The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS -// setting for the given baud rate and peripheral clock. -// -// The error of the CKS+count value can be computed by: -// E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100 -// -#define CYGARC_SCBRR_PRESCALE(_b_) \ -((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \ - (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \ - (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64) - -// These two macros provide the static values we need to stuff into the -// registers. -#define CYGARC_SCBRR_CKSx(_b_) \ - ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \ - (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \ - (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3) -#define CYGARC_SCBRR_N(_b_) \ - (((_b_) < 4800) ? 0 : \ - ((_b_) > 115200) ? 0 : \ - ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1)) - -//++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++ -#ifdef CYGARC_SH_MOD_IRDA - -//-------------------------------------------------------------------------- -// IrDA (infrared data association). Can also act as regular serial w FIFO - -#define CYGARC_REG_SCSMR1 0xa4000140 -#define CYGARC_REG_SCBRR1 0xa4000142 -#define CYGARC_REG_SCSCR1 0xa4000144 -#define CYGARC_REG_SCFTDR1 0xa4000146 -#define CYGARC_REG_SCSSR1 0xa4000148 -#define CYGARC_REG_SCFRDR1 0xa400014a -#define CYGARC_REG_SCFCR1 0xa400014c -#define CYGARC_REG_SCFDR1 0xa400014e - -// Serial Mode Register -#define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode -#define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width -#define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?) -#define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1 -#define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0 -#define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask - -// Serial Control Register -#define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable -#define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable -#define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable -#define CYGARC_REG_SCSCR1_RE 0x10 // receive enable -#define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1 -#define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0 - -// Serial Status Register -#define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors -#define CYGARC_REG_SCSSR1_PER_shift 12 -#define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors -#define CYGARC_REG_SCSSR1_FER_shift 8 -#define CYGARC_REG_SCSSR1_ER 0x0080 // receive error -#define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end -#define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty -#define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection -#define CYGARC_REG_SCSSR1_FER 0x0008 // framing error -#define CYGARC_REG_SCSSR1_PER 0x0004 // parity error -#define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full -#define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready - -// When clearing the status register, always write the value: -// CYGARC_REG_SCSSR2_CLEARMASK & ~bit -// to prevent other bits than the one of interest to be cleared. -#define CYGARC_REG_SCSSR1_CLEARMASK 0xf3 - -// Serial FIFO Control Register -#define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger -#define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char -#define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars -#define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars -#define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars - -#define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger -#define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars -#define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars -#define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars -#define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char - -#define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable -#define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset -#define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset -#define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test - - -// Serial FIFO Data Count Set Register -#define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo -#define CYGARC_REG_SCFDR1_RCOUNT_shift 0 -#define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo -#define CYGARC_REG_SCFDR1_TCOUNT_shift 8 - -#endif // CYGARC_SH_MOD_IRDA - -//++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++ -#ifdef CYGARC_SH_MOD_SCIF - -//-------------------------------------------------------------------------- -// Serial w FIFO registers - -#define CYGARC_REG_SCSMR2 0xa4000150 // Serial mode -#define CYGARC_REG_SCBRR2 0xa4000152 // Bit rate -#define CYGARC_REG_SCSCR2 0xa4000154 // Serial control -#define CYGARC_REG_SCFTDR2 0xa4000156 // Transmit FIFO data -#define CYGARC_REG_SCSSR2 0xa4000158 // Serial status -#define CYGARC_REG_SCFRDR2 0xa400015a // Receive data FIFO -#define CYGARC_REG_SCFCR2 0xa400015c // FIFO control register -#define CYGARC_REG_SCFDR2 0xa400015e // FIFO data count set - -// Serial Mode Register -#define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set) -#define CYGARC_REG_SCSMR2_PE 0x20 // parity enable -#define CYGARC_REG_SCSMR2_OE 0x10 // parity mode -#define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length -#define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1 -#define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0 -#define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask - -// Serial Control Register -#define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable -#define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable -#define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable -#define CYGARC_REG_SCSCR2_RE 0x10 // receive enable -#define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1 -#define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0 - -// Serial Status Register -#define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors -#define CYGARC_REG_SCSSR2_PER_shift 12 -#define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors -#define CYGARC_REG_SCSSR2_FER_shift 8 -#define CYGARC_REG_SCSSR2_ER 0x0080 // receive error -#define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end -#define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty -#define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection -#define CYGARC_REG_SCSSR2_FER 0x0008 // framing error -#define CYGARC_REG_SCSSR2_PER 0x0004 // parity error -#define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full -#define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready - -// When clearing the status register, always write the value: -// CYGARC_REG_SCSSR2_CLEARMASK & ~bit -// to prevent other bits than the one of interest to be cleared. -#define CYGARC_REG_SCSSR2_CLEARMASK 0xf3 - -// Serial FIFO Control Register -#define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger -#define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char -#define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars -#define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars -#define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars - -#define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger -#define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars -#define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars -#define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars -#define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char - -#define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable -#define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset -#define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset -#define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test - - -// Serial FIFO Data Count Set Register -#define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo -#define CYGARC_REG_SCFDR2_RCOUNT_shift 0 -#define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo -#define CYGARC_REG_SCFDR2_TCOUNT_shift 8 - -#endif // CYGARC_SH_MOD_SCIF - -//++++++ Module DMAC +++++++++++++++++++++++++++++++++++++++++++++++++++++++ -#ifdef CYGARC_SH_MOD_DMAC - -//-------------------------------------------------------------------------- -// DMA Controller registers - -#define CYGARC_REG_SAR0 0xa4000020 -#define CYGARC_REG_DAR0 0xa4000024 -#define CYGARC_REG_DMATCR0 0xa4000028 -#define CYGARC_REG_CHCR0 0xa400002c -#define CYGARC_REG_SAR1 0xa4000030 -#define CYGARC_REG_DAR1 0xa4000034 -#define CYGARC_REG_DMATCR1 0xa4000038 -#define CYGARC_REG_CHCR1 0xa400003c -#define CYGARC_REG_SAR2 0xa4000040 -#define CYGARC_REG_DAR2 0xa4000044 -#define CYGARC_REG_DMATCR2 0xa4000048 -#define CYGARC_REG_CHCR2 0xa400004c -#define CYGARC_REG_SAR3 0xa4000050 -#define CYGARC_REG_DAR3 0xa4000054 -#define CYGARC_REG_DMATCR3 0xa4000058 -#define CYGARC_REG_CHCR3 0xa400005c -#define CYGARC_REG_DMAOR 0xa4000060 - -// Offsets from base register -#define CYGARC_REG_SAR 0x00 -#define CYGARC_REG_DAR 0x04 -#define CYGARC_REG_DMATCR 0x08 -#define CYGARC_REG_CHCR 0x0c - - -// DMA Channel Control Register. If there's a digit suffix to CHCR the flag -// is only valid in the listed channels. -#define CYGARC_REG_CHCR3_DI 0x00100000 // direct/indirect selection -#define CYGARC_REG_CHCR2_RO 0x00080000 // source address reload -#define CYGARC_REG_CHCR01_RL 0x00040000 // request check level -#define CYGARC_REG_CHCR01_AM 0x00020000 // acknowledge mode -#define CYGARC_REG_CHCR01_AL 0x00010000 // acknowledge level -#define CYGARC_REG_CHCR_DM1 0x00008000 // destination address mode -#define CYGARC_REG_CHCR_DM0 0x00004000 -#define CYGARC_REG_CHCR_SM1 0x00002000 // source address mode -#define CYGARC_REG_CHCR_SM0 0x00001000 -#define CYGARC_REG_CHCR_RS3 0x00000800 // resource select -#define CYGARC_REG_CHCR_RS2 0x00000400 -#define CYGARC_REG_CHCR_RS1 0x00000200 -#define CYGARC_REG_CHCR_RS0 0x00000100 -#define CYGARC_REG_CHCR01_DS 0x00000040 // DREQ select -#define CYGARC_REG_CHCR_TM 0x00000020 // transmit mode -#define CYGARC_REG_CHCR_TS1 0x00000010 // transmit size -#define CYGARC_REG_CHCR_TS0 0x00000008 -#define CYGARC_REG_CHCR_IE 0x00000004 // interrupt enable -#define CYGARC_REG_CHCR_TE 0x00000002 // transfer end -#define CYGARC_REG_CHCR_DE 0x00000001 // DMAC enable - -// Resource select options -#define CYGARC_REG_CHCR_RS_EXT_DUAL 0x00000000 -#define CYGARC_REG_CHCR_RS_EXT_EX_DAC 0x00000100 -#define CYGARC_REG_CHCR_RS_EXT_DAC_EX 0x00000300 -#define CYGARC_REG_CHCR_RS_AUTO 0x00000400 -#define CYGARC_REG_CHCR_RS_IRDA_TX 0x00000a00 -#define CYGARC_REG_CHCR_RS_IRDA_RX 0x00000b00 -#define CYGARC_REG_CHCR_RS_SCIF_TX 0x00000c00 -#define CYGARC_REG_CHCR_RS_SCIF_RX 0x00000d00 -#define CYGARC_REG_CHCR_RS_AD 0x00000e00 -#define CYGARC_REG_CHCR_RS_CMT 0x00000f00 - - -// DMA Operation Register -#define CYGARC_REG_DMAOR_PR1 0x0200 // priority level -#define CYGARC_REG_DMAOR_PR0 0x0100 -#define CYGARC_REG_DMAOR_AE 0x0004 // address error flag -#define CYGARC_REG_DMAOR_NMIF 0x0002 // NMI flag -#define CYGARC_REG_DMAOR_DME 0x0001 // DMA master enable - - -#endif // CYGARC_SH_MOD_DMAC - -//++++++ Module PFC +++++++++++++++++++++++++++++++++++++++++++++++++++++++ -#ifdef CYGARC_SH_MOD_PFC - -#define CYGARC_REG_PACR 0xa4000100 // port A control -#define CYGARC_REG_PBCR 0xa4000102 // port B control -#define CYGARC_REG_PCCR 0xa4000104 // port C control -#define CYGARC_REG_PDCR 0xa4000106 // port D control -#define CYGARC_REG_PECR 0xa4000108 // port E control -#define CYGARC_REG_PFCR 0xa400010a // port F control -#define CYGARC_REG_PGCR 0xa400010c // port G control -#define CYGARC_REG_PHCR 0xa400010e // port H control -#define CYGARC_REG_PJCR 0xa4000110 // port J control -#define CYGARC_REG_PKCR 0xa4000112 // port K control -#define CYGARC_REG_PLCR 0xa4000114 // port L control -#define CYGARC_REG_SCPCR 0xa4000116 // SC port control - -#define CYGARC_REG_PADR 0xa4000120 // port A data -#define CYGARC_REG_PBDR 0xa4000122 // port B data -#define CYGARC_REG_PCDR 0xa4000124 // port C data -#define CYGARC_REG_PDDR 0xa4000126 // port D data -#define CYGARC_REG_PEDR 0xa4000128 // port E data -#define CYGARC_REG_PFDR 0xa400012a // port F data -#define CYGARC_REG_PGDR 0xa400012c // port G data -#define CYGARC_REG_PHDR 0xa400012e // port H data -#define CYGARC_REG_PJDR 0xa4000130 // port J data -#define CYGARC_REG_PKDR 0xa4000132 // port K data -#define CYGARC_REG_PLDR 0xa4000134 // port L data -#define CYGARC_REG_SCPDR 0xa4000136 // SC port data - - -// Port C -#define CYGARC_REG_PCCR_PC7_MASK 0xc000 -#define CYGARC_REG_PCCR_PC7_shift 14 -#define CYGARC_REG_PCCR_PC6_MASK 0x3000 -#define CYGARC_REG_PCCR_PC6_shift 12 -#define CYGARC_REG_PCCR_PC5_MASK 0x0c00 -#define CYGARC_REG_PCCR_PC5_shift 10 -#define CYGARC_REG_PCCR_PC4_MASK 0x0300 -#define CYGARC_REG_PCCR_PC4_shift 8 -#define CYGARC_REG_PCCR_PC3_MASK 0x00c0 -#define CYGARC_REG_PCCR_PC3_shift 6 -#define CYGARC_REG_PCCR_PC2_MASK 0x0030 -#define CYGARC_REG_PCCR_PC2_shift 4 -#define CYGARC_REG_PCCR_PC1_MASK 0x000c -#define CYGARC_REG_PCCR_PC1_shift 2 -#define CYGARC_REG_PCCR_PC0_MASK 0x0003 -#define CYGARC_REG_PCCR_PC0_shift 0 - -#define CYGARC_REG_PCCR_MD_OTHER 0x0 -#define CYGARC_REG_PCCR_MD_OUT 0x1 -#define CYGARC_REG_PCCR_MD_IN_ON 0x2 -#define CYGARC_REG_PCCR_MD_IN_OFF 0x3 - -#define CYGARC_REG_PCDR_PC7DT 0x80 -#define CYGARC_REG_PCDR_PC6DT 0x40 -#define CYGARC_REG_PCDR_PC5DT 0x20 -#define CYGARC_REG_PCDR_PC4DT 0x10 -#define CYGARC_REG_PCDR_PC3DT 0x08 -#define CYGARC_REG_PCDR_PC2DT 0x04 -#define CYGARC_REG_PCDR_PC1DT 0x02 -#define CYGARC_REG_PCDR_PC0DT 0x01 - - -#endif // CYGARC_SH_MOD_PFC +#include <cyg/hal/var_regs.h> #endif // ifndef CYGONCE_HAL_SH_REGS_H
--- a/packages/hal/sh/arch/current/src/hal_misc.c +++ b/packages/hal/sh/arch/current/src/hal_misc.c @@ -53,6 +53,8 @@ #include <cyg/hal/hal_cache.h> // HAL cache #include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions +#include <cyg/hal/sh_regs.h> // timer registers + //--------------------------------------------------------------------------- // Functions used during initialization. @@ -193,43 +195,6 @@ hal_idle_thread_action( cyg_uint32 count } //--------------------------------------------------------------------------- -// Initial cache enabling - -#ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK -# define CACHE_MODE_P0 0 -#else -# define CACHE_MODE_P0 CYGARC_REG_CCR_WT -#endif - -#ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK -# define CACHE_MODE_P1 CYGARC_REG_CCR_CB -#else -# define CACHE_MODE_P1 0 -#endif - -externC void -cyg_hal_enable_caches(void) -{ - // Initialize cache. - HAL_UCACHE_INVALIDATE_ALL(); - - // Set cache modes - HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1); - -#ifdef CYGHWR_HAL_SH_CACHE_ENABLE - // Enable cache. - HAL_UCACHE_ENABLE(); -#endif -} - -//--------------------------------------------------------------------------- -// SH3 variant stuff -// This should be split out... -void -hal_variant_init(void) -{ -} - // Low-level delay (in microseconds) void @@ -259,342 +224,4 @@ hal_delay_us(int usecs) } //--------------------------------------------------------------------------- -// Interrupt function support - -#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING -externC cyg_uint8 cyg_hal_ILVL_table[]; -#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \ - /* Update the ILVL table, so it is easy for the interrupt entry */ \ - /* code to find out the level of a given interrupt source. */ \ - cyg_hal_ILVL_table[(_vector_)] = (_level_) -#else -#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) -#endif - -void -hal_interrupt_set_level(int vector, int level) -{ - cyg_uint16 iprX; - - CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level"); - CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) - && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); - - HAL_UPDATE_ILVL_TABLE(vector, level); - - switch( (vector) ) { - case CYGNUM_HAL_INTERRUPT_NMI: - /* fall through */ - case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: - /* Cannot change levels */ - break; - - /* IPRA */ - case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0: - HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); - iprX &= ~CYGARC_REG_IPRA_TMU0_MASK; - iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); - break; - case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1: - HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); - iprX &= ~CYGARC_REG_IPRA_TMU1_MASK; - iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); - break; - case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2: - case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2: - HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); - iprX &= ~CYGARC_REG_IPRA_TMU2_MASK; - iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); - break; - case CYGNUM_HAL_INTERRUPT_RTC_ATI: - case CYGNUM_HAL_INTERRUPT_RTC_PRI: - case CYGNUM_HAL_INTERRUPT_RTC_CUI: - HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); - iprX &= ~CYGARC_REG_IPRA_RTC_MASK; - iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); - break; - - /* IPRB */ - case CYGNUM_HAL_INTERRUPT_SCI_ERI: - case CYGNUM_HAL_INTERRUPT_SCI_RXI: - case CYGNUM_HAL_INTERRUPT_SCI_TXI: - case CYGNUM_HAL_INTERRUPT_SCI_TEI: - HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); - iprX &= ~CYGARC_REG_IPRB_SCI_MASK; - iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); - break; - case CYGNUM_HAL_INTERRUPT_WDT_ITI: - HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); - iprX &= ~CYGARC_REG_IPRB_WDT_MASK; - iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); - break; - case CYGNUM_HAL_INTERRUPT_REF_RCMI: - case CYGNUM_HAL_INTERRUPT_REF_ROVI: - HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); - iprX &= ~CYGARC_REG_IPRB_REF_MASK; - iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); - break; - -#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL - /* IPRC */ - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: - HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); - iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK; - iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: - HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); - iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK; - iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: - HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); - iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK; - iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: - HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); - iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK; - iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); - break; -#endif - /* IPRD */ - case CYGNUM_HAL_INTERRUPT_PINT_PINT07: - HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); - iprX &= ~CYGARC_REG_IPRD_PINT07_MASK; - iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); - break; - case CYGNUM_HAL_INTERRUPT_PINT_PINT8F: - HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); - iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK; - iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: - HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); - iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK; - iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: - HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); - iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK; - iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); - break; - - /* IPRE */ - case CYGNUM_HAL_INTERRUPT_DMAC_DEI0: - case CYGNUM_HAL_INTERRUPT_DMAC_DEI1: - case CYGNUM_HAL_INTERRUPT_DMAC_DEI2: - case CYGNUM_HAL_INTERRUPT_DMAC_DEI3: - HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); - iprX &= ~CYGARC_REG_IPRE_DMAC_MASK; - iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); - break; - case CYGNUM_HAL_INTERRUPT_IRDA_ERI1: - case CYGNUM_HAL_INTERRUPT_IRDA_RXI1: - case CYGNUM_HAL_INTERRUPT_IRDA_BRI1: - case CYGNUM_HAL_INTERRUPT_IRDA_TXI1: - HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); - iprX &= ~CYGARC_REG_IPRE_IRDA_MASK; - iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); - break; - case CYGNUM_HAL_INTERRUPT_SCIF_ERI2: - case CYGNUM_HAL_INTERRUPT_SCIF_RXI2: - case CYGNUM_HAL_INTERRUPT_SCIF_BRI2: - case CYGNUM_HAL_INTERRUPT_SCIF_TXI2: - HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); - iprX &= ~CYGARC_REG_IPRE_SCIF_MASK; - iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); - break; - case CYGNUM_HAL_INTERRUPT_ADC_ADI: - HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); - iprX &= ~CYGARC_REG_IPRE_ADC_MASK; - iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); - break; - - /* IPRF */ - case CYGNUM_HAL_INTERRUPT_LCDC_LCDI: - HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); - iprX &= ~CYGARC_REG_IPRF_LCDI_MASK; - iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); - break; - case CYGNUM_HAL_INTERRUPT_PCC_PCC0: - HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); - iprX &= ~CYGARC_REG_IPRF_PCC0_MASK; - iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); - break; - case CYGNUM_HAL_INTERRUPT_PCC_PCC1: - HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); - iprX &= ~CYGARC_REG_IPRF_PCC1_MASK; - iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1; - HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); - break; - - case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: - case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: - /* Do nothing for these reserved vectors. */ - break; - - default: - CYG_FAIL("Unknown interrupt vector"); - break; - } -} - -void -hal_interrupt_mask(int vector) -{ - switch( (vector) ) { - case CYGNUM_HAL_INTERRUPT_NMI: - /* fall through */ - case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: - /* Can only be masked by fiddling Imask in SR. */ - break; - case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: - HAL_INTERRUPT_SET_LEVEL((vector), 0); - break; - case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: - case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: - /* Do nothing for these reserved vectors. */ - break; - default: - CYG_FAIL("Unknown interrupt vector"); - break; - } -} - -void -hal_interrupt_unmask(int vector) -{ - switch( (vector) ) { - case CYGNUM_HAL_INTERRUPT_NMI: - /* fall through */ - case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: - /* Can only be unmasked by fiddling Imask in SR. */ - break; - case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: - HAL_INTERRUPT_SET_LEVEL((vector), 1); - break; - case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: - case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: - /* Do nothing for these reserved vectors. */ - break; - default: - CYG_FAIL("Unknown interrupt vector"); - break; - } -} - -void -hal_interrupt_acknowledge(int vector) -{ - if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 - && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { - - cyg_uint8 irr0; - - HAL_READ_UINT8(CYGARC_REG_IRR0, irr0); - switch ( vector ) { -#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: - irr0 &= ~CYGARC_REG_IRR0_IRQ0; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: - irr0 &= ~CYGARC_REG_IRR0_IRQ1; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: - irr0 &= ~CYGARC_REG_IRR0_IRQ2; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: - irr0 &= ~CYGARC_REG_IRR0_IRQ3; - break; -#endif - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: - irr0 &= ~CYGARC_REG_IRR0_IRQ4; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: - irr0 &= ~CYGARC_REG_IRR0_IRQ5; - break; - default: - CYG_FAIL("Unhandled interrupt vector"); - } - HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0); - } -} - -// Note: The PINTs can be masked and configured individually, even -// though there are only two vectors. Maybe add some fake vectors just -// for masking/configuring? -void -hal_interrupt_configure(int vector, int level, int up) -{ - if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 - && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { - - cyg_uint16 icr1, ss, mask; - ss = 0; - mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL; - if (up) ss |= CYGARC_REG_ICR1_SENSE_UP; - if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL; - CYG_ASSERT(!(up && level), "Cannot trigger on high level!"); - - switch( (vector) ) { - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; - break; -#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; - break; - case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: - ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; - mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; - break; -#endif - default: - CYG_FAIL("Unhandled interrupt vector"); - } - - HAL_READ_UINT16(CYGARC_REG_ICR1, icr1); - icr1 &= ~mask; - icr1 |= ss; - HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1); - } -} - -//--------------------------------------------------------------------------- // End of hal_misc.c
--- a/packages/hal/sh/arch/current/src/hal_mk_defs.c +++ b/packages/hal/sh/arch/current/src/hal_mk_defs.c @@ -103,18 +103,6 @@ main(void) DEFINE(CYGNUM_HAL_VSR_MAX, CYGNUM_HAL_VSR_MAX); DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT); DEFINE(CYGNUM_HAL_VSR_EXCEPTION_COUNT, CYGNUM_HAL_VSR_EXCEPTION_COUNT); - - // Caching details - DEFINE(CYGARC_REG_CACHE_ADDRESS_FLUSH, CYGARC_REG_CACHE_ADDRESS_FLUSH); - DEFINE(CYGARC_REG_CACHE_ADDRESS_BASE,CYGARC_REG_CACHE_ADDRESS_BASE); - DEFINE(CYGARC_REG_CACHE_ADDRESS_TOP,CYGARC_REG_CACHE_ADDRESS_TOP); - DEFINE(CYGARC_REG_CACHE_ADDRESS_STEP,CYGARC_REG_CACHE_ADDRESS_STEP); - DEFINE(HAL_UCACHE_SIZE, HAL_UCACHE_SIZE); - DEFINE(HAL_UCACHE_WAYS, HAL_UCACHE_WAYS); - DEFINE(HAL_UCACHE_LINE_SIZE, HAL_UCACHE_LINE_SIZE); - - - // Variant definitions - want these to be included instead. } //--------------------------------------------------------------------------
deleted file mode 100644 --- a/packages/hal/sh/arch/current/src/sh3_sci.c +++ /dev/null @@ -1,307 +0,0 @@ -//============================================================================= -// -// sh3_sci.c -// -// Simple driver for the SH Serial Communication Interface (SCI) -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 1999-05-17 -// Description: Simple driver for the SH Serial Communication Interface -// Clients of this file can configure the behavior with: -// CYGNUM_SCI_PORTS: number of SCI ports -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGNUM_HAL_SH_SH3_SCI_PORTS - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED -#include <cyg/hal/hal_misc.h> // Helper functions -#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS -#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP -#include <cyg/hal/hal_if.h> // Calling-if API -#include <cyg/hal/sh_regs.h> // serial register definitions - -#include <cyg/hal/sh3_sci.h> // our header - -//-------------------------------------------------------------------------- - -#ifndef CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE -# define CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE 38400 -#endif - -void -cyg_hal_plf_sci_init_channel(const channel_data_t* chan) -{ - cyg_uint8 tmp; - cyg_uint8* base = chan->base; - - // Disable Tx/Rx interrupts, but enable Tx/Rx - HAL_WRITE_UINT8(base+_REG_SCSCR, - CYGARC_REG_SCSCR_TE|CYGARC_REG_SCSCR_RE); - - // 8-1-no parity. - HAL_WRITE_UINT8(base+_REG_SCSMR, 0); - - // Set speed to CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE - HAL_READ_UINT8(base+_REG_SCSMR, tmp); - tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK; - tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE); - HAL_WRITE_UINT8(base+_REG_SCSMR, tmp); - HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE)); -} - -static cyg_bool -cyg_hal_plf_sci_getc_nonblock(void* __ch_data, cyg_uint8* ch) -{ - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - cyg_uint8 sr; - - HAL_READ_UINT8(base+_REG_SCSSR, sr); - if ((sr & CYGARC_REG_SCSSR_RDRF) == 0) - return false; - - HAL_READ_UINT8(base+_REG_SCRDR, *ch); - - // Clear buffer full flag. - HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_RDRF); - - return true; -} - -cyg_uint8 -cyg_hal_plf_sci_getc(void* __ch_data) -{ - cyg_uint8 ch; - CYGARC_HAL_SAVE_GP(); - - while(!cyg_hal_plf_sci_getc_nonblock(__ch_data, &ch)); - - CYGARC_HAL_RESTORE_GP(); - return ch; -} - -void -cyg_hal_plf_sci_putc(void* __ch_data, cyg_uint8 c) -{ - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - cyg_uint8 sr; - CYGARC_HAL_SAVE_GP(); - - do { - HAL_READ_UINT8(base+_REG_SCSSR, sr); - } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0); - - HAL_WRITE_UINT8(base+_REG_SCTDR, c); - - // Clear empty flag. - HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_TDRE); - - // Hang around until the character has been safely sent. - do { - HAL_READ_UINT8(base+_REG_SCSSR, sr); - } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0); - - CYGARC_HAL_RESTORE_GP(); -} - -#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ - || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) - -static channel_data_t channels[CYGNUM_HAL_SH_SH3_SCI_PORTS]; - -static void -cyg_hal_plf_sci_write(void* __ch_data, const cyg_uint8* __buf, - cyg_uint32 __len) -{ - CYGARC_HAL_SAVE_GP(); - - while(__len-- > 0) - cyg_hal_plf_sci_putc(__ch_data, *__buf++); - - CYGARC_HAL_RESTORE_GP(); -} - -static void -cyg_hal_plf_sci_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) -{ - CYGARC_HAL_SAVE_GP(); - - while(__len-- > 0) - *__buf++ = cyg_hal_plf_sci_getc(__ch_data); - - CYGARC_HAL_RESTORE_GP(); -} - -cyg_bool -cyg_hal_plf_sci_getc_timeout(void* __ch_data, cyg_uint8* ch) -{ - channel_data_t* chan = (channel_data_t*)__ch_data; - int delay_count; - cyg_bool res; - CYGARC_HAL_SAVE_GP(); - - delay_count = chan->msec_timeout * 10; // delay in .1 ms steps - - for(;;) { - res = cyg_hal_plf_sci_getc_nonblock(__ch_data, ch); - if (res || 0 == delay_count--) - break; - - CYGACC_CALL_IF_DELAY_US(100); - } - - CYGARC_HAL_RESTORE_GP(); - return res; -} - -static int -cyg_hal_plf_sci_control(void *__ch_data, __comm_control_cmd_t __func, ...) -{ - static int irq_state = 0; - channel_data_t* chan = (channel_data_t*)__ch_data; - cyg_uint8 scr; - int ret = 0; - CYGARC_HAL_SAVE_GP(); - - switch (__func) { - case __COMMCTL_IRQ_ENABLE: - irq_state = 1; - HAL_INTERRUPT_UNMASK(chan->isr_vector); - HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); - scr |= CYGARC_REG_SCSCR_RIE; - HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); - break; - case __COMMCTL_IRQ_DISABLE: - ret = irq_state; - irq_state = 0; - HAL_INTERRUPT_UNMASK(chan->isr_vector); - HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); - scr &= ~CYGARC_REG_SCSCR_RIE; - HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); - break; - case __COMMCTL_DBG_ISR_VECTOR: - ret = chan->isr_vector; - break; - case __COMMCTL_SET_TIMEOUT: - { - va_list ap; - - va_start(ap, __func); - - ret = chan->msec_timeout; - chan->msec_timeout = va_arg(ap, cyg_uint32); - - va_end(ap); - } - default: - break; - } - CYGARC_HAL_RESTORE_GP(); - return ret; -} - -static int -cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc, - CYG_ADDRWORD __vector, CYG_ADDRWORD __data) -{ - cyg_uint8 c, sr; - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - int res = 0; - CYGARC_HAL_SAVE_GP(); - - *__ctrlc = 0; - HAL_READ_UINT8(base+_REG_SCSSR, sr); - if (sr & CYGARC_REG_SCSSR_RDRF) { - HAL_READ_UINT8(base+_REG_SCRDR, c); - - // Clear buffer full flag. - HAL_WRITE_UINT8(base+_REG_SCSSR, - CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF); - - if( cyg_hal_is_break( &c , 1 ) ) - *__ctrlc = 1; - - res = CYG_ISR_HANDLED; - } - - CYGARC_HAL_RESTORE_GP(); - return res; -} - -void -cyg_hal_plf_sci_init(int sci_index, int comm_index, - int rcv_vect, cyg_uint8* base) -{ - channel_data_t* chan = &channels[sci_index]; - hal_virtual_comm_table_t* comm; - int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); - - // Initialize channel table - chan->base = base; - chan->isr_vector = rcv_vect; - chan->msec_timeout = 1000; - - // Disable interrupts. - HAL_INTERRUPT_MASK(chan->isr_vector); - - // Init channel - - cyg_hal_plf_sci_init_channel(chan); - - // Setup procs in the vector table - - // Initialize channel procs - CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); - comm = CYGACC_CALL_IF_CONSOLE_PROCS(); - CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_sci_write); - CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_sci_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_sci_putc); - CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_sci_getc); - CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_sci_control); - CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_sci_isr); - CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_sci_getc_timeout); - - // Restore original console - CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); -} - -#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES - -#endif // CYGNUM_HAL_SH_SH3_SCI_PORTS - -//----------------------------------------------------------------------------- -// end of sh_sci.c
deleted file mode 100644 --- a/packages/hal/sh/arch/current/src/sh3_scif.c +++ /dev/null @@ -1,344 +0,0 @@ -//============================================================================= -// -// sh3_scif.c -// -// Simple driver for the SH3 Serial Communication Interface with FIFO -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 2000-03-30 -// Description: Simple driver for the SH Serial Communication Interface -// The driver can be used for either the SCIF or the IRDA -// modules (the latter can act as the former). -// Clients of this file can configure the behavior with: -// CYGNUM_SCIF_PORTS: number of SCI ports -// -// Note: It should be possible to configure a channel to IRDA mode. -// Worry about that when some board needs it. -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGNUM_HAL_SH_SH3_SCIF_PORTS - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED -#include <cyg/hal/hal_misc.h> // Helper functions -#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS -#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP -#include <cyg/hal/hal_if.h> // Calling-if API -#include <cyg/hal/sh_regs.h> // serial register definitions -#include <cyg/hal/sh_stub.h> // target_register_t - -#include <cyg/hal/sh3_scif.h> // our header - -//-------------------------------------------------------------------------- - -#ifndef CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE -# define CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE 38400 -#endif - -void -cyg_hal_plf_scif_init_channel(const channel_data_t* chan) -{ - cyg_uint8* base = chan->base; - cyg_uint8 tmp; - cyg_uint16 sr; - - // Disable everything. - HAL_WRITE_UINT8(base+_REG_SCSCR, 0); - - // Reset FIFO. - HAL_WRITE_UINT8(base+_REG_SCFCR, - CYGARC_REG_SCFCR2_TFRST|CYGARC_REG_SCFCR2_RFRST); - - // 8-1-no parity. - HAL_WRITE_UINT8(base+_REG_SCSMR, 0); - - // Set speed to CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE - HAL_READ_UINT8(base+_REG_SCSMR, tmp); - tmp &= ~CYGARC_REG_SCSMR2_CKSx_MASK; - tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE); - HAL_WRITE_UINT8(base+_REG_SCSMR, tmp); - HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE)); - - // Let things settle: Here we should should wait the equivalent of - // one bit interval, - // i.e. 1/CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE second, but - // until we have something like the Linux delay loop, it's hard to - // do reliably. So just move on and hope for the best (this is - // unlikely to cause problems since the CPU has just come out of - // reset anyway). - - // Clear status register (read back first). - HAL_READ_UINT16(base+_REG_SCSSR, sr); - HAL_WRITE_UINT16(base+_REG_SCSSR, 0); - - // Bring FIFO out of reset and set to trigger on every char in - // FIFO (or C-c input would not be processed). - HAL_WRITE_UINT8(base+_REG_SCFCR, - CYGARC_REG_SCFCR2_RTRG_1|CYGARC_REG_SCFCR2_TTRG_1); - - // Leave Tx/Rx interrupts disabled, but enable Tx/Rx - HAL_WRITE_UINT8(base+_REG_SCSCR, - CYGARC_REG_SCSCR2_TE|CYGARC_REG_SCSCR2_RE); -} - -//static -cyg_bool -cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch) -{ - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - cyg_uint16 fdr, sr; - - HAL_READ_UINT16(base+_REG_SCFDR, fdr); - if (0 == (fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK)) - return false; - - HAL_READ_UINT8(base+_REG_SCFRDR, *ch); - - // Clear DR/RDF flags - HAL_READ_UINT16(base+_REG_SCSSR, sr); - HAL_WRITE_UINT16(base+_REG_SCSSR, - CYGARC_REG_SCSSR2_CLEARMASK & ~(CYGARC_REG_SCSSR2_RDF | CYGARC_REG_SCSSR2_DR)); - - return true; -} - -cyg_uint8 -cyg_hal_plf_scif_getc(void* __ch_data) -{ - cyg_uint8 ch; - CYGARC_HAL_SAVE_GP(); - - while(!cyg_hal_plf_scif_getc_nonblock(__ch_data, &ch)); - - CYGARC_HAL_RESTORE_GP(); - return ch; -} - -void -cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c) -{ - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - cyg_uint16 fdr, sr; - CYGARC_HAL_SAVE_GP(); - - do { - HAL_READ_UINT16(base+_REG_SCFDR, fdr); - } while (((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) >> CYGARC_REG_SCFDR2_TCOUNT_shift) == 16); - - HAL_WRITE_UINT8(base+_REG_SCFTDR, c); - - // Clear FIFO-empty/transmit end flags (read back SR first) - HAL_READ_UINT16(base+_REG_SCSSR, sr); - HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCSSR2_CLEARMASK - & ~(CYGARC_REG_SCSSR2_TDFE | CYGARC_REG_SCSSR2_TEND )); - - // Hang around until the character has been safely sent. - do { - HAL_READ_UINT16(base+_REG_SCFDR, fdr); - } while ((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) != 0); - - CYGARC_HAL_RESTORE_GP(); -} - -#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ - || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) - -static channel_data_t channels[CYGNUM_HAL_SH_SH3_SCIF_PORTS]; - -static void -cyg_hal_plf_scif_write(void* __ch_data, const cyg_uint8* __buf, - cyg_uint32 __len) -{ - CYGARC_HAL_SAVE_GP(); - - while(__len-- > 0) - cyg_hal_plf_scif_putc(__ch_data, *__buf++); - - CYGARC_HAL_RESTORE_GP(); -} - -static void -cyg_hal_plf_scif_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) -{ - CYGARC_HAL_SAVE_GP(); - - while(__len-- > 0) - *__buf++ = cyg_hal_plf_scif_getc(__ch_data); - - CYGARC_HAL_RESTORE_GP(); -} - -cyg_bool -cyg_hal_plf_scif_getc_timeout(void* __ch_data, cyg_uint8* ch) -{ - channel_data_t* chan = (channel_data_t*)__ch_data; - int delay_count; - cyg_bool res; - CYGARC_HAL_SAVE_GP(); - - delay_count = chan->msec_timeout * 10; // delay in .1 ms steps - - for(;;) { - res = cyg_hal_plf_scif_getc_nonblock(__ch_data, ch); - if (res || 0 == delay_count--) - break; - - CYGACC_CALL_IF_DELAY_US(100); - } - - CYGARC_HAL_RESTORE_GP(); - return res; -} - -static int -cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...) -{ - static int irq_state = 0; - channel_data_t* chan = (channel_data_t*)__ch_data; - cyg_uint8 scr; - int ret = 0; - CYGARC_HAL_SAVE_GP(); - - switch (__func) { - case __COMMCTL_IRQ_ENABLE: - irq_state = 1; - HAL_INTERRUPT_UNMASK(chan->isr_vector); - HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); - scr |= CYGARC_REG_SCSCR2_RIE; - HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); - break; - case __COMMCTL_IRQ_DISABLE: - ret = irq_state; - irq_state = 0; - HAL_INTERRUPT_UNMASK(chan->isr_vector); - HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); - scr &= ~CYGARC_REG_SCSCR2_RIE; - HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); - break; - case __COMMCTL_DBG_ISR_VECTOR: - ret = chan->isr_vector; - break; - case __COMMCTL_SET_TIMEOUT: - { - va_list ap; - - va_start(ap, __func); - - ret = chan->msec_timeout; - chan->msec_timeout = va_arg(ap, cyg_uint32); - - va_end(ap); - } - default: - break; - } - CYGARC_HAL_RESTORE_GP(); - return ret; -} - -static int -cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc, - CYG_ADDRWORD __vector, CYG_ADDRWORD __data) -{ - cyg_uint8 c; - cyg_uint16 fdr, sr; - cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - int res = 0; - CYGARC_HAL_SAVE_GP(); - - *__ctrlc = 0; - HAL_READ_UINT16(base+_REG_SCFDR, fdr); - if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) != 0) { - HAL_READ_UINT8(base+_REG_SCFRDR, c); - - // Clear buffer full flag (read back first). - HAL_READ_UINT16(base+_REG_SCSSR, sr); - HAL_WRITE_UINT16(base+_REG_SCSSR, - CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF); - - if( cyg_hal_is_break( &c , 1 ) ) - *__ctrlc = 1; - - res = CYG_ISR_HANDLED; - } - - CYGARC_HAL_RESTORE_GP(); - return res; -} - -void -cyg_hal_plf_scif_init(int scif_index, int comm_index, - int rcv_vect, cyg_uint8* base) -{ - channel_data_t* chan = &channels[scif_index]; - hal_virtual_comm_table_t* comm; - int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); - - // Initialize channel table - chan->base = base; - chan->isr_vector = rcv_vect; - chan->msec_timeout = 1000; - - // Disable interrupts. - HAL_INTERRUPT_MASK(chan->isr_vector); - - // Init channel - cyg_hal_plf_scif_init_channel(chan); - - // Setup procs in the vector table - - // Initialize channel procs - CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); - comm = CYGACC_CALL_IF_CONSOLE_PROCS(); - CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write); - CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc); - CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc); - CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control); - CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr); - CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout); - - // Restore original console - CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); -} - -#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES - -#endif // CYGNUM_HAL_SH_SH3_SCIF_PORTS - -//----------------------------------------------------------------------------- -// end of sh3_scif.c
--- a/packages/hal/sh/arch/current/src/sh_stub.c +++ b/packages/hal/sh/arch/current/src/sh_stub.c @@ -131,7 +131,7 @@ void __single_step (void) // The address of the instruction to execute. HAL_WRITE_UINT32(CYGARC_REG_BARA, get_register(PC)); // Match entire address. -#ifdef CYGARC_SH_MOD_UBC_V1 +#if (CYGARC_SH_MOD_UBC == 1) HAL_WRITE_UINT8(CYGARC_REG_BAMRA, CYGARC_REG_BAMRA_BARA_UNMASKED); #else HAL_WRITE_UINT32(CYGARC_REG_BAMRA, 0xffffffff); @@ -140,7 +140,7 @@ void __single_step (void) HAL_WRITE_UINT16(CYGARC_REG_BRCR, CYGARC_REG_BRCR_PCBA); // Stop on IFETCH/READ HAL_WRITE_UINT16(CYGARC_REG_BBRA, -#ifdef CYGARC_SH_MOD_UBC_V3 +#if (CYGARC_SH_MOD_UBC == 3) CYGARC_REG_BBRA_CPU| // Match on CPU cycle #endif CYGARC_REG_BBRA_IFETCH|CYGARC_REG_BBRA_READ);
--- a/packages/hal/sh/arch/current/src/vectors.S +++ b/packages/hal/sh/arch/current/src/vectors.S @@ -53,6 +53,7 @@ #endif #include <cyg/hal/arch.inc> +#include <cyg/hal/variant.inc> #include <cyg/hal/sh_regs.h> #include <cyg/hal/sh_offsets.inc> @@ -66,22 +67,6 @@ #undef __DEBUG #=========================================================================== -# SR initialization value -# zero all bits except: -# MD = Processor operation mode field (privileged mode) -# I0-3 = Mask out all interrupts but NMI. -# -# When saving or restoring the state of an exception or interrupt, the bit -# CYGARC_REG_SR_RB is also set, switching the register bank. When this bit -# is set, interrupts must be disabled. -# -# Note: We could also use the BL bit to prevent interrupts, but that would -# also prevent the use of breakpoints. - -#define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK) -#define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) - -#=========================================================================== # Start by defining the exceptions vectors. .section ".vectors","ax" @@ -124,7 +109,7 @@ mov #1,r7 #endif - mov #CYGARC_REG_EXCEVT,r1 + mov.l $nCYGARC_REG_EXCEVT,r1 mov.l @r1,r1 shlr2 r1 shlr r1 ! divide cause by 0x08 @@ -160,7 +145,7 @@ #ifdef __DEBUG mov.l $exc_state_marker,r0 mov.l r0,@-r15 - mov #CYGARC_REG_EXCEVT,r0 + mov.l $nCYGARC_REG_EXCEVT,r0 mov.l @r0,r0 mov.l r0,@-r15 #endif @@ -213,7 +198,7 @@ .globl _cyg_hal_default_exception_vsr_bp_safe _cyg_hal_default_exception_vsr_bp_safe: #endif - mov #CYGARC_REG_EXCEVT,r0 + mov.l $nCYGARC_REG_EXCEVT,r0 mov.l @r0,r4 mov #-5,r0 ! divide cause by 0x20 shld r0,r4 @@ -257,7 +242,7 @@ mov #2,r7 #endif - mov #CYGARC_REG_EXCEVT,r1 + mov.l $nCYGARC_REG_EXCEVT,r1 mov.l @r1,r1 shlr2 r1 shlr r1 ! divide cause by 0x08 @@ -269,6 +254,8 @@ .align 2 $_hal_vsr_table2: .long _hal_vsr_table +$nCYGARC_REG_EXCEVT: + .long CYGARC_REG_EXCEVT #--------------------------------------------------------------------------- # Interrupt entry @@ -279,7 +266,7 @@ #ifdef CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS # A spurious interrupt with INTEVT=0 may be caused by # clearing of BL. Those interrupts need to be ignored. - mov #CYGARC_REG_INTEVT,r0 + mov.l $nCYGARC_REG_INTEVT,r0 mov.l @r0,r0 cmp/eq #0,r0 bf 1f @@ -415,31 +402,13 @@ 1: mov.l r8,@-r15 1: #endif - # Decode the interrupt vector -#ifdef CYGARC_SH_MOD_INTC_V2 - mov.l $nCYGARC_REG_INTEVT2,r0 -#else - mov #CYGARC_REG_INTEVT,r0 -#endif - mov.l @r0,r4 - mov #-5,r0 ! divide cause by 0x20 - shld r0,r4 - add #-14,r4 ! adjust so NMI becomes 0 + # Decode the interrupt vector, and find ISR index + hal_intc_decode r0,r4 mov #CYGARC_SHREG_EVENT,r0 mov.l r4,@(r0,r8) ! store decoded vector number back ! to saved state. - - // Find ISR index. -#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN -#define CYG_ISR_TABLE_SIZE 1 - mov #0,r9 ! only one ISR in the table -#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN -#define CYG_ISR_TABLE_SIZE CYGNUM_HAL_ISR_COUNT - mov r4,r9 - shll2 r9 ! get from vector number to ISR index -#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN - + hal_intc_translate r4,r9 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) @@ -640,7 +609,9 @@ restore_state: .long CYG_SR $nCYG_SR_BANK1: .long CYG_SR_BANK1 -#ifdef CYGARC_SH_MOD_INTC_V2 +$nCYGARC_REG_INTEVT: + .long CYGARC_REG_INTEVT +#ifdef CYGARC_REG_INTEVT2 $nCYGARC_REG_INTEVT2: .long CYGARC_REG_INTEVT2 #endif @@ -675,54 +646,8 @@ restore_state: #--------------------------------------------------------------------------- # Platform initialization (reset) __reset_platform: - # Initialize CPU - mov.l $nCYG_SR,r1 ! Put CPU in a well-known state - ldc r1,sr - mov #0,r0 - mov #CYGARC_REG_CCR,r1 ! Disable cache - mov.l r0,@r1 - mov #CYGARC_REG_MMUCR,r1 ! Disable MMU - mov.l r0,@r1 - mov #CYGARC_REG_BBRA,r1 ! Disable UBC Channel A - mov.w r0,@r1 - mov #CYGARC_REG_BBRB,r1 ! Disable UBC Channel B - mov.w r0,@r1 - mov #CYGARC_REG_BRCR,r1 ! Reset UBC common register - mov.w r0,@r1 - mov.l $CYGARC_REG_TSTR,r1 ! Disable timers - mov.b r0,@r1 - mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources - mov.w r0,@r1 - mov.l $CYGARC_REG_IPRB,r1 - mov.w r0,@r1 -#ifdef CYGARC_SH_MOD_INTC_V2 - mov.l $CYGARC_REG_IPRC,r1 - mov.w r0,@r1 - mov.l $CYGARC_REG_IPRD,r1 - mov.w r0,@r1 - mov.l $CYGARC_REG_IPRE,r1 - mov.w r0,@r1 -#ifdef CYGARC_SH_MOD_INTC_V3 - mov.l $CYGARC_REG_IPRF,r1 - mov.w r0,@r1 -#endif - mov.w $nCYG_ICR1_INIT,r0 - mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode - mov.w r0,@r1 -#endif - mov.w $nCYG_WTCSR,r0 ! Clear watchdog - mov #CYGARC_REG_WTCSR,r1 - mov.w r0,@r1 + hal_post_reset_init - # Initialize VBR if necessary -#if !defined(CYG_HAL_STARTUP_RAM) || \ - ( defined(CYG_HAL_STARTUP_RAM) && \ - !defined(CYGSEM_HAL_USE_ROM_MONITOR)) - mov.l $__reset,r1 ! Set VBR - ldc r1,vbr -#endif - - #ifdef __DEBUG mov #0,r0 mov #1,r1 @@ -740,45 +665,7 @@ restore_state: mov #13,r13 mov #14,r14 #endif - - bra hal_hw_init - nop - -$nCYG_WTCSR: - .word 0xa500 ! clear all CSR bits - - .align 2 - -$nCYG_SR: - .long CYG_SR -$CYGARC_REG_TSTR: - .long CYGARC_REG_TSTR -$CYGARC_REG_IPRA: - .long CYGARC_REG_IPRA -$CYGARC_REG_IPRB: - .long CYGARC_REG_IPRB -#ifdef CYGARC_SH_MOD_INTC_V2 -$CYGARC_REG_IPRC: - .long CYGARC_REG_IPRC -$CYGARC_REG_IPRD: - .long CYGARC_REG_IPRD -$CYGARC_REG_IPRE: - .long CYGARC_REG_IPRE -$CYGARC_REG_ICR1: - .long CYGARC_REG_ICR1 -#endif -#ifdef CYGARC_SH_MOD_INTC_V2 -$CYGARC_REG_IPRF: - .long CYGARC_REG_IPRF -$nCYG_ICR1_INIT: - .word CYGARC_REG_ICR1_INIT - .align 2 -#endif -$__reset: - .long __reset - -hal_hw_init: - + # Call platform specific hardware initialization # This may include memory controller initialization. It is not # safe to access RAM until after this point. @@ -895,7 +782,7 @@ 2: # nop # Enable caches - mov.l $_cyg_hal_enable_caches,r1 + mov.l $_cyg_var_enable_caches,r1 jsr @r1 nop @@ -950,8 +837,8 @@ 9: .long __bss_end $_cyg_hal_invoke_constructors: .long _cyg_hal_invoke_constructors -$_cyg_hal_enable_caches: - .long _cyg_hal_enable_caches +$_cyg_var_enable_caches: + .long _cyg_var_enable_caches $_hal_variant_init: .long _hal_variant_init $_hal_platform_init: @@ -972,151 +859,6 @@ 9: #endif #--------------------------------------------------------------------------- -# Cache operations -# These need to be written in assembly to ensure they do not rely on data -# in cachable space (i.e., code must use registers exclusively, not the stack). - -# This macro must be used at the top of each cache function. It ensures -# that the code gets executed from a shadow region where caching is disabled -# (0xA0000000). - .macro GOTO_NONCACHED_SHADOW - mova 10f,r0 - mov.l $MASK,r1 - and r1,r0 - mov.l $BASE,r1 - or r1,r0 - jmp @r0 - nop - .align 2 -10: - .endm - - .globl _cyg_hal_cache_enable -_cyg_hal_cache_enable: - GOTO_NONCACHED_SHADOW - mov #CYGARC_REG_CCR,r1 - mov.l @r1,r0 - or #CYGARC_REG_CCR_CE,r0 - mov.l r0,@r1 - nop - rts - nop - - .globl _cyg_hal_cache_disable -_cyg_hal_cache_disable: - GOTO_NONCACHED_SHADOW - mov #CYGARC_REG_CCR,r1 - mov.l @r1,r0 - mov #CYGARC_REG_CCR_CE,r2 - not r2,r2 - and r2,r0 - mov.l r0,@r1 - nop - rts - nop - - .globl _cyg_hal_cache_invalidate_all -_cyg_hal_cache_invalidate_all: - GOTO_NONCACHED_SHADOW - mov #CYGARC_REG_CCR,r1 - mov.l @r1,r0 - or #CYGARC_REG_CCR_CF,r0 - mov.l r0,@r1 - nop ! Nothing in the docs suggest we need - nop ! nops here, but without them, the - nop ! CPU crashes. - rts - nop - - .globl _cyg_hal_cache_sync -_cyg_hal_cache_sync: - GOTO_NONCACHED_SHADOW - mov.l $CYGARC_REG_CACHE_ADDRESS_FLUSH,r0 - mov.l $CYGARC_REG_CACHE_ADDRESS_BASE,r1 - mov.l $CYGARC_REG_CACHE_ADDRESS_TOP,r2 - mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3 -1: cmp/hi r1,r2 - bf 2f - mov.l r0,@r1 - bra 1b - add r3,r1 ! delay slot! -2: nop - rts - nop - - ! r4 = base - ! r5 = size - .globl _cyg_hal_cache_sync_region -_cyg_hal_cache_sync_region: - GOTO_NONCACHED_SHADOW - mov.l 10f,r0 - and r4,r0 ! array index - mov.l 11f,r1 - add r0,r1 ! base (aligned, A set) - - ! make sure top is aligned to start of _next_ cache line - mov r1,r0 - add r5,r0 ! top (non-aligned) - add #2*HAL_UCACHE_LINE_SIZE-1,r0 - mov.l 13f,r2 - and r0,r2 - - mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3 - mov.l 12f,r5 -1: cmp/hi r1,r2 - bf 3f - mov r4,r0 ! create address tag - and r5,r0 - mov.l r0,@r1 ! store tag in array, causing (sync+)invalidate - ! if the tag matches any of the lines - add r3,r4 ! inc address tag - bra 1b - add r3,r1 ! inc array index, delay slot! -3: nop - rts - nop - - .align 2 -10: .long ((HAL_UCACHE_SIZE/HAL_UCACHE_WAYS)-1)&~0xf ! mask -11: .long CYGARC_REG_CACHE_ADDRESS_BASE|CYGARC_REG_CACHE_ADDRESS_ADDRESS -12: .long CYGARC_REG_CACHE_ADDRESS_TAG_Mask -13: .long ~(HAL_UCACHE_LINE_SIZE-1) - - .globl _cyg_hal_cache_write_mode -_cyg_hal_cache_write_mode: - GOTO_NONCACHED_SHADOW - # Mode argument in r4. - # Read current state and mask out the two caching mode bits - mov #CYGARC_REG_CCR,r1 - mov.l @r1,r3 - mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2 - and r2,r4 - not r2,r2 - and r2,r3 - # Or in the new settings and restore to CCR - or r4,r3 - mov.l r3,@r1 - nop - rts - nop - - .align 2 -$CYGARC_REG_CACHE_ADDRESS_FLUSH: - .long CYGARC_REG_CACHE_ADDRESS_FLUSH -$CYGARC_REG_CACHE_ADDRESS_BASE: - .long CYGARC_REG_CACHE_ADDRESS_BASE -$CYGARC_REG_CACHE_ADDRESS_TOP: - .long CYGARC_REG_CACHE_ADDRESS_TOP -$CYGARC_REG_CACHE_ADDRESS_STEP: - .long CYGARC_REG_CACHE_ADDRESS_STEP - - -$MASK: - .long 0x1fffffff ! mask off top 3 bits -$BASE: - .long 0xa0000000 ! base of non-cachable memory - -#--------------------------------------------------------------------------- # Interrupt vector tables. # These tables contain the isr, data and object pointers used to deliver # interrupts to user code. @@ -1124,6 +866,11 @@ 13: .long ~(HAL_UCACHE_LINE_SIZE-1) .data .extern _hal_default_isr +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN +#define CYG_ISR_TABLE_SIZE 1 +#else +#define CYG_ISR_TABLE_SIZE CYGNUM_HAL_ISR_COUNT +#endif .globl _hal_interrupt_handlers _hal_interrupt_handlers:
--- a/packages/hal/sh/cq7708/current/ChangeLog +++ b/packages/hal/sh/cq7708/current/ChangeLog @@ -1,3 +1,8 @@ +2000-10-31 Jesper Skov <jskov@redhat.com> + + * include/plf_intr.h: Added. + * include/plf_cache.h: Added. + 2000-10-20 Jonathan Larmour <jlarmour@redhat.com> * include/pkgconf/mlt_sh_sh7708_cq7708_ram.h:
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7708/current/include/plf_cache.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform specific cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-31 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7708/current/include/plf_intr.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, +// Date: 2000-10-31 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the CQ7708 board. +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +//-------------------------------------------------------------------------- + +// No platform specific stuff at present. + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/ChangeLog @@ -0,0 +1,37 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_sh7750_cq7750.cdl: Adding clock options. + +2000-08-16 Haruki Kashiwaya <kashiwaya@redhat.com> + + * Set up directory structure. + +2000-04-18 Ryozaburo Suzuki <ryos@atom-tc.or.jp> + + * Contributed sources for the CqREEK/SH-4 platform. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl @@ -0,0 +1,319 @@ +# ==================================================================== +# +# hal_sh_sh7750_cq7750.cdl +# +# CQ7750 board HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: jskov +# Contributors: Ryozaburo Suzuki +# Date: 1999-10-29 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SH_SH7750_CQ7750 { + display "CqREEK SH7750 board" + parent CYGPKG_HAL_SH + requires CYGPKG_HAL_SH_7750 + define_header hal_sh_sh7750_cq7750.h + include_dir cyg/hal + description " + The cq HAL package provides the support needed to run + eCos on a CqREEK SH7750 board." + + compile hal_diag.c plf_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7750_cq7750.h>" + + puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1" + puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000" + puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the CQ7750 board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. + RAM bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap typically + requires that the eCos application be blown into EPROMs or + equivalent technology." + } + + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The CQ/7750 board has only one serial port. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The CQ/7750 board has only one serial port. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS { + display "SH on-chip platform clock controls" + description " + The various clocks used by the system are derived from + these options." + flavor none + no_define + + cdl_option CYGHWR_HAL_SH_OOC_XTAL { + display "SH clock crystal" + flavor data + legal_values 9000000 to 66000000 + default_value 33000000 + no_define + description " + This option specifies the frequency of the crystal all + other clocks are derived from." + } + + cdl_option CYGHWR_HAL_SH_OOC_CKIO { + display "SH clock CKIO output enable" + default_value 1 + description " + This selects whether CKIO output is enabled." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_1 { + display "SH clock PLL circuit 1" + flavor data + default_value 6 + legal_values { 0 6 } + description " + This selects whether PLL1 is enabled." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_2 { + display "SH clock PLL circuit 2" + flavor data + default_value 1 + legal_values { 0 1 } + description " + This selects whether PLL2 is enabled." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC { + display "SH clock divider, core" + flavor data + default_value 1 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the CPU core clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC { + display "SH clock divider, bus" + flavor data + default_value 8 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the bus clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC { + display "SH clock divider, peripheral" + flavor data + default_value 8 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the peripheral clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE { + display "SH clock mode" + flavor data + default_value 2 + legal_values { 0 1 2 3 4 5 } + description " + This option must mirror the clock mode hardwired on + the MD0-MD2 pins of the CPU in order to correctly + initialize the FRQCR register." + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "sh-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7750_cq7750_ram" : \ + "sh_sh7750_cq7750_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.ldi>" : \ + "<pkgconf/mlt_sh_sh7750_cq7750_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.h>" : \ + "<pkgconf/mlt_sh_sh7750_cq7750_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + parent CYGPKG_HAL_ROM_MONITOR + requires !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + description " + Support can be enabled for boot ROMs or ROM monitors which contain + GDB stubs. This support changes various eCos semantics such as + the encoding of diagnostic output, and the overriding of hardware + interrupt vectors." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/hal_diag.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-04-24 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// Simple LED control. +externC void hal_diag_led_on( void ); +externC void hal_diag_led_off( void ); + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Wed Nov 01 08:48:23 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x8008000) +#define CYGMEM_REGION_ram_SIZE (0xff8000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x9000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_ram.ldi @@ -0,0 +1,26 @@ +// eCos memory layout - Wed Nov 01 08:48:23 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x8008000, LENGTH = 0xff8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (ram, 0x8008000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 8008000 ff8000 0 ! +section vectors 0 1 0 1 1 1 1 1 8008000 8008000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Wed Nov 01 08:47:52 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x8000200) +#define CYGMEM_REGION_ram_SIZE (0xfffe00) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x80000000) +#define CYGMEM_REGION_rom_SIZE (0x100000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x9000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_rom.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Wed Nov 01 08:47:52 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x8000200, LENGTH = 0xfffe00 + rom : ORIGIN = 0x80000000, LENGTH = 0x100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0x80000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x8000200, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/pkgconf/mlt_sh_sh7750_cq7750_rom.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 8000200 fffe00 0 ! +region rom 80000000 100000 1 ! +section data 0 1 1 1 1 1 0 0 8000200 bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section vectors 0 1 0 1 1 1 1 1 80000000 80000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/platform.inc @@ -0,0 +1,228 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## SH/CQ7750 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:Ryozaburo Suzuki +## Date: 2000-04-18 +## Purpose: SH/CQ7750 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the SH/CQ7750 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/sh_offsets.inc> +#include <cyg/hal/sh_regs.h> + +#------------------------------------------------------------------------------ +# Hardware initialization. + + .macro hal_hardware_init + // Set up the Bus State Controller + mova BSC_settings_table,r0 + mov r0,r3 +1: mov.l @r3+,r0 // Address (or zero) + mov r0,r2 + cmp/eq #0,r0 + bt 4f + mov.l @r3+,r1 // data + mov.l @r3+,r0 // byte or word or long? + + cmp/eq #0,r0 // byte + bt 2f + + cmp/eq #1,r0 // word + bt 3f + + bra 1b // long + mov.l r1,@r2 // delay slot + +2: bra 1b + mov.b r1,@r2 // delay slot + +3: bra 1b + mov.w r1,@r2 // delay slot + + .align 2 + +BSC_settings_table: + # BCR1: + .long CYGARC_REG_BCR1 + .long 0x0020000c + .long 2 + # BCR2: + .long CYGARC_REG_BCR2 + .long 0x35F8 + .long 1 + # WCR1: + .long CYGARC_REG_WCR1 + .long 0x77117121 + .long 2 + # WCR2: + .long CYGARC_REG_WCR2 + .long 0xFC8AE520 + .long 2 + # WCR3: + .long CYGARC_REG_WCR3 + .long 0x07117101 + .long 2 + # PCR: + .long CYGARC_REG_PCR + .long 0x0000 + .long 1 + # RTCNT: + .long CYGARC_REG_RTCNT + .long 0xa500 + .long 1 + # RTCOR: + .long CYGARC_REG_RTCOR + .long 0xa53b + .long 1 + # RFCR: + .long CYGARC_REG_RFCR + .long 0xa400 + .long 1 + # RTCSR: + .long CYGARC_REG_RTCSR + .long 0xa508 + .long 1 + # MCR: + .long CYGARC_REG_MCR + .long 0x10192194 + .long 2 + # SDMR2: + .long CYGARC_REG_SDMR2 + .long 0xaa + .long 0 + # MCR: + .long CYGARC_REG_MCR + .long 0x50192194 + .long 2 + # SDMR2: + .long CYGARC_REG_SDMR2 + .long 0xaa + .long 0 + # Table end + .long 0 + + .align 2 +4: + .endm + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_SH_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + mov.l $_hal_vsr_table_p,r3 + # Write exception vectors + mov.l $_cyg_hal_default_exception_vsr_p,r4 + mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5 +1: mov.l r4,@r3 + add #4,r3 + dt r5 + bf 1b + # Write interrupt vector + mov.l $_cyg_hal_default_interrupt_vsr_p,r4 + mov.l r4,@r3 + bra 2f + nop + .align 2 + +$_cyg_hal_default_exception_vsr_p: + .long _cyg_hal_default_exception_vsr +$_cyg_hal_default_interrupt_vsr_p: + .long _cyg_hal_default_interrupt_vsr + + .extern _hal_vsr_table +$_hal_vsr_table_p: + .long _hal_vsr_table + +2: + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + # Write interrupt vector + mov.l $_hal_vsr_table_p,r3 + mov.l $_cyg_hal_default_interrupt_vsr_p,r4 + mov.l r4,@r3 + bra 2f + nop + .align 2 + +$_cyg_hal_default_interrupt_vsr_p: + .long _cyg_hal_default_interrupt_vsr + + .extern _hal_vsr_table +$_hal_vsr_table_p: + .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4 + +2: + .endm + +#else + + .macro hal_mon_init + .endm + +#endif + + +#define CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGONCE_HAL_PLATFORM_INC
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/plf_cache.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform specific cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-31 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/plf_intr.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, +// Date: 2000-10-31 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the CQ7750 board. +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +//-------------------------------------------------------------------------- + +// No platform specific stuff at present. + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/include/plf_stub.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-05-18 +// Purpose: Platform HAL stub support for Hitachi/CQ boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#include <cyg/hal/sh_stub.h> // architecture stub support + +#include <cyg/hal/hal_diag.h> // hal_diag_led_on + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +//---------------------------------------------------------------------------- +// Stub initializer. +#ifdef CYGSEM_HAL_ROM_MONITOR +# define HAL_STUB_PLATFORM_INIT() hal_diag_led_on() +#else +# define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT +#endif + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//---------------------------------------------------------------------------- +// Reset. +// Block interrupts and cause an exception. This forces a reset. +#define HAL_STUB_PLATFORM_RESET() \ + asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL)) + +#define HAL_STUB_PLATFORM_RESET_ENTRY 0xa0000000 + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/src/hal_diag.c @@ -0,0 +1,218 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jskov +// Contributors: nickg, jskov +// Date: 1999-03-23 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_diag.h> // our header. + +#include <cyg/infra/cyg_type.h> // base types, externC +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // calling interface API +#include <cyg/hal/hal_intr.h> // Interrupt macros +#include <cyg/hal/sh4_scif.h> // driver API +#include <cyg/hal/hal_misc.h> // Helper functions + +#define SCI_BASE ((cyg_uint8*)0xffe80000) + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_scif_init(0, 0, CYGNUM_HAL_INTERRUPT_SCIF_RXI, SCI_BASE); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +//============================================================================= +// Led control +//============================================================================= +#define LED 0xb4000000 + +void +hal_diag_led_on( void ) +{ + HAL_WRITE_UINT8(LED, 0x18); +} + +void +hal_diag_led_off( void ) +{ + HAL_WRITE_UINT8(LED, 0); +} + +//============================================================================= +// Compatibility with older stubs +//============================================================================= + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +static channel_data_t channel = { (cyg_uint8*)SCI_BASE, 0, 0}; + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + +#define CYG_HAL_DIAG_GDB + +#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + +#define CYG_HAL_DIAG_GDB + +#endif + +//----------------------------------------------------------------------------- + +void hal_diag_init(void) +{ + cyg_hal_plf_scif_init_channel(&channel); +} + +void +hal_diag_write_char_serial( char c ) +{ + cyg_hal_plf_scif_putc(&channel, c); +} + +void +hal_diag_read_char(char *c) +{ + *c = (char) cyg_hal_plf_scif_getc(&channel); +} + +// Packet function +void +hal_diag_write_char(char c) +{ +#ifdef CYG_HAL_DIAG_GDB + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + char c1; + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + cyg_hal_plf_scif_putc(&channel, '$'); + cyg_hal_plf_scif_putc(&channel, 'O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + cyg_hal_plf_scif_putc(&channel, h); + cyg_hal_plf_scif_putc(&channel, l); + csum += h; + csum += l; + } + cyg_hal_plf_scif_putc(&channel, '#'); + cyg_hal_plf_scif_putc(&channel, hex[(csum>>4)&0xF]); + cyg_hal_plf_scif_putc(&channel, hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. + c1 = (char) cyg_hal_plf_scif_getc(&channel); + + if( c1 == '+' ) + break; // a good acknowledge + + // Check for user break. + if( cyg_hal_is_break( &c1, 1 ) ) + cyg_hal_user_break( NULL ); + + // otherwise, loop round again + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + } +#else // CYG_HAL_DIAG_GDB + cyg_hal_plf_scif_putc(&channel, c); +#endif +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/cq7750/current/src/plf_misc.c @@ -0,0 +1,57 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov,nickg, jlarmour +// Date: 1999-10-13 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_if.h> // interfacing API + +//-------------------------------------------------------------------------- +void +hal_platform_init(void) +{ + hal_if_init(); +} + +//-------------------------------------------------------------------------- +// eof plf_misc.c
deleted file mode 100644 --- a/packages/hal/sh/edk/current/ChangeLog +++ /dev/null @@ -1,356 +0,0 @@ -2000-10-20 Jonathan Larmour <jlarmour@redhat.com> - - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_rom.h: - * include/pkgconf/mlt_sh_edk7708_romram.h: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_rom.ldi: - * include/pkgconf/mlt_sh_edk7708_romram.ldi: - Regenerated with updated host tools - -2000-10-17 Jesper Skov <jskov@redhat.com> - - * include/pkgconf/mlt_sh_edk7708_ram.h: Adding heap1. - * include/pkgconf/mlt_sh_edk7708_ram.mlt: Ditto. - * include/pkgconf/mlt_sh_edk7708_ram.ldi: Ditto. - * include/pkgconf/mlt_sh_edk7708_rom.h: Ditto. - * include/pkgconf/mlt_sh_edk7708_rom.mlt: Ditto. - * include/pkgconf/mlt_sh_edk7708_rom.ldi: Ditto. - * include/pkgconf/mlt_sh_edk7708_romram.h: Ditto. - * include/pkgconf/mlt_sh_edk7708_romram.mlt: Ditto. - * include/pkgconf/mlt_sh_edk7708_romram.ldi: Ditto. - -2000-10-10 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Fix legal OCC ranges. - -2000-09-26 Jesper Skov <jskov@redhat.com> - - * include/platform.inc: Use calculated FRQCR init value. - - * cdl/hal_sh_edk7708.cdl: Updated clock options. - -2000-07-07 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Require sub-variant package. - -2000-06-29 Jesper Skov <jskov@redhat.com> - - * src/hal_diag.c: serial driver API changes. - -2000-06-28 Jesper Skov <jskov@redhat.com> - - * src/hal_diag.c: Include hal_if file. - -2000-06-28 Jesper Skov <jskov@redhat.com> - - * src/plf_misc.c: - * src/hal_diag.c: - * src/plf_stub.c: [deleted] - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - * include/pkgconf/mlt_sh_edk7708_rom.h: - * include/pkgconf/mlt_sh_edk7708_rom.ldi: - * include/pkgconf/mlt_sh_edk7708_rom.mlt: - * include/pkgconf/mlt_sh_edk7708_romram.h: - * include/pkgconf/mlt_sh_edk7708_romram.ldi: - * include/pkgconf/mlt_sh_edk7708_romram.mlt: - * include/plf_stub.h: - * include/hal_diag.h: - * cdl/hal_sh_edk7708.cdl: - Changed to use virtual vector table. - -1999-06-19 John Dallaway <jld@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Tidy display strings. - -2000-04-12 Jesper Skov <jskov@redhat.com> - - * src/hal_diag.c: Output text raw if configuration requires it. - - * include/platform.inc: - * src/edk.S: [deleted] - * cdl/hal_sh_edk7708.cdl: - Hardware init code moved to platform.inc in order to allow ROMRAM - startup. - - * include/pkgconf/mlt_sh_edk7708_romram.h: - * include/pkgconf/mlt_sh_edk7708_romram.mlt: - * include/pkgconf/mlt_sh_edk7708_romram.ldi: - * cdl/hal_sh_edk7708.cdl: - Add ROMRAM startup option. - -2000-04-06 Jonathan Larmour <jlarmour@redhat.co.uk> - - * cdl/hal_sh_edk7708.cdl: Use -g now that toolchains work with that - (and in fact new toolchains no longer work with -ggdb) - -2000-04-06 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Define vsr base location. - -2000-04-04 Jesper Skov <jskov@redhat.com> - - * src/hal_diag.c (hal_diag_write_char): Add GDB critical IO region - handling. - -2000-03-20 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Added board speed variable. - -2000-03-09 Jesper Skov <jskov@redhat.com> - - * src/hal_diag.c: Fix compiler warning. - -2000-02-28 Jesper Skov <jskov@redhat.com> - - * include/platform.inc: Use sh_offsets instead of C header. - -2000-02-18 Jonathan Larmour <jlarmour@redhat.co.uk> - - * cdl/hal_sh_edk7708.cdl (CYGBLD_BUILD_GDB_STUBS): When - building stubs, define every dependency required here rather than - in the template - -2000-02-17 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: - Go back to -ggdb. -gstabs don't provide enough info for - source-level debugging. - - * include/pkgconf/mlt_sh_edk7708_rom.h: - * include/pkgconf/mlt_sh_edk7708_rom.ldi: - * include/pkgconf/mlt_sh_edk7708_rom.mlt: - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - Don't use . assignment due to tools problem. - -2000-02-16 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Added LE support. - -2000-02-15 Jesper Skov <jskov@redhat.com> - - * misc/STUBS_config: - * include/pkgconf/mlt_sh_edk7708_rom.ldi: - * include/pkgconf/mlt_sh_edk7708_rom.mlt: - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - Updated for new stubs scheme. - - * cdl/hal_sh_edk7708.cdl: Removed stubs startup. - Use -gstabs instead of -ggdb to work around problem with GDB. - -2000-02-10 Jesper Skov <jskov@redhat.com> - - * include/plf_stub.h: - HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT - -2000-02-07 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: use cpu flags when linking. - -2000-02-03 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Implements stubs. - -2000-01-27 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Moved part of stubs build rule to - common HAL. Changed description. - -2000-01-26 Jesper Skov <jskov@redhat.com> - - * cdl/hal_sh_edk7708.cdl: Fix display string. - -2000-01-24 Jesper Skov <jskov@cygnus.co.uk> - - * cdl/hal_sh_edk7708.cdl: Add stubs build rule. - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - * include/pkgconf/mlt_sh_edk7708_stubs.ldi: - * include/pkgconf/mlt_sh_edk7708_stubs.h: - * include/pkgconf/mlt_sh_edk7708_stubs.mlt: - Give stub more RAM. - -2000-01-24 John Dallaway <jld@cygnus.co.uk> - - * cdl/*.cdl: - - Remove obsolete option CYGTST_TESTING_IDENTIFIER. - -2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> - - * cdl/*.cdl: Add descriptions to a number of options &c which were - lacking same, also tidied up other typos as noticed en passant. - -2000-01-18 Jesper Skov <jskov@cygnus.co.uk> - CR 902066 - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - * include/pkgconf/mlt_sh_edk7708_ram.h: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - Correct RAM size. - -1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * src/plf_misc.c (cyg_hal_user_break): Rename - CYG_HAL_USE_ROM_MONITOR_GDB_STUBS -> CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs - - * cdl/hal_sh_edk7708.cdl: Don't need to define CYG_HAL_SH_SH7708 any - more - Add new platform-specific CYGSEM_HAL_USE_ROM_MONITOR option to - control ROM monitor support - -1999-12-20 Gary Thomas <gthomas@cygnus.co.uk> - - * cdl/hal_sh_edk7708.cdl: Add -Wl for linker options. - -1999-11-25 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/mlt_sh_edk7708_stubs.h: - * include/pkgconf/mlt_sh_edk7708_rom.h: - * include/pkgconf/mlt_sh_edk7708_ram.h: New file(s). - -1999-11-02 Jesper Skov <jskov@cygnus.co.uk> - - * cdl/hal_sh_edk7708.cdl: Use define_proc for CPU define. - -1999-11-01 Jesper Skov <jskov@cygnus.co.uk> - - * cdl/hal_sh_edk7708.cdl: Use define_proc for const header defs. - -1999-10-29 Jesper Skov <jskov@cygnus.co.uk> - - * cdl/hal_sh_edk7708.cdl: Added. - -1999-10-13 Jesper Skov <jskov@cygnus.co.uk> - - * src/hal_diag.c (hal_diag_write_char): - * src/plf_misc.c: - * src/PKGconf.mak (COMPILE): - Added user breakpoint handling. - -1999-09-02 Jesper Skov <jskov@cygnus.co.uk> - - * misc/STUBS_config: Also disable kernel support in HAL. - -1999-08-17 Jesper Skov <jskov@cygnus.co.uk> - - * misc/STUBS_config: Added. - -1999-06-18 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/hal_sh_edk7708.h: Consistent EDK7708 naming. - -1999-06-01 Jesper Skov <jskov@cygnus.co.uk> - - * src/hal_diag.c (hal_diag_write_char): Don't look for 0x03 - chars. It doesn't work well. Better the dedicated magic handles - C-c. - - * src/edk.S: Cleaned up memory controller setup. - -1999-05-31 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/hal_sh_edk7708.h: Removed FIX ME. - - * src/edk.S: Fixed delay-slot problem. - -1999-05-28 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/hal_sh_edk7708.h: Fixed platform name. - - * include/pkgconf/mlt_sh_edk7708_rom.ldi: - * include/pkgconf/mlt_sh_edk7708_rom.mlt: - * include/pkgconf/mlt_sh_edk7708_stubs.ldi: - * include/pkgconf/mlt_sh_edk7708_stubs.mlt: - * include/pkgconf/mlt_sh_edk7708_ram.ldi: - * include/pkgconf/mlt_sh_edk7708_ram.mlt: - Fixed memory layout and generated MLT files. - -1999-05-28 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/hal_sh_edk.h: [deleted] - * include/pkgconf/mlt_sh_edk_ram.ldi: [deleted] - * include/pkgconf/mlt_sh_edk_ram.mlt: [deleted] - * include/pkgconf/mlt_sh_edk_rom.ldi: [deleted] - * include/pkgconf/mlt_sh_edk_stubs.ldi: [deleted] - * include/pkgconf/hal_sh_edk7708.h: [added] - * include/pkgconf/mlt_sh_edk7708_ram.ldi: [added] - * include/pkgconf/mlt_sh_edk7708_ram.mlt: [added] - * include/pkgconf/mlt_sh_edk7708_rom.ldi: [added] - * include/pkgconf/mlt_sh_edk7708_rom.mlt: [added] - * include/pkgconf/mlt_sh_edk7708_stubs.ldi:[added] - * include/pkgconf/mlt_sh_edk7708_stubs.mlt:[added] - * src/PKGconf.mak: - Renamed SH platform package to edk7708. - -1999-05-21 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/hal_sh_edk.h (CYGNUM_HAL_RTC_PERIOD): The timer - is running at 1/4 of the peripheral clock. - - * include/plf_stub.h: Added RESET code. - - * include/pkgconf/hal_sh_edk.h: Added RTC data for the edk board. - -1999-05-20 John Dallaway <jld@cygnus.co.uk> - - * include/pkgconf/mlt_sh_edk_ram.mlt: Working MLT-generated - version. - -1999-05-20 Jesper Skov <jskov@cygnus.co.uk> - - * Moved files to CVS trunk. - -1999-05-19 Jesper Skov <jskov@cygnus.co.uk> - - * src/edk.S (_hal_hardware_init): Fix a few mistakes. - - * include/plf_stub.h: Enable led in stub init. - - * include/pkgconf/mlt_sh_edk_stubs.ldi: - * include/pkgconf/mlt_sh_edk_rom.ldi: - Added. - Moved RAM region to the end of the chunk and made it bigger. - - * src/edk.S (_hal_hardware_init): Added Bus State Controller - initialization. - -1999-05-19 Jesper Skov <jskov@cygnus.co.uk> - - * Most things working now. Will start keeping track of changes. - -1999-04-22 Jesper Skov <jskov@lassi.cygnus.co.uk> - - * Set up directory structure. - -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//===========================================================================
deleted file mode 100644 --- a/packages/hal/sh/edk/current/cdl/hal_sh_edk7708.cdl +++ /dev/null @@ -1,312 +0,0 @@ -# ==================================================================== -# -# hal_sh_edk7708.cdl -# -# EDK7708 board HAL package configuration data -# -# ==================================================================== -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.1 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://www.redhat.com/ -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -# ==================================================================== -######DESCRIPTIONBEGIN#### -# -# Author(s): jskov -# Original data: jskov -# Contributors: -# Date: 1999-10-29 -# -#####DESCRIPTIONEND#### -# -# ==================================================================== - -cdl_package CYGPKG_HAL_SH_EDK7708 { - display "Hitachi EDK/SH7708 board" - parent CYGPKG_HAL_SH - requires CYGPKG_HAL_SH_7708 - define_header hal_sh_edk7708.h - include_dir cyg/hal - description " - The edk HAL package provides the support needed to run - eCos on a Hitachi SH3 EDK7708 board." - - compile hal_diag.c plf_misc.c - - implements CYGINT_HAL_DEBUG_GDB_STUBS - implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK - implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT - - define_proc { - puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>" - puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_edk7708.h>" - - puts $::cdl_header "#define CYGNUM_HAL_SH_SH3_SCI_PORTS 1" - puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000" - puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100" - } - - cdl_component CYG_HAL_STARTUP { - display "Startup type" - flavor data - legal_values {"RAM" "ROM" "ROMRAM"} - default_value {"RAM"} - no_define - define -file system.h CYG_HAL_STARTUP - description " - When targetting the EDK7708 board it is possible to build - the system for either RAM bootstrap or ROM bootstrap. - RAM bootstrap generally requires that the board - is equipped with ROMs containing a suitable ROM monitor or - equivalent software that allows GDB to download the eCos - application on to the board. The ROM bootstrap typically - requires that the eCos application be blown into EPROMs or - equivalent technology. ROMRAM bootstrap is similar to ROM - bootstrap, but everything is copied to RAM before execution - starts thus improving performace, but at the cost of an - increased RAM footprint." - } - - cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { - display "Number of communication channels on the board" - flavor data - calculated 1 - } - - cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { - display "Debug serial port" - flavor data - legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 - default_value 0 - description " - The EDK/7708 board has only one serial port. This option - chooses which port will be used to connect to a host - running GDB." - } - - cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { - display "Diagnostic serial port" - flavor data - legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 - default_value 0 - description " - The EDK/7708 board has only one serial port. This option - chooses which port will be used for diagnostic output." - } - - cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS { - display "SH on-chip platform clock controls" - description " - The various clocks used by the system are derived from - these options." - flavor none - no_define - - cdl_option CYGHWR_HAL_SH_OOC_XTAL { - display "SH clock crystal" - flavor data - legal_values 8000000 to 50000000 - default_value 15000000 - no_define - description " - This option specifies the frequency of the crystal all - other clocks are derived from." - } - - cdl_option CYGHWR_HAL_SH_OOC_PLL_1 { - display "SH clock PLL circuit 1" - flavor data - default_value 1 - legal_values { 0 1 2 4 } - description " - This selects the multiplication factor provided by - PLL1. If PLL1 is disabled via CAP1, this option should - be set to zero." - } - - cdl_option CYGHWR_HAL_SH_OOC_PLL_2 { - display "SH clock PLL circuit 2" - flavor data - default_value 4 - legal_values { 0 1 4 } - no_define - description " - This selects the multiplication factor provided by - PLL2. If PLL2 is disabled via CAP2, this option should - be set to zero." - } - - cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 { - display "SH clock divider 1" - flavor data - default_value 1 - legal_values { 1 2 3 4 } - description " - This divider option affects the CPU core clock." - } - - cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_2 { - display "SH clock divider 2" - flavor data - default_value 4 - legal_values { 1 2 3 4 } - description " - This divider option affects the peripheral clock." - } - - cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE { - display "SH clock mode" - flavor data - default_value 2 - legal_values { 0 1 2 3 4 7 } - description " - This option must mirror the clock mode hardwired on - the MD0-MD2 pins of the CPU in order to correctly - initialize the FRQCR register." - } - } - - cdl_component CYGBLD_GLOBAL_OPTIONS { - display "Global build options" - flavor none - parent CYGPKG_NONE - no_define - description " - Global build options including control over - compiler flags, linker flags and choice of toolchain." - - - cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { - display "Global command prefix" - flavor data - no_define - default_value { "sh-elf" } - description " - This option specifies the command prefix used when - invoking the build tools." - } - - cdl_option CYGBLD_GLOBAL_CFLAGS { - display "Global compiler flags" - flavor data - no_define - default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } - description " - This option controls the global compiler flags which - are used to compile all packages by - default. Individual packages may define - options which override these global flags." - } - - cdl_option CYGBLD_GLOBAL_LDFLAGS { - display "Global linker flags" - flavor data - no_define - default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -nostdlib -Wl,--gc-sections -Wl,-static" } - description " - This option controls the global linker flags. Individual - packages may define options which override these global flags." - } - - cdl_option CYGBLD_BUILD_GDB_STUBS { - display "Build GDB stub ROM image" - default_value 0 - requires { CYG_HAL_STARTUP == "ROM" } - requires CYGSEM_HAL_ROM_MONITOR - requires CYGBLD_BUILD_COMMON_GDB_STUBS - requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT - requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT - requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT - requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM - no_define - description " - This option enables the building of the GDB stubs for the - board. The common HAL controls takes care of most of the - build process, but the final conversion from ELF image to - binary data is handled by the platform CDL, allowing - relocation of the data if necessary." - - make -priority 320 { - <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img - $(OBJCOPY) -O binary $< $@ - } - } - } - - cdl_component CYGHWR_MEMORY_LAYOUT { - display "Memory layout" - flavor data - no_define - calculated { CYG_HAL_STARTUP == "RAM" ? "sh_edk7708_ram" : \ - CYG_HAL_STARTUP == "ROM" ? "sh_edk7708_rom" : \ - "sh_edk7708_romram" } - - cdl_option CYGHWR_MEMORY_LAYOUT_LDI { - display "Memory layout linker script fragment" - flavor data - no_define - define -file system.h CYGHWR_MEMORY_LAYOUT_LDI - calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_edk7708_ram.ldi>" : \ - CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_edk7708_rom.ldi>" : \ - "<pkgconf/mlt_sh_edk7708_romram.ldi>" } - } - - cdl_option CYGHWR_MEMORY_LAYOUT_H { - display "Memory layout header file" - flavor data - no_define - define -file system.h CYGHWR_MEMORY_LAYOUT_H - calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_edk7708_ram.h>" : \ - CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_edk7708_rom.h>" : \ - "<pkgconf/mlt_sh_edk7708_romram.h>" } - } - } - - cdl_option CYGSEM_HAL_USE_ROM_MONITOR { - display "Work with a ROM monitor" - flavor booldata - legal_values { "GDB_stubs" } - default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } - requires { CYG_HAL_STARTUP == "RAM" } - parent CYGPKG_HAL_ROM_MONITOR - description " - Support can be enabled for boot ROMs or ROM monitors which contain - GDB stubs. This support changes various eCos semantics such as - the encoding of diagnostic output, and the overriding of hardware - interrupt vectors." - } - - cdl_option CYGSEM_HAL_ROM_MONITOR { - display "Behave as a ROM monitor" - flavor bool - default_value 0 - parent CYGPKG_HAL_ROM_MONITOR - requires { CYG_HAL_STARTUP == "ROM" } - description " - Enable this option if this program is to be used as a ROM monitor, - i.e. applications will be loaded into RAM on the board, and this - ROM monitor may process exceptions or interrupts generated from the - application. This enables features such as utilizing a separate - interrupt stack when exceptions are generated." - } -}
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/hal_diag.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef CYGONCE_HAL_HAL_DIAG_H -#define CYGONCE_HAL_HAL_DIAG_H - -//============================================================================= -// -// hal_diag.h -// -// HAL Support for Kernel Diagnostic Routines -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 1999-04-24 -// Purpose: HAL Support for Kernel Diagnostic Routines -// Description: Diagnostic routines for use during kernel development. -// Usage: #include <cyg/hal/hal_diag.h> -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> - -#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) - -#include <cyg/hal/hal_if.h> - -#define HAL_DIAG_INIT() hal_if_diag_init() -#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) -#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) - -#else // everything by steam - -//----------------------------------------------------------------------------- -// functions implemented in hal_diag.c - -externC void hal_diag_init(void); - -externC void hal_diag_write_char(char c); - -externC void hal_diag_read_char(char *c); - -//----------------------------------------------------------------------------- - -#define HAL_DIAG_INIT() hal_diag_init() - -#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) - -#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) - -#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG - -//----------------------------------------------------------------------------- -// Simple LED control. -externC void hal_diag_led_on( void ); -externC void hal_diag_led_off( void ); - -//----------------------------------------------------------------------------- -// end of hal_diag.h -#endif // CYGONCE_HAL_HAL_DIAG_H
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_ram.h +++ /dev/null @@ -1,17 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:50:36 2000 - -// This is a generated file - do not edit - -#ifndef __ASSEMBLER__ -#include <cyg/infra/cyg_type.h> -#include <stddef.h> - -#endif -#define CYGMEM_REGION_ram (0x8008000) -#define CYGMEM_REGION_ram_SIZE (0xf8000) -#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#ifndef __ASSEMBLER__ -extern char CYG_LABEL_NAME (__heap1) []; -#endif -#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_ram.ldi +++ /dev/null @@ -1,26 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:50:36 2000 - -// This is a generated file - do not edit - -#include <cyg/infra/cyg_type.inc> - -MEMORY -{ - ram : ORIGIN = 0x8008000, LENGTH = 0xf8000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_vectors (ram, 0x8008000, LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) - CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_ram.mlt +++ /dev/null @@ -1,12 +0,0 @@ -version 0 -region ram 8008000 f8000 0 ! -section vectors 0 1 0 1 1 1 1 1 8008000 8008000 text text ! -section text 0 4 0 1 0 1 0 1 fini fini ! -section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! -section rodata 0 8 0 1 0 1 0 1 fixup fixup ! -section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 1 0 1 data data ! -section data 0 8 0 1 0 1 0 1 bss bss ! -section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! -section heap1 0 8 0 0 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_rom.h +++ /dev/null @@ -1,20 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:51:04 2000 - -// This is a generated file - do not edit - -#ifndef __ASSEMBLER__ -#include <cyg/infra/cyg_type.h> -#include <stddef.h> - -#endif -#define CYGMEM_REGION_ram (0x8000200) -#define CYGMEM_REGION_ram_SIZE (0xffe00) -#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_rom (0xa0000000) -#define CYGMEM_REGION_rom_SIZE (0x20000) -#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) -#ifndef __ASSEMBLER__ -extern char CYG_LABEL_NAME (__heap1) []; -#endif -#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_rom.ldi +++ /dev/null @@ -1,27 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:51:04 2000 - -// This is a generated file - do not edit - -#include <cyg/infra/cyg_type.inc> - -MEMORY -{ - ram : ORIGIN = 0x8000200, LENGTH = 0xffe00 - rom : ORIGIN = 0xa0000000, LENGTH = 0x20000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_vectors (rom, 0xa0000000, LMA_EQ_VMA) - SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) - SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) - SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) - SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, 0x8000200, FOLLOWING (.gcc_except_table)) - SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) - CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_rom.mlt +++ /dev/null @@ -1,13 +0,0 @@ -version 0 -region ram 8000200 ffe00 0 ! -region rom a0000000 20000 1 ! -section data 0 1 1 1 1 1 0 0 8000200 bss ! -section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! -section heap1 0 8 0 0 0 0 0 0 ! -section vectors 0 1 0 1 1 1 1 1 a0000000 a0000000 text text ! -section text 0 4 0 1 0 1 0 1 fini fini ! -section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! -section rodata 0 8 0 1 0 1 0 1 fixup fixup ! -section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 0 0 1 data !
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_romram.h +++ /dev/null @@ -1,20 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:51:30 2000 - -// This is a generated file - do not edit - -#ifndef __ASSEMBLER__ -#include <cyg/infra/cyg_type.h> -#include <stddef.h> - -#endif -#define CYGMEM_REGION_ram (0x8000200) -#define CYGMEM_REGION_ram_SIZE (0xffe00) -#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_rom (0xa0000000) -#define CYGMEM_REGION_rom_SIZE (0x20000) -#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) -#ifndef __ASSEMBLER__ -extern char CYG_LABEL_NAME (__heap1) []; -#endif -#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_romram.ldi +++ /dev/null @@ -1,27 +0,0 @@ -// eCos memory layout - Fri Oct 20 09:51:30 2000 - -// This is a generated file - do not edit - -#include <cyg/infra/cyg_type.inc> - -MEMORY -{ - ram : ORIGIN = 0x8000200, LENGTH = 0xffe00 - rom : ORIGIN = 0xa0000000, LENGTH = 0x20000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_vectors (ram, 0x8000200, AT (0xa0000000)) - SECTION_text (ram, ALIGN (0x10), FOLLOWING (.vectors)) - SECTION_fini (ram, ALIGN (0x10), FOLLOWING (.text)) - SECTION_rodata1 (ram, ALIGN (0x10), FOLLOWING (.fini)) - SECTION_rodata (ram, ALIGN (0x10), FOLLOWING (.rodata1)) - SECTION_fixup (ram, ALIGN (0x10), FOLLOWING (.rodata)) - SECTION_gcc_except_table (ram, ALIGN (0x10), FOLLOWING (.fixup)) - SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) - SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) - CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/pkgconf/mlt_sh_edk7708_romram.mlt +++ /dev/null @@ -1,13 +0,0 @@ -version 0 -region ram 8000200 ffe00 0 ! -region rom a0000000 20000 1 ! -section vectors 0 10 1 1 1 1 1 1 8000200 a0000000 text text ! -section text 0 10 1 1 0 1 0 1 fini fini ! -section fini 0 10 1 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 10 1 1 0 1 0 1 rodata rodata ! -section rodata 0 10 1 1 0 1 0 1 fixup fixup ! -section fixup 0 10 1 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 10 1 1 0 1 0 1 data data ! -section data 0 10 1 1 0 1 0 0 bss ! -section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! -section heap1 0 8 0 0 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/platform.inc +++ /dev/null @@ -1,196 +0,0 @@ -#ifndef CYGONCE_HAL_PLATFORM_INC -#define CYGONCE_HAL_PLATFORM_INC -##============================================================================= -## -## platform.inc -## -## SH/EDK7708 board assembler header file -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.0 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://sourceware.cygnus.com/ecos -# -# Software distributed under the License is distributed on an -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): jskov -## Contributors:jskov -## Date: 2000-02-02 -## Purpose: SH/EDK7708 board definitions. -## Description: This file contains various definitions and macros that are -## useful for writing assembly code for the SH/EDK7708 board. -## Usage: -## #include <cyg/hal/platform.inc> -## ... -## -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <pkgconf/hal.h> - -#include <cyg/hal/sh_regs.h> -#include <cyg/hal/sh_offsets.inc> - -#------------------------------------------------------------------------------ -# Hardware initialization. - - .macro hal_hardware_init - // Set up the Bus State Controller - mova BSC_settings_table,r0 - mov r0,r3 -1: mov.w @r3+,r0 // Address (or zero) - cmp/eq #0,r0 - bt 2f - mov.w @r3+,r1 // data - bra 1b - mov.w r1,@r0 // delay slot - - .align 2 -BSC_settings_table: - # These are the settings set by the Hitachi ROM Monitor. - - .word CYGARC_REG_FRQCR - .word CYGARC_REG_FRQCR_INIT - - # BCR2: Bus size of areas 1-6 to 32 bits - .word CYGARC_REG_BCR2 - .word 0x3ffc - # BCR1: Areas 2 and 3 are SDRAM - .word CYGARC_REG_BCR1 - .word 0x080c - # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!] - .word CYGARC_REG_BCR2 - .word 0x3ffc - # WCR1: 3 wait-state cycles inserted for all areas - .word CYGARC_REG_WCR1 - .word 0x3fff - # WCR2: extra wait states and full pitch for burst - .word CYGARC_REG_WCR2 - .word 0xffd7 - # MCR: RAS/CAS & burst timing area 2/3 - .word CYGARC_REG_MCR - .word 0x963c - # RTCNT: refresh counter (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCNT - .word (0xa500 | 0x0000) - # RTCOR: refresh time constant (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCOR - .word (0xa500 | 0x003b) - # RFCR: refresh count register (needs a4 in top byte to accept write) - .word CYGARC_REG_RFCR - .word (0xa400 | 0x0000) - # RTCSR: refresh timer control (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCSR - .word (0xa500 | 0x0008) - - # Set SDMR to 0x220 - .word 0xd880 - .word 0 - - # Table end - .word 0 - - .align 2 -2: - .endm - -#------------------------------------------------------------------------------ -# Monitor initialization. - -#ifndef CYGPKG_HAL_SH_MON_DEFINED - -#if !defined(CYG_HAL_STARTUP_RAM) || \ - ( defined(CYG_HAL_STARTUP_RAM) && \ - !defined(CYGSEM_HAL_USE_ROM_MONITOR)) - - # If we are not starting up from RAM, or we are starting in - # RAM and NOT using a ROM monitor, initialize the VSR table. - - .macro hal_mon_init - mov.l $_hal_vsr_table_p,r3 - # Write exception vectors - mov.l $_cyg_hal_default_exception_vsr_p,r4 - mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5 -1: mov.l r4,@r3 - add #4,r3 - dt r5 - bf 1b - # Write interrupt vector - mov.l $_cyg_hal_default_interrupt_vsr_p,r4 - mov.l r4,@r3 - bra 2f - nop - .align 2 - -$_cyg_hal_default_exception_vsr_p: - .long _cyg_hal_default_exception_vsr -$_cyg_hal_default_interrupt_vsr_p: - .long _cyg_hal_default_interrupt_vsr - - .extern _hal_vsr_table -$_hal_vsr_table_p: - .long _hal_vsr_table - -2: - .endm - -#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) - - # Initialize the VSR table entries - # We only take control of the interrupt vector, - # the rest are left to the ROM for now... - - .macro hal_mon_init - # Write interrupt vector - mov.l $_hal_vsr_table_p,r3 - mov.l $_cyg_hal_default_interrupt_vsr_p,r4 - mov.l r4,@r3 - bra 2f - nop - .align 2 - -$_cyg_hal_default_interrupt_vsr_p: - .long _cyg_hal_default_interrupt_vsr - - .extern _hal_vsr_table -$_hal_vsr_table_p: - .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4 - -2: - .endm - -#else - - .macro hal_mon_init - .endm - -#endif - - -#define CYGPKG_HAL_SH_MON_DEFINED - -#endif // CYGPKG_HAL_SH_MON_DEFINED - -#endif // CYGONCE_HAL_PLATFORM_INC
deleted file mode 100644 --- a/packages/hal/sh/edk/current/include/plf_stub.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef CYGONCE_HAL_PLF_STUB_H -#define CYGONCE_HAL_PLF_STUB_H - -//============================================================================= -// -// plf_stub.h -// -// Platform header for GDB stub support. -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 1999-05-18 -// Purpose: Platform HAL stub support for Hitachi/EDK boards. -// Usage: #include <cyg/hal/plf_stub.h> -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/system.h> -#include <pkgconf/hal.h> - -#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - -#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC - -#include <cyg/hal/sh_stub.h> // architecture stub support - -#include <cyg/hal/hal_diag.h> // hal_diag_led_on - -//---------------------------------------------------------------------------- -// Define some platform specific communication details. This is mostly -// handled by hal_if now, but we need to make sure the comms tables are -// properly initialized. - -externC void cyg_hal_plf_comms_init(void); - -#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() - -#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) -#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 - -//---------------------------------------------------------------------------- -// Stub initializer. -#ifdef CYGSEM_HAL_ROM_MONITOR -# define HAL_STUB_PLATFORM_INIT() hal_diag_led_on() -#else -# define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT -#endif - -#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - -//---------------------------------------------------------------------------- -// Reset. -// Block interrupts and cause an exception. This forces a reset. -#define HAL_STUB_PLATFORM_RESET() \ - asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL)) - -#define HAL_STUB_PLATFORM_RESET_ENTRY 0xa0000000 - -//----------------------------------------------------------------------------- -#endif // CYGONCE_HAL_PLF_STUB_H -// End of plf_stub.h
deleted file mode 100644 --- a/packages/hal/sh/edk/current/misc/STUBS_config +++ /dev/null @@ -1,84 +0,0 @@ -#! /bin/sh -# Configure SH/edk7708 eCos to create EDK7708 GDB stubs -# Ensure that PATH include the directory where the SH tools reside. -# -# Run from an empty temporary directory with one argument: the path to -# the packages directory (i.e., where pkgconf.tcl lives). -# -# Output will be ./stubrom.bin which is suitable for burning into ROM. - -if ( echo | tclsh ) 2>/dev/null ; then - TCL=tclsh -elif ( echo | cygtclsh80 ) 2>/dev/null ; then - TCL=cygtclsh80 -else - echo Could not find TCL interpreter - exit 1 -fi - -$TCL $1/pkgconf.tcl \ - --target=sh --platform=edk7708 --startup=rom \ - --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ - --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ - --disable CYGPKG_ERROR --disable CYGPKG_IO \ - --disable CYGPKG_IO_SERIAL --disable CYGPKG_DEVICES_WALLCLOCK \ - --disable CYGPKG_DEVICES_WATCHDOG - -patch <<END_OF_PATCH -p0 ---- pkgconf/hal.h.orig Thu Feb 10 09:05:07 2000 -+++ pkgconf/hal.h Thu Feb 10 09:04:56 2000 -@@ -122,7 +122,7 @@ - } - - }}CFG_DATA */ --#define CYGFUN_HAL_COMMON_KERNEL_SUPPORT -+#undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT - #undef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL - - #ifdef CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL -@@ -243,7 +243,7 @@ - #define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK - #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 - #undef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING --#define CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT -+#undef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT - #undef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN - #undef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS - -@@ -272,7 +272,7 @@ - } - - }}CFG_DATA */ --#define CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM -+#undef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM - - /* {{CFG_DATA - -@@ -423,10 +423,10 @@ - - }}CFG_DATA */ - --#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS -+#define CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - #undef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT --#define CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT --#define CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT -+#undef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT -+#undef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT - - /* - * NOTE: -@@ -522,7 +522,7 @@ - - - /* Enable this when configuring as a ROM monitor (i.e., stub) */ --#undef CYGSEM_HAL_ROM_MONITOR -+#define CYGSEM_HAL_ROM_MONITOR - - #include CYGBLD_HAL_TARGET_H - #include CYGBLD_HAL_PLATFORM_H -END_OF_PATCH - -make -make -C hal/common/current/src/stubrom -sh-elf-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.bin
deleted file mode 100644 --- a/packages/hal/sh/edk/current/src/edk.S +++ /dev/null @@ -1,117 +0,0 @@ -##============================================================================= -## -## edk.S -## -## EDK board hardware setup -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.1 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://www.redhat.com/ -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): jskov -## Contributors:jskov -## Date: 1999-05-03 -## Purpose: EDK7708 board hardware setup -## Description: This file contains any code needed to initialize the -## hardware on a Hitachi SH3 EDK7708 board. -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <pkgconf/hal.h> -#include <cyg/hal/sh_regs.h> - - .globl _hal_hardware_init -_hal_hardware_init: - - // Set up the Bus State Controller - mov.l $BSC_settings_table,r3 -1: mov.w @r3+,r0 // Address (or zero) - cmp/eq #0,r0 - bt 2f - mov.w @r3+,r1 // data - bra 1b - mov.w r1,@r0 // delay slot - -2: - rts - nop - - .align 2 -$BSC_settings_table: - .long BSC_settings_table -BSC_settings_table: - # These are the settings set by the Hitachi ROM Monitor. - - # BCR2: Bus size of areas 1-6 to 32 bits - .word CYGARC_REG_BCR2 - .word 0x3ffc - # BCR1: Areas 2 and 3 are SDRAM - .word CYGARC_REG_BCR1 - .word 0x080c - # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!] - .word CYGARC_REG_BCR2 - .word 0x3ffc - # WCR1: 3 wait-state cycles inserted for all areas - .word CYGARC_REG_WCR1 - .word 0x3fff - # WCR2: extra wait states and full pitch for burst - .word CYGARC_REG_WCR2 - .word 0xffd7 - # MCR: RAS/CAS & burst timing area 2/3 - .word CYGARC_REG_MCR - .word 0x963c -#if 0 - # DCR: RAS/CAS & burst timing area 2 - .word CYGARC_REG_DCR - .word 0x0000 - # PCR: PCMCIA disabled - .word CYGARC_REG_PCR - .word 0x0000 -#endif - # RTCNT: refresh counter (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCNT - .word (0xa500 | 0x0000) - # RTCOR: refresh time constant (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCOR - .word (0xa500 | 0x003b) - # RFCR: refresh count register (needs a4 in top byte to accept write) - .word CYGARC_REG_RFCR - .word (0xa400 | 0x0000) - # RTCSR: refresh timer control (needs a5 in top byte to accept write) - .word CYGARC_REG_RTCSR - .word (0xa500 | 0x0008) - - # Set SDMR to 0x220 - .word 0xd880 - .word 0 - - # Table end - .word 0 - -#------------------------------------------------------------------------------ -# end of edk.S
deleted file mode 100644 --- a/packages/hal/sh/edk/current/src/hal_diag.c +++ /dev/null @@ -1,219 +0,0 @@ -//============================================================================= -// -// hal_diag.c -// -// HAL diagnostic output code -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg, jskov -// Contributors: nickg, jskov -// Date: 1999-03-23 -// Purpose: HAL diagnostic output -// Description: Implementations of HAL diagnostic output support. -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#include <cyg/hal/hal_diag.h> // our header. - -#include <cyg/infra/cyg_type.h> // base types, externC -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_if.h> // Calling interface -#include <cyg/hal/hal_intr.h> // Interrupt macros -#include <cyg/hal/sh3_sci.h> // driver API -#include <cyg/hal/hal_misc.h> // Helper functions - -#define SCI_BASE ((cyg_uint8*)0xfffffe80) - -//----------------------------------------------------------------------------- - -#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ - || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) - -void -cyg_hal_plf_comms_init(void) -{ - static int initialized = 0; - - if (initialized) - return; - - initialized = 1; - - cyg_hal_plf_sci_init(0, 0, CYGNUM_HAL_INTERRUPT_SCI_RXI, SCI_BASE); -} - -#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES - -//============================================================================= -// Led control -//============================================================================= -#define LED_ON 0x04000000 -#define LED_OFF 0x18000000 - -void -hal_diag_led_on( void ) -{ - HAL_WRITE_UINT8(LED_ON, 0); -} - -void -hal_diag_led_off( void ) -{ - HAL_WRITE_UINT8(LED_OFF, 0); -} - - -//============================================================================= -// Compatibility with older stubs -//============================================================================= - -#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG - -static channel_data_t channel = { (cyg_uint8*)SCI_BASE, 0, 0}; - -#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) -#include <cyg/hal/hal_stub.h> // hal_output_gdb_string -#endif - -#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) - -#define CYG_HAL_DIAG_GDB - -#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) - -#define CYG_HAL_DIAG_GDB - -#endif - -//----------------------------------------------------------------------------- - -void hal_diag_init(void) -{ - cyg_hal_plf_sci_init_channel(&channel); -} - -void -hal_diag_write_char_serial( char c ) -{ - cyg_hal_plf_sci_putc(&channel, c); -} - -void -hal_diag_read_char(char *c) -{ - *c = (char) cyg_hal_plf_sci_getc(&channel); -} - -// Packet function -void -hal_diag_write_char(char c) -{ -#ifdef CYG_HAL_DIAG_GDB - static char line[100]; - static int pos = 0; - - // No need to send CRs - if( c == '\r' ) return; - - line[pos++] = c; - - if( c == '\n' || pos == sizeof(line) ) - { - CYG_INTERRUPT_STATE old; - - // Disable interrupts. This prevents GDB trying to interrupt us - // while we are in the middle of sending a packet. The serial - // receive interrupt will be seen when we re-enable interrupts - // later. - -#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); -#else - HAL_DISABLE_INTERRUPTS(old); -#endif - - while(1) - { - char c1; - static char hex[] = "0123456789ABCDEF"; - cyg_uint8 csum = 0; - int i; - - cyg_hal_plf_sci_putc(&channel, '$'); - cyg_hal_plf_sci_putc(&channel, 'O'); - csum += 'O'; - for( i = 0; i < pos; i++ ) - { - char ch = line[i]; - char h = hex[(ch>>4)&0xF]; - char l = hex[ch&0xF]; - cyg_hal_plf_sci_putc(&channel, h); - cyg_hal_plf_sci_putc(&channel, l); - csum += h; - csum += l; - } - cyg_hal_plf_sci_putc(&channel, '#'); - cyg_hal_plf_sci_putc(&channel, hex[(csum>>4)&0xF]); - cyg_hal_plf_sci_putc(&channel, hex[csum&0xF]); - - // Wait for the ACK character '+' from GDB here and handle - // receiving a ^C instead. - c1 = (char) cyg_hal_plf_sci_getc(&channel); - - if( c1 == '+' ) - break; // a good acknowledge - - // Check for user break. - if( cyg_hal_is_break( &c1, 1 ) ) - cyg_hal_user_break( NULL ); - - // otherwise, loop round again - } - - pos = 0; - - // And re-enable interrupts -#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); -#else - HAL_RESTORE_INTERRUPTS(old); -#endif - } -#else // CYG_HAL_DIAG_GDB - cyg_hal_plf_sci_putc(&channel, c); -#endif -} -#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG - -//----------------------------------------------------------------------------- -// End of hal_diag.c
deleted file mode 100644 --- a/packages/hal/sh/edk/current/src/plf_misc.c +++ /dev/null @@ -1,57 +0,0 @@ -//========================================================================== -// -// plf_misc.c -// -// HAL platform miscellaneous functions -// -//========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors: jskov,nickg, jlarmour -// Date: 1999-10-13 -// Purpose: HAL miscellaneous functions -// Description: This file contains miscellaneous functions provided by the -// HAL. -// -//####DESCRIPTIONEND#### -// -//========================================================================== - -#include <pkgconf/hal.h> - -#include <cyg/hal/hal_if.h> // interfacing API - -//-------------------------------------------------------------------------- -void -hal_platform_init(void) -{ - hal_if_init(); -} - -//-------------------------------------------------------------------------- -// eof plf_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/ChangeLog @@ -0,0 +1,365 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * Moved HAL to edk7708. + +2000-10-31 Jesper Skov <jskov@redhat.com> + + * include/plf_intr.h: Added. + * include/plf_cache.h: Added. + +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_rom.h: + * include/pkgconf/mlt_sh_edk7708_romram.h: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_rom.ldi: + * include/pkgconf/mlt_sh_edk7708_romram.ldi: + Regenerated with updated host tools + +2000-10-17 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/mlt_sh_edk7708_ram.h: Adding heap1. + * include/pkgconf/mlt_sh_edk7708_ram.mlt: Ditto. + * include/pkgconf/mlt_sh_edk7708_ram.ldi: Ditto. + * include/pkgconf/mlt_sh_edk7708_rom.h: Ditto. + * include/pkgconf/mlt_sh_edk7708_rom.mlt: Ditto. + * include/pkgconf/mlt_sh_edk7708_rom.ldi: Ditto. + * include/pkgconf/mlt_sh_edk7708_romram.h: Ditto. + * include/pkgconf/mlt_sh_edk7708_romram.mlt: Ditto. + * include/pkgconf/mlt_sh_edk7708_romram.ldi: Ditto. + +2000-10-10 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Fix legal OCC ranges. + +2000-09-26 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: Use calculated FRQCR init value. + + * cdl/hal_sh_edk7708.cdl: Updated clock options. + +2000-07-07 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Require sub-variant package. + +2000-06-29 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: serial driver API changes. + +2000-06-28 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Include hal_if file. + +2000-06-28 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: + * src/hal_diag.c: + * src/plf_stub.c: [deleted] + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + * include/pkgconf/mlt_sh_edk7708_rom.h: + * include/pkgconf/mlt_sh_edk7708_rom.ldi: + * include/pkgconf/mlt_sh_edk7708_rom.mlt: + * include/pkgconf/mlt_sh_edk7708_romram.h: + * include/pkgconf/mlt_sh_edk7708_romram.ldi: + * include/pkgconf/mlt_sh_edk7708_romram.mlt: + * include/plf_stub.h: + * include/hal_diag.h: + * cdl/hal_sh_edk7708.cdl: + Changed to use virtual vector table. + +1999-06-19 John Dallaway <jld@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Tidy display strings. + +2000-04-12 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Output text raw if configuration requires it. + + * include/platform.inc: + * src/edk.S: [deleted] + * cdl/hal_sh_edk7708.cdl: + Hardware init code moved to platform.inc in order to allow ROMRAM + startup. + + * include/pkgconf/mlt_sh_edk7708_romram.h: + * include/pkgconf/mlt_sh_edk7708_romram.mlt: + * include/pkgconf/mlt_sh_edk7708_romram.ldi: + * cdl/hal_sh_edk7708.cdl: + Add ROMRAM startup option. + +2000-04-06 Jonathan Larmour <jlarmour@redhat.co.uk> + + * cdl/hal_sh_edk7708.cdl: Use -g now that toolchains work with that + (and in fact new toolchains no longer work with -ggdb) + +2000-04-06 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Define vsr base location. + +2000-04-04 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c (hal_diag_write_char): Add GDB critical IO region + handling. + +2000-03-20 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Added board speed variable. + +2000-03-09 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Fix compiler warning. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * include/platform.inc: Use sh_offsets instead of C header. + +2000-02-18 Jonathan Larmour <jlarmour@redhat.co.uk> + + * cdl/hal_sh_edk7708.cdl (CYGBLD_BUILD_GDB_STUBS): When + building stubs, define every dependency required here rather than + in the template + +2000-02-17 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: + Go back to -ggdb. -gstabs don't provide enough info for + source-level debugging. + + * include/pkgconf/mlt_sh_edk7708_rom.h: + * include/pkgconf/mlt_sh_edk7708_rom.ldi: + * include/pkgconf/mlt_sh_edk7708_rom.mlt: + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + Don't use . assignment due to tools problem. + +2000-02-16 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Added LE support. + +2000-02-15 Jesper Skov <jskov@redhat.com> + + * misc/STUBS_config: + * include/pkgconf/mlt_sh_edk7708_rom.ldi: + * include/pkgconf/mlt_sh_edk7708_rom.mlt: + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + Updated for new stubs scheme. + + * cdl/hal_sh_edk7708.cdl: Removed stubs startup. + Use -gstabs instead of -ggdb to work around problem with GDB. + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + HAL_STUB_PLATFORM_STUBS_INIT->HAL_STUB_PLATFORM_INIT + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: use cpu flags when linking. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Implements stubs. + +2000-01-27 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Moved part of stubs build rule to + common HAL. Changed description. + +2000-01-26 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Fix display string. + +2000-01-24 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sh_edk7708.cdl: Add stubs build rule. + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + * include/pkgconf/mlt_sh_edk7708_stubs.ldi: + * include/pkgconf/mlt_sh_edk7708_stubs.h: + * include/pkgconf/mlt_sh_edk7708_stubs.mlt: + Give stub more RAM. + +2000-01-24 John Dallaway <jld@cygnus.co.uk> + + * cdl/*.cdl: + + Remove obsolete option CYGTST_TESTING_IDENTIFIER. + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-18 Jesper Skov <jskov@cygnus.co.uk> + CR 902066 + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + * include/pkgconf/mlt_sh_edk7708_ram.h: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + Correct RAM size. + +1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/plf_misc.c (cyg_hal_user_break): Rename + CYG_HAL_USE_ROM_MONITOR_GDB_STUBS -> CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs + + * cdl/hal_sh_edk7708.cdl: Don't need to define CYG_HAL_SH_SH7708 any + more + Add new platform-specific CYGSEM_HAL_USE_ROM_MONITOR option to + control ROM monitor support + +1999-12-20 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/hal_sh_edk7708.cdl: Add -Wl for linker options. + +1999-11-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/mlt_sh_edk7708_stubs.h: + * include/pkgconf/mlt_sh_edk7708_rom.h: + * include/pkgconf/mlt_sh_edk7708_ram.h: New file(s). + +1999-11-02 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sh_edk7708.cdl: Use define_proc for CPU define. + +1999-11-01 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sh_edk7708.cdl: Use define_proc for const header defs. + +1999-10-29 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sh_edk7708.cdl: Added. + +1999-10-13 Jesper Skov <jskov@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): + * src/plf_misc.c: + * src/PKGconf.mak (COMPILE): + Added user breakpoint handling. + +1999-09-02 Jesper Skov <jskov@cygnus.co.uk> + + * misc/STUBS_config: Also disable kernel support in HAL. + +1999-08-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/STUBS_config: Added. + +1999-06-18 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_sh_edk7708.h: Consistent EDK7708 naming. + +1999-06-01 Jesper Skov <jskov@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): Don't look for 0x03 + chars. It doesn't work well. Better the dedicated magic handles + C-c. + + * src/edk.S: Cleaned up memory controller setup. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_sh_edk7708.h: Removed FIX ME. + + * src/edk.S: Fixed delay-slot problem. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_sh_edk7708.h: Fixed platform name. + + * include/pkgconf/mlt_sh_edk7708_rom.ldi: + * include/pkgconf/mlt_sh_edk7708_rom.mlt: + * include/pkgconf/mlt_sh_edk7708_stubs.ldi: + * include/pkgconf/mlt_sh_edk7708_stubs.mlt: + * include/pkgconf/mlt_sh_edk7708_ram.ldi: + * include/pkgconf/mlt_sh_edk7708_ram.mlt: + Fixed memory layout and generated MLT files. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_sh_edk.h: [deleted] + * include/pkgconf/mlt_sh_edk_ram.ldi: [deleted] + * include/pkgconf/mlt_sh_edk_ram.mlt: [deleted] + * include/pkgconf/mlt_sh_edk_rom.ldi: [deleted] + * include/pkgconf/mlt_sh_edk_stubs.ldi: [deleted] + * include/pkgconf/hal_sh_edk7708.h: [added] + * include/pkgconf/mlt_sh_edk7708_ram.ldi: [added] + * include/pkgconf/mlt_sh_edk7708_ram.mlt: [added] + * include/pkgconf/mlt_sh_edk7708_rom.ldi: [added] + * include/pkgconf/mlt_sh_edk7708_rom.mlt: [added] + * include/pkgconf/mlt_sh_edk7708_stubs.ldi:[added] + * include/pkgconf/mlt_sh_edk7708_stubs.mlt:[added] + * src/PKGconf.mak: + Renamed SH platform package to edk7708. + +1999-05-21 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_sh_edk.h (CYGNUM_HAL_RTC_PERIOD): The timer + is running at 1/4 of the peripheral clock. + + * include/plf_stub.h: Added RESET code. + + * include/pkgconf/hal_sh_edk.h: Added RTC data for the edk board. + +1999-05-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/mlt_sh_edk_ram.mlt: Working MLT-generated + version. + +1999-05-20 Jesper Skov <jskov@cygnus.co.uk> + + * Moved files to CVS trunk. + +1999-05-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/edk.S (_hal_hardware_init): Fix a few mistakes. + + * include/plf_stub.h: Enable led in stub init. + + * include/pkgconf/mlt_sh_edk_stubs.ldi: + * include/pkgconf/mlt_sh_edk_rom.ldi: + Added. + Moved RAM region to the end of the chunk and made it bigger. + + * src/edk.S (_hal_hardware_init): Added Bus State Controller + initialization. + +1999-05-19 Jesper Skov <jskov@cygnus.co.uk> + + * Most things working now. Will start keeping track of changes. + +1999-04-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * Set up directory structure. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/cdl/hal_sh_edk7708.cdl @@ -0,0 +1,312 @@ +# ==================================================================== +# +# hal_sh_edk7708.cdl +# +# EDK7708 board HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: jskov +# Contributors: +# Date: 1999-10-29 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SH_EDK7708 { + display "Hitachi EDK/SH7708 board" + parent CYGPKG_HAL_SH + requires CYGPKG_HAL_SH_7708 + define_header hal_sh_edk7708.h + include_dir cyg/hal + description " + The edk HAL package provides the support needed to run + eCos on a Hitachi SH3 EDK7708 board." + + compile hal_diag.c plf_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_edk7708.h>" + + puts $::cdl_header "#define CYGNUM_HAL_SH_SH3_SCI_PORTS 1" + puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000" + puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMRAM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the EDK7708 board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. + RAM bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap typically + requires that the eCos application be blown into EPROMs or + equivalent technology. ROMRAM bootstrap is similar to ROM + bootstrap, but everything is copied to RAM before execution + starts thus improving performace, but at the cost of an + increased RAM footprint." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The EDK/7708 board has only one serial port. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The EDK/7708 board has only one serial port. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS { + display "SH on-chip platform clock controls" + description " + The various clocks used by the system are derived from + these options." + flavor none + no_define + + cdl_option CYGHWR_HAL_SH_OOC_XTAL { + display "SH clock crystal" + flavor data + legal_values 8000000 to 50000000 + default_value 15000000 + no_define + description " + This option specifies the frequency of the crystal all + other clocks are derived from." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_1 { + display "SH clock PLL circuit 1" + flavor data + default_value 1 + legal_values { 0 1 2 4 } + description " + This selects the multiplication factor provided by + PLL1. If PLL1 is disabled via CAP1, this option should + be set to zero." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_2 { + display "SH clock PLL circuit 2" + flavor data + default_value 4 + legal_values { 0 1 4 } + no_define + description " + This selects the multiplication factor provided by + PLL2. If PLL2 is disabled via CAP2, this option should + be set to zero." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 { + display "SH clock divider 1" + flavor data + default_value 1 + legal_values { 1 2 3 4 } + description " + This divider option affects the CPU core clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_2 { + display "SH clock divider 2" + flavor data + default_value 4 + legal_values { 1 2 3 4 } + description " + This divider option affects the peripheral clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE { + display "SH clock mode" + flavor data + default_value 2 + legal_values { 0 1 2 3 4 7 } + description " + This option must mirror the clock mode hardwired on + the MD0-MD2 pins of the CPU in order to correctly + initialize the FRQCR register." + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "sh-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "sh_edk7708_ram" : \ + CYG_HAL_STARTUP == "ROM" ? "sh_edk7708_rom" : \ + "sh_edk7708_romram" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_edk7708_ram.ldi>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_edk7708_rom.ldi>" : \ + "<pkgconf/mlt_sh_edk7708_romram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_edk7708_ram.h>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_edk7708_rom.h>" : \ + "<pkgconf/mlt_sh_edk7708_romram.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + parent CYGPKG_HAL_ROM_MONITOR + description " + Support can be enabled for boot ROMs or ROM monitors which contain + GDB stubs. This support changes various eCos semantics such as + the encoding of diagnostic output, and the overriding of hardware + interrupt vectors." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/hal_diag.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-04-24 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// Simple LED control. +externC void hal_diag_led_on( void ); +externC void hal_diag_led_off( void ); + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Fri Oct 20 09:50:36 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x8008000) +#define CYGMEM_REGION_ram_SIZE (0xf8000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_ram.ldi @@ -0,0 +1,26 @@ +// eCos memory layout - Fri Oct 20 09:50:36 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x8008000, LENGTH = 0xf8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (ram, 0x8008000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 8008000 f8000 0 ! +section vectors 0 1 0 1 1 1 1 1 8008000 8008000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 09:51:04 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x8000200) +#define CYGMEM_REGION_ram_SIZE (0xffe00) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xa0000000) +#define CYGMEM_REGION_rom_SIZE (0x20000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_rom.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 09:51:04 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x8000200, LENGTH = 0xffe00 + rom : ORIGIN = 0xa0000000, LENGTH = 0x20000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xa0000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x8000200, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_rom.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 8000200 ffe00 0 ! +region rom a0000000 20000 1 ! +section data 0 1 1 1 1 1 0 0 8000200 bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section vectors 0 1 0 1 1 1 1 1 a0000000 a0000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_romram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 09:51:30 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x8000200) +#define CYGMEM_REGION_ram_SIZE (0xffe00) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xa0000000) +#define CYGMEM_REGION_rom_SIZE (0x20000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x8100000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_romram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 09:51:30 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x8000200, LENGTH = 0xffe00 + rom : ORIGIN = 0xa0000000, LENGTH = 0x20000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (ram, 0x8000200, AT (0xa0000000)) + SECTION_text (ram, ALIGN (0x10), FOLLOWING (.vectors)) + SECTION_fini (ram, ALIGN (0x10), FOLLOWING (.text)) + SECTION_rodata1 (ram, ALIGN (0x10), FOLLOWING (.fini)) + SECTION_rodata (ram, ALIGN (0x10), FOLLOWING (.rodata1)) + SECTION_fixup (ram, ALIGN (0x10), FOLLOWING (.rodata)) + SECTION_gcc_except_table (ram, ALIGN (0x10), FOLLOWING (.fixup)) + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/pkgconf/mlt_sh_edk7708_romram.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 8000200 ffe00 0 ! +region rom a0000000 20000 1 ! +section vectors 0 10 1 1 1 1 1 1 8000200 a0000000 text text ! +section text 0 10 1 1 0 1 0 1 fini fini ! +section fini 0 10 1 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 10 1 1 0 1 0 1 rodata rodata ! +section rodata 0 10 1 1 0 1 0 1 fixup fixup ! +section fixup 0 10 1 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 10 1 1 0 1 0 1 data data ! +section data 0 10 1 1 0 1 0 0 bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/platform.inc @@ -0,0 +1,196 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## SH/EDK7708 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-02-02 +## Purpose: SH/EDK7708 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the SH/EDK7708 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/sh_regs.h> +#include <cyg/hal/sh_offsets.inc> + +#------------------------------------------------------------------------------ +# Hardware initialization. + + .macro hal_hardware_init + // Set up the Bus State Controller + mova BSC_settings_table,r0 + mov r0,r3 +1: mov.w @r3+,r0 // Address (or zero) + cmp/eq #0,r0 + bt 2f + mov.w @r3+,r1 // data + bra 1b + mov.w r1,@r0 // delay slot + + .align 2 +BSC_settings_table: + # These are the settings set by the Hitachi ROM Monitor. + + .word CYGARC_REG_FRQCR + .word CYGARC_REG_FRQCR_INIT + + # BCR2: Bus size of areas 1-6 to 32 bits + .word CYGARC_REG_BCR2 + .word 0x3ffc + # BCR1: Areas 2 and 3 are SDRAM + .word CYGARC_REG_BCR1 + .word 0x080c + # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!] + .word CYGARC_REG_BCR2 + .word 0x3ffc + # WCR1: 3 wait-state cycles inserted for all areas + .word CYGARC_REG_WCR1 + .word 0x3fff + # WCR2: extra wait states and full pitch for burst + .word CYGARC_REG_WCR2 + .word 0xffd7 + # MCR: RAS/CAS & burst timing area 2/3 + .word CYGARC_REG_MCR + .word 0x963c + # RTCNT: refresh counter (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCNT + .word (0xa500 | 0x0000) + # RTCOR: refresh time constant (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCOR + .word (0xa500 | 0x003b) + # RFCR: refresh count register (needs a4 in top byte to accept write) + .word CYGARC_REG_RFCR + .word (0xa400 | 0x0000) + # RTCSR: refresh timer control (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCSR + .word (0xa500 | 0x0008) + + # Set SDMR to 0x220 + .word 0xd880 + .word 0 + + # Table end + .word 0 + + .align 2 +2: + .endm + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_SH_MON_DEFINED + +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are not starting up from RAM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + mov.l $_hal_vsr_table_p,r3 + # Write exception vectors + mov.l $_cyg_hal_default_exception_vsr_p,r4 + mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5 +1: mov.l r4,@r3 + add #4,r3 + dt r5 + bf 1b + # Write interrupt vector + mov.l $_cyg_hal_default_interrupt_vsr_p,r4 + mov.l r4,@r3 + bra 2f + nop + .align 2 + +$_cyg_hal_default_exception_vsr_p: + .long _cyg_hal_default_exception_vsr +$_cyg_hal_default_interrupt_vsr_p: + .long _cyg_hal_default_interrupt_vsr + + .extern _hal_vsr_table +$_hal_vsr_table_p: + .long _hal_vsr_table + +2: + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + # Write interrupt vector + mov.l $_hal_vsr_table_p,r3 + mov.l $_cyg_hal_default_interrupt_vsr_p,r4 + mov.l r4,@r3 + bra 2f + nop + .align 2 + +$_cyg_hal_default_interrupt_vsr_p: + .long _cyg_hal_default_interrupt_vsr + + .extern _hal_vsr_table +$_hal_vsr_table_p: + .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4 + +2: + .endm + +#else + + .macro hal_mon_init + .endm + +#endif + + +#define CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGONCE_HAL_PLATFORM_INC
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/plf_cache.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform specific cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-31 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/plf_intr.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, +// Date: 2000-10-31 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the EDK board. +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +//-------------------------------------------------------------------------- + +// No platform specific stuff at present. + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/include/plf_stub.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-05-18 +// Purpose: Platform HAL stub support for Hitachi/EDK boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#include <cyg/hal/sh_stub.h> // architecture stub support + +#include <cyg/hal/hal_diag.h> // hal_diag_led_on + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +//---------------------------------------------------------------------------- +// Stub initializer. +#ifdef CYGSEM_HAL_ROM_MONITOR +# define HAL_STUB_PLATFORM_INIT() hal_diag_led_on() +#else +# define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT +#endif + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//---------------------------------------------------------------------------- +// Reset. +// Block interrupts and cause an exception. This forces a reset. +#define HAL_STUB_PLATFORM_RESET() \ + asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL)) + +#define HAL_STUB_PLATFORM_RESET_ENTRY 0xa0000000 + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/src/edk.S @@ -0,0 +1,117 @@ +##============================================================================= +## +## edk.S +## +## EDK board hardware setup +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 1999-05-03 +## Purpose: EDK7708 board hardware setup +## Description: This file contains any code needed to initialize the +## hardware on a Hitachi SH3 EDK7708 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/sh_regs.h> + + .globl _hal_hardware_init +_hal_hardware_init: + + // Set up the Bus State Controller + mov.l $BSC_settings_table,r3 +1: mov.w @r3+,r0 // Address (or zero) + cmp/eq #0,r0 + bt 2f + mov.w @r3+,r1 // data + bra 1b + mov.w r1,@r0 // delay slot + +2: + rts + nop + + .align 2 +$BSC_settings_table: + .long BSC_settings_table +BSC_settings_table: + # These are the settings set by the Hitachi ROM Monitor. + + # BCR2: Bus size of areas 1-6 to 32 bits + .word CYGARC_REG_BCR2 + .word 0x3ffc + # BCR1: Areas 2 and 3 are SDRAM + .word CYGARC_REG_BCR1 + .word 0x080c + # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!] + .word CYGARC_REG_BCR2 + .word 0x3ffc + # WCR1: 3 wait-state cycles inserted for all areas + .word CYGARC_REG_WCR1 + .word 0x3fff + # WCR2: extra wait states and full pitch for burst + .word CYGARC_REG_WCR2 + .word 0xffd7 + # MCR: RAS/CAS & burst timing area 2/3 + .word CYGARC_REG_MCR + .word 0x963c +#if 0 + # DCR: RAS/CAS & burst timing area 2 + .word CYGARC_REG_DCR + .word 0x0000 + # PCR: PCMCIA disabled + .word CYGARC_REG_PCR + .word 0x0000 +#endif + # RTCNT: refresh counter (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCNT + .word (0xa500 | 0x0000) + # RTCOR: refresh time constant (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCOR + .word (0xa500 | 0x003b) + # RFCR: refresh count register (needs a4 in top byte to accept write) + .word CYGARC_REG_RFCR + .word (0xa400 | 0x0000) + # RTCSR: refresh timer control (needs a5 in top byte to accept write) + .word CYGARC_REG_RTCSR + .word (0xa500 | 0x0008) + + # Set SDMR to 0x220 + .word 0xd880 + .word 0 + + # Table end + .word 0 + +#------------------------------------------------------------------------------ +# end of edk.S
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/src/hal_diag.c @@ -0,0 +1,219 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jskov +// Contributors: nickg, jskov +// Date: 1999-03-23 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_diag.h> // our header. + +#include <cyg/infra/cyg_type.h> // base types, externC +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // Calling interface +#include <cyg/hal/hal_intr.h> // Interrupt macros +#include <cyg/hal/sh3_sci.h> // driver API +#include <cyg/hal/hal_misc.h> // Helper functions + +#define SCI_BASE ((cyg_uint8*)0xfffffe80) + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_sci_init(0, 0, CYGNUM_HAL_INTERRUPT_SCI_RXI, SCI_BASE); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +//============================================================================= +// Led control +//============================================================================= +#define LED_ON 0x04000000 +#define LED_OFF 0x18000000 + +void +hal_diag_led_on( void ) +{ + HAL_WRITE_UINT8(LED_ON, 0); +} + +void +hal_diag_led_off( void ) +{ + HAL_WRITE_UINT8(LED_OFF, 0); +} + + +//============================================================================= +// Compatibility with older stubs +//============================================================================= + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +static channel_data_t channel = { (cyg_uint8*)SCI_BASE, 0, 0}; + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + +#define CYG_HAL_DIAG_GDB + +#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + +#define CYG_HAL_DIAG_GDB + +#endif + +//----------------------------------------------------------------------------- + +void hal_diag_init(void) +{ + cyg_hal_plf_sci_init_channel(&channel); +} + +void +hal_diag_write_char_serial( char c ) +{ + cyg_hal_plf_sci_putc(&channel, c); +} + +void +hal_diag_read_char(char *c) +{ + *c = (char) cyg_hal_plf_sci_getc(&channel); +} + +// Packet function +void +hal_diag_write_char(char c) +{ +#ifdef CYG_HAL_DIAG_GDB + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + char c1; + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + cyg_hal_plf_sci_putc(&channel, '$'); + cyg_hal_plf_sci_putc(&channel, 'O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + cyg_hal_plf_sci_putc(&channel, h); + cyg_hal_plf_sci_putc(&channel, l); + csum += h; + csum += l; + } + cyg_hal_plf_sci_putc(&channel, '#'); + cyg_hal_plf_sci_putc(&channel, hex[(csum>>4)&0xF]); + cyg_hal_plf_sci_putc(&channel, hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. + c1 = (char) cyg_hal_plf_sci_getc(&channel); + + if( c1 == '+' ) + break; // a good acknowledge + + // Check for user break. + if( cyg_hal_is_break( &c1, 1 ) ) + cyg_hal_user_break( NULL ); + + // otherwise, loop round again + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + } +#else // CYG_HAL_DIAG_GDB + cyg_hal_plf_sci_putc(&channel, c); +#endif +} +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/edk7708/current/src/plf_misc.c @@ -0,0 +1,57 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov,nickg, jlarmour +// Date: 1999-10-13 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_if.h> // interfacing API + +//-------------------------------------------------------------------------- +void +hal_platform_init(void) +{ + hal_if_init(); +} + +//-------------------------------------------------------------------------- +// eof plf_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/ChangeLog @@ -0,0 +1,35 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * Many changes to bring the Haruki's HAL split up to date. Also + split the register header file into many header files, one for + each CPU module. + +2000-08-15 Haruki Kashiwaya <kashiwaya@redhat.com> + + * Set up directory structure. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/cdl/hal_sh_sh3.cdl @@ -0,0 +1,372 @@ +# ==================================================================== +# +# hal_sh_sh3.cdl +# +# SH3 variant HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: jskov +# Contributors: +# Date: 2000-10-30 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SH_SH3 { + display "SH3 variant" + parent CYGPKG_HAL_SH + hardware + include_dir cyg/hal + define_header hal_sh_sh3.h + description " + The SH3 (SuperH 3) variant HAL package provides generic + support for SH3 variant CPUs." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_sh_sh3.h>" + } + + compile sh3_sci.c sh3_scif.c var_misc.c variant.S + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + <PREFIX>/include/cyg/hal/sh3_offsets.inc : <PACKAGE>/src/var_mk_defs.c + $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $< + fgrep .equ var_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 sh3_offsets.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm sh3_offsets.tmp var_mk_defs.tmp + } + + # CPU variant supported + cdl_option CYGPKG_HAL_SH_7707A { + display "SH 7707A microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + implements CYGINT_HAL_SH_CPG_T2 + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7707A + description " + The SH3 7707A microprocessor. This is an embedded part that in + addition to the SH3 processor core has built in peripherals + such as memory controllers, serial ports, LCD controller and + timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7707a.h>" + } + } + + cdl_option CYGPKG_HAL_SH_7708 { + display "SH 7708 microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + implements CYGINT_HAL_SH_CPG_T1 + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7708 + description " + The SH3 7708 microprocessor. This is an embedded part that in + addition to the SH3 processor core has built in peripherals + such as memory controllers, serial ports and + timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7708.h>" + } + } + + cdl_option CYGPKG_HAL_SH_7709A { + display "SH 7709A microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + implements CYGINT_HAL_SH_CPG_T3 + implements CYGINT_HAL_SH_DMA_CHANNELS + implements CYGINT_HAL_SH_DMA_CHANNELS + implements CYGINT_HAL_SH_DMA_CHANNELS + implements CYGINT_HAL_SH_DMA_CHANNELS + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7709A + description " + The SH3 7709A microprocessor. This is an embedded part that in + addition to the SH3 processor core has built in peripherals + such as memory controllers, DMA controllers, A/D and D/A + converters, serial ports and timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7709a.h>" + } + } + + cdl_option CYGPKG_HAL_SH_7729 { + display "SH 7729 microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + implements CYGINT_HAL_SH_CPG_T3 + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7729 + description " + The SH3 7729 microprocessor. This is an embedded part that in + addition to the SH3 processor core has built in peripherals + such as memory controllers, serial ports, and timers/counters, + and a DSP engine." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7729.h>" + } + } + + cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS { + display "SH on-chip generic clock controls" + description " + The various clocks used by the system are controlled by + these options, some of which are derived from platform + settings." + flavor none + no_define + + cdl_interface CYGINT_HAL_SH_CPG_T1 { + display "Clock pulse generator type 1" + } + + cdl_interface CYGINT_HAL_SH_CPG_T2 { + display "Clock pulse generator type 2" + } + + cdl_interface CYGINT_HAL_SH_CPG_T3 { + display "Clock pulse generator type 3" + } + + + cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 { + display "TMU counter 0 prescaling" + description " + The peripheral clock is driving the counter used for + the real-time clock, prescaled by this factor." + flavor data + legal_values { 4 16 64 256 } + default_value 4 + } + + + cdl_option CYGHWR_HAL_SH_CLOCK_CKIO { + display "CKIO clock" + no_define + flavor data + # CKIO is either XTAL or PLL2 output + calculated { CYGINT_HAL_SH_CPG_T1 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) + ? (CYGHWR_HAL_SH_OOC_XTAL) + : CYGHWR_HAL_SH_PLL2_OUTPUT + ) + : CYGINT_HAL_SH_CPG_T2 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 2) + ? (CYGHWR_HAL_SH_OOC_XTAL) + : CYGHWR_HAL_SH_PLL2_OUTPUT + ) + : CYGINT_HAL_SH_CPG_T3 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) + ? (CYGHWR_HAL_SH_OOC_XTAL) + : CYGHWR_HAL_SH_PLL2_OUTPUT + ) + : 0 } + } + + cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT { + display "The clock output from PLL1" + no_define + flavor data + calculated { CYGHWR_HAL_SH_CLOCK_CKIO * CYGHWR_HAL_SH_OOC_PLL_1 } + } + + cdl_option CYGHWR_HAL_SH_PLL2_OUTPUT { + display "The clock output from PLL2" + no_define + flavor data + calculated { CYGINT_HAL_SH_CPG_T1 ? ( + (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) + ) + : CYGINT_HAL_SH_CPG_T2 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 5) + ? (CYGHWR_HAL_SH_OOC_XTAL / 2) + : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 6) + ? (14745600) + : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7) + ? (11075600) + : (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) + ) + : CYGINT_HAL_SH_CPG_T3 ? ( + (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2) + ) + : 0 } + } + + + cdl_option CYGHWR_HAL_SH_DIVIDER1_INPUT { + display "The clock input to divider 1" + no_define + flavor data + # DIV1 input is either PLL2 output or PLL1 output + calculated { (CYGHWR_HAL_SH_OOC_PLL_1 == 0) + ? CYGHWR_HAL_SH_PLL2_OUTPUT + : CYGHWR_HAL_SH_PLL1_OUTPUT } + } + + cdl_option CYGHWR_HAL_SH_DIVIDER2_INPUT { + display "The clock input to divider 2" + no_define + flavor data + # DIV2 input is either PLL2 output or PLL1 output + calculated { CYGINT_HAL_SH_CPG_T1 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4) + ? CYGHWR_HAL_SH_PLL2_OUTPUT + : CYGHWR_HAL_SH_PLL1_OUTPUT + ) + : CYGINT_HAL_SH_CPG_T2 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2) + ? CYGHWR_HAL_SH_PLL1_OUTPUT + : CYGHWR_HAL_SH_PLL2_OUTPUT + ) + : CYGINT_HAL_SH_CPG_T3 ? ( + (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4) + ? CYGHWR_HAL_SH_PLL2_OUTPUT + : CYGHWR_HAL_SH_PLL1_OUTPUT + ) + : 0 } + } + + cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED { + display "Processor clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_DIVIDER1_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_1 } + description " + The core (CPU, cache and MMU) speed is computed from + the input clock speed and the divider 1 setting." + } + + cdl_option CYGHWR_HAL_SH_BOARD_SPEED { + display "Platform bus clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_CLOCK_CKIO } + description " + The platform bus speed is CKIO." + } + + cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED { + display "Processor on-chip peripheral clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_DIVIDER2_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_2 } + description " + The peripheral speed is computed from the input clock + speed and the divider 2 settings." + } + } + + + cdl_component CYGPKG_HAL_SH_INTERRUPT { + display "Interrupt controls" + flavor none + no_define + description " + Initial interrupt settings can be specified using these option." + + cdl_option CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS { + display "Handle spurious interrupts" + default_value 0 + description " + The SH3 may generate spurious interrupts with INTEVT = 0 + when changing the BL bit of the status register. Enabling + this option will cause such interrupts to be identified + very early in the interrupt handler and be ignored. Given + that the SH HAL uses the I-mask to control interrupts, + these spurious interrupts should not occur, and so there + should be no reason to include the special handling code." + } + + cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL { + display "Use IRQ0-3 pins as IRL input" + default_value 0 + description " + It is possible for the IRQ0-3 pins to be used as IRL + inputs by enabling this option." + } + + cdl_option CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS { + display "Enable IRLS interrupt pins" + default_value 0 + active_if CYGHWR_HAL_SH_IRQ_USE_IRQLVL + description " + IRLS interrupt pins must be specifically + activated. When they are, they will cause the same + type of interrupt as those caused by the IRL pins. If + IRL and IRLS pins signal an interrupt at the same + time, the highest level interrupt will be generated. + Only available on some cores, and probably share pins + with other interrupt sources (PINT) which cannot be + used in this configuration." + } + } + + # Cache settings + cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 { + display "Select cache mode set for P0/U0/P3 at startup" + parent CYGPKG_HAL_SH_CACHE + default_value { "WRITE_BACK" } + legal_values { "WRITE_BACK" "WRITE_THROUGH" } + flavor data + description " + Controls what cache mode the cache should be put in at + startup for areas P0, U0 and P3. Write-back mode improves + performance by letting dirty data to be kept in the + cache for a period of time, allowing mutiple writes to + the same cache line to be written back to memory in + one memory transaction. In Write-through mode, each + individual write will cause a memory transaction." + } + + cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 { + display "Select cache mode set for P1 at startup" + parent CYGPKG_HAL_SH_CACHE + default_value { "WRITE_BACK" } + legal_values { "WRITE_BACK" "WRITE_THROUGH" } + flavor data + description " + Controls what cache mode the cache should be put in at + startup for area P1. Write-back mode improves + performance by letting dirty data to be kept in the + cache for a period of time, allowing mutiple writes to + the same cache line to be written back to memory in + one memory transaction. In Write-through mode, each + individual write will cause a memory transaction." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_7707a.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7707a.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-06-08 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_BCN 2 +#define CYGARC_SH_MOD_CPG 2 +#define CYGARC_SH_MOD_INTC 3 +#define CYGARC_SH_MOD_IRDA 1 +#define CYGARC_SH_MOD_PFC 1 +#define CYGARC_SH_MOD_SCI 1 +#define CYGARC_SH_MOD_SCIF 1 +#define CYGARC_SH_MOD_UBC 1 + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +// Cache dimenions - one unified cache +#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line +#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache + +// Cache addressing information +// way: bits 13 - 12 +// entry: bits 11 - 4 +#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_77xx_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_7708.h @@ -0,0 +1,81 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7708.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-03-16 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_BCN 1 +#define CYGARC_SH_MOD_CPG 1 +#define CYGARC_SH_MOD_INTC 1 +#define CYGARC_SH_MOD_SCI 2 +#define CYGARC_SH_MOD_UBC 1 + + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +// Cache dimenions - one unified cache +#define CYGARC_SH_MOD_CAC_SIZE 8192 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line +#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache + +// Cache addressing information +// way: bits 12 - 11 +// entry: bits 10 - 4 +#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0002000 +#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_77xx_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_7709a.h @@ -0,0 +1,84 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7709a.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-03-16 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_BCN 2 +#define CYGARC_SH_MOD_CPG 3 +#define CYGARC_SH_MOD_DMAC 1 +#define CYGARC_SH_MOD_INTC 2 +#define CYGARC_SH_MOD_IRDA 1 +#define CYGARC_SH_MOD_PFC 1 +#define CYGARC_SH_MOD_SCI 1 +#define CYGARC_SH_MOD_SCIF 1 +#define CYGARC_SH_MOD_UBC 2 + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +// Cache dimenions - one unified cache +#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line +#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache + +// Cache addressing information +// way: bits 13 - 12 +// entry: bits 11 - 4 +#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_77xx_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_7729.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7729.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-08-29 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_BCN 2 +#define CYGARC_SH_MOD_CPG 3 +#define CYGARC_SH_MOD_INTC 3 +#define CYGARC_SH_MOD_IRDA 1 +#define CYGARC_SH_MOD_PFC 1 +#define CYGARC_SH_MOD_SCI 1 +#define CYGARC_SH_MOD_SCIF 1 +#define CYGARC_SH_MOD_UBC 3 + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +// Cache dimenions - one unified cache +#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line +#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache + +// Cache addressing information +// way: bits 13 - 12 +// entry: bits 11 - 4 +#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_77xx_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_bsc.h @@ -0,0 +1,180 @@ +//============================================================================= +// +// mod_regs_bsc.h +// +// BSC (bus state controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Register definitions +#define CYGARC_REG_BCR1 0xffffff60 +#define CYGARC_REG_BCR2 0xffffff62 +#define CYGARC_REG_WCR1 0xffffff64 +#define CYGARC_REG_WCR2 0xffffff66 +#define CYGARC_REG_MCR 0xffffff68 +#define CYGARC_REG_DCR 0xffffff6a +#define CYGARC_REG_PCR 0xffffff6c +#define CYGARC_REG_RTCSR 0xffffff6e +#define CYGARC_REG_RTCNT 0xffffff70 +#define CYGARC_REG_RTCOR 0xffffff72 +#define CYGARC_REG_RFCR 0xffffff74 + +#define CYGARC_REG_SDMR_AREA2_BASE 0xffffd000 +#define CYGARC_REG_SDMR_AREA3_BASE 0xffffe000 + +#define CYGARC_REG_BCR1_DRAMTP2 0x0010 +#define CYGARC_REG_BCR1_DRAMTP1 0x0008 +#define CYGARC_REG_BCR1_DRAMTP0 0x0004 + +// Bus widths for areas +#define CYGARC_REG_BCR2_A6_8 0x1000 +#define CYGARC_REG_BCR2_A6_16 0x2000 +#define CYGARC_REG_BCR2_A6_32 0x3000 +#define CYGARC_REG_BCR2_A5_8 0x0400 +#define CYGARC_REG_BCR2_A5_16 0x0800 +#define CYGARC_REG_BCR2_A5_32 0x0c00 +#define CYGARC_REG_BCR2_A4_8 0x0100 +#define CYGARC_REG_BCR2_A4_16 0x0200 +#define CYGARC_REG_BCR2_A4_32 0x0300 +#define CYGARC_REG_BCR2_A3_8 0x0040 +#define CYGARC_REG_BCR2_A3_16 0x0080 +#define CYGARC_REG_BCR2_A3_32 0x00c0 +#define CYGARC_REG_BCR2_A2_8 0x0010 +#define CYGARC_REG_BCR2_A2_16 0x0020 +#define CYGARC_REG_BCR2_A2_32 0x0030 + +// Memory type selection and other IO behavior controls +#define CYGARC_REG_BCR1_PULA 0x8000 // Pin A25 to A0 Pull-Up +#define CYGARC_REG_BCR1_PULD 0x4000 // Pin D31 to D0 Pull-Up +#define CYGARC_REG_BCR1_HIZMEM 0x2000 // Hi-Z memory control +#define CYGARC_REG_BCR1_HIZCNT 0x1000 // High-Z Control +#define CYGARC_REG_BCR1_ENDIAN 0x0800 // Endian Flag +#define CYGARC_REG_BCR1_A0_BST_MASK 0x0600 // Area 0 Burst ROM Control +#define CYGARC_REG_BCR1_A0_BST_4 0x0200 +#define CYGARC_REG_BCR1_A0_BST_8 0x0400 +#define CYGARC_REG_BCR1_A0_BST_16 0x0600 +#define CYGARC_REG_BCR1_A5_BST_MASK 0x0180 // Area 5 Burst ROM Control +#define CYGARC_REG_BCR1_A5_BST_4 0x0080 +#define CYGARC_REG_BCR1_A5_BST_8 0x0100 +#define CYGARC_REG_BCR1_A5_BST_16 0x0180 +#define CYGARC_REG_BCR1_A6_BST_MASK 0x0060 // Area 6 Burst ROM Control +#define CYGARC_REG_BCR1_A6_BST_4 0x0020 +#define CYGARC_REG_BCR1_A6_BST_8 0x0040 +#define CYGARC_REG_BCR1_A6_BST_16 0x0060 +#define CYGARC_REG_BCR1_DRAMTP_MASK 0x001c // Area 2, Area 3 Memory Type +#define CYGARC_REG_BCR1_A5PCM 0x0002 // Area 5 Bus Type +#define CYGARC_REG_BCR1_A6PCM 0x0001 // Area 6 Bus Type + +// Intercycle wait states +#define CYGARC_REG_WCR1_WAITSEL 0x8000 // WAIT Sampling Timing Select +#define CYGARC_REG_WCR1_A6I_MASK 0x3000 // Intercycle Idle Specification +#define CYGARC_REG_WCR1_A6I_SHIFT 12 +#define CYGARC_REG_WCR1_A5I_MASK 0x0c00 +#define CYGARC_REG_WCR1_A5I_SHIFT 10 +#define CYGARC_REG_WCR1_A4I_MASK 0x0300 +#define CYGARC_REG_WCR1_A4I_SHIFT 8 +#define CYGARC_REG_WCR1_A3I_MASK 0x00c0 +#define CYGARC_REG_WCR1_A3I_SHIFT 6 +#define CYGARC_REG_WCR1_A2I_MASK 0x0030 +#define CYGARC_REG_WCR1_A2I_SHIFT 4 +#define CYGARC_REG_WCR1_A0I_MASK 0x0003 +#define CYGARC_REG_WCR1_A0I_SHIFT 0 + +#define CYGARC_REG_WCR1_0WS 0 +#define CYGARC_REG_WCR1_1WS 1 +#define CYGARC_REG_WCR1_2WS 2 +#define CYGARC_REG_WCR1_3WS 3 + + +// Wait states +#define CYGARC_REG_WCR2_A6_MASK 0xe000 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A6_SHIFT 13 +#define CYGARC_REG_WCR2_A5_MASK 0x1c00 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A5_SHIFT 10 +#define CYGARC_REG_WCR2_A4_MASK 0x0380 // Wait states +#define CYGARC_REG_WCR2_A4_SHIFT 7 +#define CYGARC_REG_WCR2_A3_MASK 0x0060 // Wait states / CAS latency +#define CYGARC_REG_WCR2_A3_SHIFT 5 +#define CYGARC_REG_WCR2_A2_MASK 0x0018 // Wait states / CAS latency +#define CYGARC_REG_WCR2_A2_SHIFT 3 +#define CYGARC_REG_WCR2_A0_MASK 0x0007 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A0_SHIFT 0 + +#define CYGARC_REG_WCR2_0WS 0 +#define CYGARC_REG_WCR2_1WS 1 +#define CYGARC_REG_WCR2_2WS 2 +#define CYGARC_REG_WCR2_3WS 3 +#define CYGARC_REG_WCR2_4WS 4 +#define CYGARC_REG_WCR2_6WS 5 +#define CYGARC_REG_WCR2_8WS 6 +#define CYGARC_REG_WCR2_10WS 7 + +//-------------------------------------------------------------------------- +// Additional type definitions +#if (CYGARC_SH_MOD_BCN > 1) +# define CYGARC_REG_BCR3 0xffffff7e +#endif + + + +//----------------------------------------------------------------------------- +// Calculate constants needed to drive the proper SDRAM refresh rate. Argument +// is delay between required refresh events in microseconds (us). Should be +// available off the SDRAM spec sheet. +// These should be a part of a fully CDLicized memory controller setup. +#define CYGARC_RTCSR_PRESCALE(_r_) \ +(((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096) + +// These two macros provide the static values we need to stuff into the +// registers. +#define CYGARC_RTCSR_CKSx(_r_) \ + (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \ + ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \ + ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \ + ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \ + (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \ + (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 ) + +#define CYGARC_RTCSR_N(_r_) \ + (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_cac.h @@ -0,0 +1,66 @@ +//============================================================================= +// +// mod_regs_cac.h +// +// CAC (cache) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Besides the below, cache sizes are defined in the CPU variant module +// headers (mod_77xx.h). + +//-------------------------------------------------------------------------- +// Cache registers +#define CYGARC_REG_CCR 0xffffffec + +#define CYGARC_REG_CCR_RA 0x00000020 +#define CYGARC_REG_CCR_CF 0x00000008 +#define CYGARC_REG_CCR_CB 0x00000004 +#define CYGARC_REG_CCR_WT 0x00000002 +#define CYGARC_REG_CCR_CE 0x00000001 + + +//-------------------------------------------------------------------------- +// Address array access +// Address part (base/top/step specified in mod file) +#define CYGARC_REG_CACHE_ADDRESS_ADDRESS 0x00000008 // compare address + +// Data part +#define CYGARC_REG_CACHE_ADDRESS_TAG_Mask 0x1ffffc00 +#define CYGARC_REG_CACHE_ADDRESS_U 0x00000002 // updated (contains dirty data) +#define CYGARC_REG_CACHE_ADDRESS_V 0x00000001 // valid + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_cpg.h @@ -0,0 +1,213 @@ +//============================================================================= +// +// mod_regs_cpg.h +// +// CPG (clock pulse generator) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Oscillator control registers +#define CYGARC_REG_FRQCR 0xffffff80 +#define CYGARC_REG_WTCNT 0xffffff84 // read 8bit, write 16bit +#define CYGARC_REG_WTCSR 0xffffff86 // read 8bit, write 16bit + +#define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write + +#define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write +#define CYGARC_REG_WTCSR_TME 0x80 // timer enable +#define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0) +#define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0) +#define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow +#define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow +#define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2 +#define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1 +#define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0 +#define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask +// This is the period (in us) between watchdog reset and overflow. +// Note: We use max timeout delay for now. +#define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay + +#define CYGARC_REG_WTCSR_PERIOD ((1000000000/(CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/4096))*256) + +// Translate various CDL clock configurations to register equivalents +// for the various CPG versions +#if (CYGARC_SH_MOD_CPG == 1) // ---------------------------- V1 + +// PLL1 +#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 +#else +# error "Unsupported PLL1 setting" +#endif + +// Divider1 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 +#else +# error "Unsupported Divider1 setting" +#endif + +// Divider2 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 +#else +# error "Unsupported Divider1 setting" +#endif + +// CKOEN - set in all modes but 7 +#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 7) +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 +#else +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 +#endif + +#elif (CYGARC_SH_MOD_CPG == 2) // ---------------------------- V2 + +// PLL1 +#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 +#else +# error "Unsupported PLL1 setting" +#endif + +// Divider1 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 +#else +# error "Unsupported Divider1 setting" +#endif + +// Divider2 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 +#else +# error "Unsupported Divider1 setting" +#endif + +// CKOEN - set in all modes but 2 +#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE != 2) +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 +#else +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 +#endif + +#elif (CYGARC_SH_MOD_CPG == 3) // ---------------------------- V3 + +// PLL1 +#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) || (CYGHWR_HAL_SH_OOC_PLL_1 == 1) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 2) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0010 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 3) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x8000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0020 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x8010 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0030 +#else +# error "Unsupported PLL1 setting" +#endif + +// Divider1 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0004 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 3) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x4000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER1 0x0008 +#else +# error "Unsupported Divider1 setting" +#endif + +// Divider2 +#if (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0001 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 3) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x0002 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 6) +# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002 +#else +# error "Unsupported Divider2 setting" +#endif + +// CKOEN - set in modes 0-2 +#if (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2) +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0100 +#else +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 +#endif + +#else + +# error "Unsupported CPG version" + +#endif + +// Init value +#define CYGARC_REG_FRQCR_INIT (CYGARC_REG_FRQCR_INIT_PLL1|CYGARC_REG_FRQCR_INIT_DIVIDER1|CYGARC_REG_FRQCR_INIT_DIVIDER2|CYGARC_REG_FRQCR_INIT_CKOEN)
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_dma.h @@ -0,0 +1,111 @@ +//============================================================================= +// +// mod_regs_dma.h +// +// DMA (direct memory access) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// DMA Controller registers + +#define CYGARC_REG_SAR0 0xa4000020 +#define CYGARC_REG_DAR0 0xa4000024 +#define CYGARC_REG_DMATCR0 0xa4000028 +#define CYGARC_REG_CHCR0 0xa400002c +#define CYGARC_REG_SAR1 0xa4000030 +#define CYGARC_REG_DAR1 0xa4000034 +#define CYGARC_REG_DMATCR1 0xa4000038 +#define CYGARC_REG_CHCR1 0xa400003c +#define CYGARC_REG_SAR2 0xa4000040 +#define CYGARC_REG_DAR2 0xa4000044 +#define CYGARC_REG_DMATCR2 0xa4000048 +#define CYGARC_REG_CHCR2 0xa400004c +#define CYGARC_REG_SAR3 0xa4000050 +#define CYGARC_REG_DAR3 0xa4000054 +#define CYGARC_REG_DMATCR3 0xa4000058 +#define CYGARC_REG_CHCR3 0xa400005c +#define CYGARC_REG_DMAOR 0xa4000060 + +// Offsets from base register +#define CYGARC_REG_SAR 0x00 +#define CYGARC_REG_DAR 0x04 +#define CYGARC_REG_DMATCR 0x08 +#define CYGARC_REG_CHCR 0x0c + + +// DMA Channel Control Register. If there's a digit suffix to CHCR the flag +// is only valid in the listed channels. +#define CYGARC_REG_CHCR3_DI 0x00100000 // direct/indirect selection +#define CYGARC_REG_CHCR2_RO 0x00080000 // source address reload +#define CYGARC_REG_CHCR01_RL 0x00040000 // request check level +#define CYGARC_REG_CHCR01_AM 0x00020000 // acknowledge mode +#define CYGARC_REG_CHCR01_AL 0x00010000 // acknowledge level +#define CYGARC_REG_CHCR_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR_DM0 0x00004000 +#define CYGARC_REG_CHCR_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR_SM0 0x00001000 +#define CYGARC_REG_CHCR_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR_RS2 0x00000400 +#define CYGARC_REG_CHCR_RS1 0x00000200 +#define CYGARC_REG_CHCR_RS0 0x00000100 +#define CYGARC_REG_CHCR01_DS 0x00000040 // DREQ select +#define CYGARC_REG_CHCR_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR_TS0 0x00000008 +#define CYGARC_REG_CHCR_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR_DE 0x00000001 // DMAC enable + +// Resource select options +#define CYGARC_REG_CHCR_RS_EXT_DUAL 0x00000000 +#define CYGARC_REG_CHCR_RS_EXT_EX_DAC 0x00000100 +#define CYGARC_REG_CHCR_RS_EXT_DAC_EX 0x00000300 +#define CYGARC_REG_CHCR_RS_AUTO 0x00000400 +#define CYGARC_REG_CHCR_RS_IRDA_TX 0x00000a00 +#define CYGARC_REG_CHCR_RS_IRDA_RX 0x00000b00 +#define CYGARC_REG_CHCR_RS_SCIF_TX 0x00000c00 +#define CYGARC_REG_CHCR_RS_SCIF_RX 0x00000d00 +#define CYGARC_REG_CHCR_RS_AD 0x00000e00 +#define CYGARC_REG_CHCR_RS_CMT 0x00000f00 + + +// DMA Operation Register +#define CYGARC_REG_DMAOR_PR1 0x0200 // priority level +#define CYGARC_REG_DMAOR_PR0 0x0100 +#define CYGARC_REG_DMAOR_AE 0x0004 // address error flag +#define CYGARC_REG_DMAOR_NMIF 0x0002 // NMI flag +#define CYGARC_REG_DMAOR_DME 0x0001 // DMA master enable
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_intc.h @@ -0,0 +1,158 @@ +//============================================================================= +// +// mod_regs_intc.h +// +// INTC (interrupt controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Interrupt registers, module type 1 +#define CYGARC_REG_EXCEVT 0xffffffd4 +#define CYGARC_REG_INTEVT 0xffffffd8 + +#define CYGARC_REG_ICR 0xfffffee0 +#define CYGARC_REG_IPRA 0xfffffee2 +#define CYGARC_REG_IPRB 0xfffffee4 + +#define CYGARC_REG_IPRA_TMU0_MASK 0xf000 +#define CYGARC_REG_IPRA_TMU0_PRI1 0x1000 +#define CYGARC_REG_IPRA_TMU1_MASK 0x0f00 +#define CYGARC_REG_IPRA_TMU1_PRI1 0x0100 +#define CYGARC_REG_IPRA_TMU2_MASK 0x00f0 +#define CYGARC_REG_IPRA_TMU2_PRI1 0x0010 +#define CYGARC_REG_IPRA_RTC_MASK 0x000f +#define CYGARC_REG_IPRA_RTC_PRI1 0x0001 + +#define CYGARC_REG_IPRB_WDT_MASK 0xf000 +#define CYGARC_REG_IPRB_WDT_PRI1 0x1000 +#define CYGARC_REG_IPRB_REF_MASK 0x0f00 +#define CYGARC_REG_IPRB_REF_PRI1 0x0100 +#define CYGARC_REG_IPRB_SCI_MASK 0x00f0 +#define CYGARC_REG_IPRB_SCI_PRI1 0x0010 + + +#if (CYGARC_SH_MOD_INTC >= 2) +# define CYGARC_REG_INTEVT2 0xa4000000 +# define CYGARC_REG_IRR0 0xa4000004 +# define CYGARC_REG_IRR1 0xa4000006 +# define CYGARC_REG_IRR2 0xa4000008 +# define CYGARC_REG_ICR0 CYGARC_REG_ICR +# define CYGARC_REG_ICR1 0xa4000010 +# define CYGARC_REG_ICR2 0xa4000012 +# define CYGARC_REG_INTER 0xa4000014 +# define CYGARC_REG_IPRC 0xa4000016 +# define CYGARC_REG_IPRD 0xa4000018 +# define CYGARC_REG_IPRE 0xa400001a + + +#define CYGARC_REG_IPRC_IRQ3_MASK 0xf000 +#define CYGARC_REG_IPRC_IRQ3_PRI1 0x1000 +#define CYGARC_REG_IPRC_IRQ2_MASK 0x0f00 +#define CYGARC_REG_IPRC_IRQ2_PRI1 0x0100 +#define CYGARC_REG_IPRC_IRQ1_MASK 0x00f0 +#define CYGARC_REG_IPRC_IRQ1_PRI1 0x0010 +#define CYGARC_REG_IPRC_IRQ0_MASK 0x000f +#define CYGARC_REG_IPRC_IRQ0_PRI1 0x0001 + +#define CYGARC_REG_IPRD_PINT07_MASK 0xf000 +#define CYGARC_REG_IPRD_PINT07_PRI1 0x1000 +#define CYGARC_REG_IPRD_PINT8F_MASK 0x0f00 +#define CYGARC_REG_IPRD_PINT8F_PRI1 0x0100 +#define CYGARC_REG_IPRD_IRQ5_MASK 0x00f0 +#define CYGARC_REG_IPRD_IRQ5_PRI1 0x0010 +#define CYGARC_REG_IPRD_IRQ4_MASK 0x000f +#define CYGARC_REG_IPRD_IRQ4_PRI1 0x0001 + +#define CYGARC_REG_IPRE_DMAC_MASK 0xf000 +#define CYGARC_REG_IPRE_DMAC_PRI1 0x1000 +#define CYGARC_REG_IPRE_IRDA_MASK 0x0f00 +#define CYGARC_REG_IPRE_IRDA_PRI1 0x0100 +#define CYGARC_REG_IPRE_SCIF_MASK 0x00f0 +#define CYGARC_REG_IPRE_SCIF_PRI1 0x0010 +#define CYGARC_REG_IPRE_ADC_MASK 0x000f +#define CYGARC_REG_IPRE_ADC_PRI1 0x0001 + +#define CYGARC_REG_ICR1_MAI 0x8000 +#define CYGARC_REG_ICR1_IRQLVL 0x4000 +#define CYGARC_REG_ICR1_BLMSK 0x2000 +#define CYGARC_REG_ICR1_IRLSEN 0x1000 +#define CYGARC_REG_ICR1_SENSE_IRQ5_shift 10 +#define CYGARC_REG_ICR1_SENSE_IRQ4_shift 8 +#define CYGARC_REG_ICR1_SENSE_IRQ3_shift 6 +#define CYGARC_REG_ICR1_SENSE_IRQ2_shift 4 +#define CYGARC_REG_ICR1_SENSE_IRQ1_shift 2 +#define CYGARC_REG_ICR1_SENSE_IRQ0_shift 0 +#define CYGARC_REG_ICR1_SENSE_LEVEL 0x2 +#define CYGARC_REG_ICR1_SENSE_UP 0x1 + +// The (initial) IRQ mode is controlled by configuration. +#ifdef CYGHWR_HAL_SH_IRQ_USE_IRQLVL +# ifdef CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS +# define CYGARC_REG_ICR1_INIT (CYGARC_REG_ICR1_IRLSEN|CYGARC_REG_ICR1_IRQLVL) +# else +# define CYGARC_REG_ICR1_INIT (CYGARC_REG_ICR1_IRQLVL) +# endif +#else +# define CYGARC_REG_ICR1_INIT 0x0000 +#endif + +#define CYGARC_REG_IRR0_PINT07 0x80 +#define CYGARC_REG_IRR0_PINT8F 0x40 +#define CYGARC_REG_IRR0_IRQ5 0x20 +#define CYGARC_REG_IRR0_IRQ4 0x10 +#define CYGARC_REG_IRR0_IRQ3 0x08 +#define CYGARC_REG_IRR0_IRQ2 0x04 +#define CYGARC_REG_IRR0_IRQ1 0x02 +#define CYGARC_REG_IRR0_IRQ0 0x01 + +#endif + + + +#if (CYGARC_SH_MOD_INTC >= 3) +# define CYGARC_REG_IRR3 0xa400000a +# define CYGARC_REG_IRR4 0xa400000c +# define CYGARC_REG_IPRF 0xa400001c + +#define CYGARC_REG_IPRF_LCDI_MASK 0x0f00 +#define CYGARC_REG_IPRF_LCDI_PRI1 0x0100 +#define CYGARC_REG_IPRF_PCC0_MASK 0x00f0 +#define CYGARC_REG_IPRF_PCC0_PRI1 0x0010 +#define CYGARC_REG_IPRF_PCC1_MASK 0x000f +#define CYGARC_REG_IPRF_PCC1_PRI1 0x0001 + +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_mmu.h @@ -0,0 +1,50 @@ +//============================================================================= +// +// mod_regs_mmu.h +// +// MMU Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// MMU control registers +#define CYGARC_REG_MMUCR 0xffffffe0 + +#define CYGARC_REG_MMUCR_SV 0x00000100 +#define CYGARC_REG_MMUCR_RC_MASK 0x000000c0 +#define CYGARC_REG_MMUCR_TF 0x00000004 +#define CYGARC_REG_MMUCR_IX 0x00000002 +#define CYGARC_REG_MMUCR_AT 0x00000001
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_pfc.h @@ -0,0 +1,100 @@ +//============================================================================= +// +// mod_regs_pfc.h +// +// PFC (pin function controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#define CYGARC_REG_PACR 0xa4000100 // port A control +#define CYGARC_REG_PBCR 0xa4000102 // port B control +#define CYGARC_REG_PCCR 0xa4000104 // port C control +#define CYGARC_REG_PDCR 0xa4000106 // port D control +#define CYGARC_REG_PECR 0xa4000108 // port E control +#define CYGARC_REG_PFCR 0xa400010a // port F control +#define CYGARC_REG_PGCR 0xa400010c // port G control +#define CYGARC_REG_PHCR 0xa400010e // port H control +#define CYGARC_REG_PJCR 0xa4000110 // port J control +#define CYGARC_REG_PKCR 0xa4000112 // port K control +#define CYGARC_REG_PLCR 0xa4000114 // port L control +#define CYGARC_REG_SCPCR 0xa4000116 // SC port control + +#define CYGARC_REG_PADR 0xa4000120 // port A data +#define CYGARC_REG_PBDR 0xa4000122 // port B data +#define CYGARC_REG_PCDR 0xa4000124 // port C data +#define CYGARC_REG_PDDR 0xa4000126 // port D data +#define CYGARC_REG_PEDR 0xa4000128 // port E data +#define CYGARC_REG_PFDR 0xa400012a // port F data +#define CYGARC_REG_PGDR 0xa400012c // port G data +#define CYGARC_REG_PHDR 0xa400012e // port H data +#define CYGARC_REG_PJDR 0xa4000130 // port J data +#define CYGARC_REG_PKDR 0xa4000132 // port K data +#define CYGARC_REG_PLDR 0xa4000134 // port L data +#define CYGARC_REG_SCPDR 0xa4000136 // SC port data + + +// Port C +#define CYGARC_REG_PCCR_PC7_MASK 0xc000 +#define CYGARC_REG_PCCR_PC7_shift 14 +#define CYGARC_REG_PCCR_PC6_MASK 0x3000 +#define CYGARC_REG_PCCR_PC6_shift 12 +#define CYGARC_REG_PCCR_PC5_MASK 0x0c00 +#define CYGARC_REG_PCCR_PC5_shift 10 +#define CYGARC_REG_PCCR_PC4_MASK 0x0300 +#define CYGARC_REG_PCCR_PC4_shift 8 +#define CYGARC_REG_PCCR_PC3_MASK 0x00c0 +#define CYGARC_REG_PCCR_PC3_shift 6 +#define CYGARC_REG_PCCR_PC2_MASK 0x0030 +#define CYGARC_REG_PCCR_PC2_shift 4 +#define CYGARC_REG_PCCR_PC1_MASK 0x000c +#define CYGARC_REG_PCCR_PC1_shift 2 +#define CYGARC_REG_PCCR_PC0_MASK 0x0003 +#define CYGARC_REG_PCCR_PC0_shift 0 + +#define CYGARC_REG_PCCR_MD_OTHER 0x0 +#define CYGARC_REG_PCCR_MD_OUT 0x1 +#define CYGARC_REG_PCCR_MD_IN_ON 0x2 +#define CYGARC_REG_PCCR_MD_IN_OFF 0x3 + +#define CYGARC_REG_PCDR_PC7DT 0x80 +#define CYGARC_REG_PCDR_PC6DT 0x40 +#define CYGARC_REG_PCDR_PC5DT 0x20 +#define CYGARC_REG_PCDR_PC4DT 0x10 +#define CYGARC_REG_PCDR_PC3DT 0x08 +#define CYGARC_REG_PCDR_PC2DT 0x04 +#define CYGARC_REG_PCDR_PC1DT 0x02 +#define CYGARC_REG_PCDR_PC0DT 0x01 +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_rtc.h @@ -0,0 +1,77 @@ +//============================================================================= +// +// mod_regs_rtc.h +// +// RTC (real time clock) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// RealTime Clock + +#define CYGARC_REG_RC64CNT 0xfffffec0 +#define CYGARC_REG_RSECCNT 0xfffffec2 +#define CYGARC_REG_RMINCNT 0xfffffec4 +#define CYGARC_REG_RHRCNT 0xfffffec6 +#define CYGARC_REG_RWKCNT 0xfffffec8 +#define CYGARC_REG_RDAYCNT 0xfffffeca +#define CYGARC_REG_RMONCNT 0xfffffecc +#define CYGARC_REG_RYRCNT 0xfffffece +#define CYGARC_REG_RSECAR 0xfffffed0 +#define CYGARC_REG_RMINAR 0xfffffed2 +#define CYGARC_REG_RHRAR 0xfffffed4 +#define CYGARC_REG_RWKAR 0xfffffed6 +#define CYGARC_REG_RDAYAR 0xfffffed8 +#define CYGARC_REG_RMONAR 0xfffffeda +#define CYGARC_REG_RCR1 0xfffffedc +#define CYGARC_REG_RCR2 0xfffffede + + +#define CYGARC_REG_RCR1_CF 0x80 // carry flag +#define CYGARC_REG_RCR1_CIE 0x10 // carry interrupt enable +#define CYGARC_REG_RCR1_AIE 0x08 // alarm interrupt enable +#define CYGARC_REG_RCR1_AF 0x01 // alarm flag + +#define CYGARC_REG_RCR2_PEF 0x80 // periodic interrupt flag +#define CYGARC_REG_RCR2_PES2 0x40 // periodic interrupt setting +#define CYGARC_REG_RCR2_PES1 0x20 +#define CYGARC_REG_RCR2_PES0 0x10 +#define CYGARC_REG_RCR2_RTCEN 0x08 // RTC enable +#define CYGARC_REG_RCR2_ADJ 0x04 // second adjustment +#define CYGARC_REG_RCR2_RESET 0x02 // reset +#define CYGARC_REG_RCR2_START 0x01 // start + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_ser.h @@ -0,0 +1,278 @@ +//============================================================================= +// +// mod_regs_ser.h +// +// SCI, SCIF, and IRDA (serial) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// Note: All three serial module definitions kept in the same file +// since they share some of the information. +//####DESCRIPTIONEND#### +// +//============================================================================= + +//++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//-------------------------------------------------------------------------- +// Serial registers. All 8 bit registers. +#define CYGARC_REG_SCSMR 0xfffffe80 // serial mode register +#define CYGARC_REG_SCBRR 0xfffffe82 // bit rate register +#define CYGARC_REG_SCSCR 0xfffffe84 // serial control register +#define CYGARC_REG_SCTDR 0xfffffe86 // transmit data register +#define CYGARC_REG_SCSSR 0xfffffe88 // serial status register +#define CYGARC_REG_SCRDR 0xfffffe8a // receive data register + +// Serial Mode Register +#define CYGARC_REG_SCSMR_CA 0x80 // communication mode +#define CYGARC_REG_SCSMR_CHR 0x40 // character length (7 if set) +#define CYGARC_REG_SCSMR_PE 0x20 // parity enable +#define CYGARC_REG_SCSMR_OE 0x10 // parity mode +#define CYGARC_REG_SCSMR_STOP 0x08 // stop bit length +#define CYGARC_REG_SCSMR_MP 0x04 // multiprocessor mode +#define CYGARC_REG_SCSMR_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR_MPIE 0x08 // multiprocessor interrupt enable +#define CYGARC_REG_SCSCR_TEIE 0x04 // transmit-end interrupt enable +#define CYGARC_REG_SCSCR_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR_TDRE 0x80 // transmit data register empty +#define CYGARC_REG_SCSSR_RDRF 0x40 // receive data register full +#define CYGARC_REG_SCSSR_ORER 0x20 // overrun error +#define CYGARC_REG_SCSSR_FER 0x10 // framing error +#define CYGARC_REG_SCSSR_PER 0x08 // parity error +#define CYGARC_REG_SCSSR_TEND 0x04 // transmit end +#define CYGARC_REG_SCSSR_MPB 0x02 // multiprocessor bit +#define CYGARC_REG_SCSSR_MPBT 0x01 // multiprocessor bit transfer + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR_CLEARMASK 0xf8 + + +#if (CYGARC_SH_MOD_SCI >= 2) +# define CYGARC_REG_SCSPTR 0xfffffe7c // serial port register +#endif + + +// Baud rate values calculation, depending on peripheral clock (Pf) +// n is CKS setting (0-3) +// N = (Pf/(64*2^(2n-1)*B))-1 +// With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get +// N = (Pf/(32*_CKS*B))-1 +// +// The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS +// setting for the given baud rate and peripheral clock. +// +// The error of the CKS+count value can be computed by: +// E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100 +// +#define CYGARC_SCBRR_PRESCALE(_b_) \ +((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \ + (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \ + (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64) + +// These two macros provide the static values we need to stuff into the +// registers. +#define CYGARC_SCBRR_CKSx(_b_) \ + ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \ + (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \ + (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3) +#define CYGARC_SCBRR_N(_b_) \ + (((_b_) < 4800) ? 0 : \ + ((_b_) > 115200) ? 0 : \ + ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1)) + + +//++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_IRDA + +//-------------------------------------------------------------------------- +// IrDA (infrared data association). Can also act as regular serial w FIFO + +#define CYGARC_REG_SCSMR1 0xa4000140 +#define CYGARC_REG_SCBRR1 0xa4000142 +#define CYGARC_REG_SCSCR1 0xa4000144 +#define CYGARC_REG_SCFTDR1 0xa4000146 +#define CYGARC_REG_SCSSR1 0xa4000148 +#define CYGARC_REG_SCFRDR1 0xa400014a +#define CYGARC_REG_SCFCR1 0xa400014c +#define CYGARC_REG_SCFDR1 0xa400014e + +// Serial Mode Register +#define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode +#define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width +#define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?) +#define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR1_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR1_PER_shift 12 +#define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR1_FER_shift 8 +#define CYGARC_REG_SCSSR1_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR1_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR1_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR1_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test + + +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR1_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR1_TCOUNT_shift 8 + +#endif // CYGARC_SH_MOD_IRDA + +//++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_SCIF + +//-------------------------------------------------------------------------- +// Serial w FIFO registers + +#define CYGARC_REG_SCSMR2 0xa4000150 // Serial mode +#define CYGARC_REG_SCBRR2 0xa4000152 // Bit rate +#define CYGARC_REG_SCSCR2 0xa4000154 // Serial control +#define CYGARC_REG_SCFTDR2 0xa4000156 // Transmit FIFO data +#define CYGARC_REG_SCSSR2 0xa4000158 // Serial status +#define CYGARC_REG_SCFRDR2 0xa400015a // Receive data FIFO +#define CYGARC_REG_SCFCR2 0xa400015c // FIFO control register +#define CYGARC_REG_SCFDR2 0xa400015e // FIFO data count set + +// Serial Mode Register +#define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set) +#define CYGARC_REG_SCSMR2_PE 0x20 // parity enable +#define CYGARC_REG_SCSMR2_OE 0x10 // parity mode +#define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length +#define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR2_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR2_PER_shift 12 +#define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR2_FER_shift 8 +#define CYGARC_REG_SCSSR2_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR2_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR2_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR2_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test + + +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR2_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR2_TCOUNT_shift 8 + +#endif // CYGARC_SH_MOD_SCIF
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_tmu.h @@ -0,0 +1,79 @@ +//============================================================================= +// +// mod_regs_tmu.h +// +// TMU (timer unit) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// TMU registers +#define CYGARC_REG_TOCR 0xfffffe90 // 8 bit +#define CYGARC_REG_TSTR 0xfffffe92 // 8 bit +#define CYGARC_REG_TCOR0 0xfffffe94 // 32 bit +#define CYGARC_REG_TCNT0 0xfffffe98 // 32 bit +#define CYGARC_REG_TCR0 0xfffffe9c // 16 bit +#define CYGARC_REG_TCOR1 0xfffffea0 // 32 bit +#define CYGARC_REG_TCNT1 0xfffffea4 // 32 bit +#define CYGARC_REG_TCR1 0xfffffea8 // 16 bit +#define CYGARC_REG_TCOR2 0xfffffeac // 32 bit +#define CYGARC_REG_TCNT2 0xfffffeb0 // 32 bit +#define CYGARC_REG_TCR2 0xfffffeb4 // 16 bit +#define CYGARC_REG_TCPR2 0xfffffeb8 // 32 bit + +// TSTR +#define CYGARC_REG_TSTR_STR0 0x0001 +#define CYGARC_REG_TSTR_STR1 0x0002 +#define CYGARC_REG_TSTR_STR2 0x0004 + +// TCR0/1/2 +#define CYGARC_REG_TCR_TPSC0 0x0001 +#define CYGARC_REG_TCR_TPSC1 0x0002 +#define CYGARC_REG_TCR_TPSC2 0x0004 +#define CYGARC_REG_TCR_CKEG0 0x0008 +#define CYGARC_REG_TCR_CKEG1 0x0010 +#define CYGARC_REG_TCR_UNIE 0x0020 +#define CYGARC_REG_TCR_UNF 0x0100 + +#define CYGARC_REG_TCR_TPSC_4 (0) +#define CYGARC_REG_TCR_TPSC_16 (CYGARC_REG_TCR_TPSC0) +#define CYGARC_REG_TCR_TPSC_64 (CYGARC_REG_TCR_TPSC1) +#define CYGARC_REG_TCR_TPSC_256 (CYGARC_REG_TCR_TPSC0|CYGARC_REG_TCR_TPSC1) + +// TCR2 additional bits +#define CYGARC_REG_TCR_ICPE0 0x0040 +#define CYGARC_REG_TCR_ICPE1 0x0080 +#define CYGARC_REG_TCR_ICPF 0x0200
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/mod_regs_ubc.h @@ -0,0 +1,95 @@ +//============================================================================= +// +// mod_regs_ubc.h +// +// UBC (user break controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// User Break Control +#define CYGARC_REG_BRCR 0xffffff98 // 16 bit + +#define CYGARC_REG_BARA 0xffffffb0 // 32 bit +#define CYGARC_REG_BAMRA 0xffffffb4 // 8 bit (v1) / 32 bit +#define CYGARC_REG_BBRA 0xffffffb8 // 16 bit +#define CYGARC_REG_BASRA 0xffffffe4 // 8 bit + +#define CYGARC_REG_BARB 0xffffffa0 // 32 bit +#define CYGARC_REG_BAMRB 0xffffffa4 // 8 bit (v1) / 32 bit +#define CYGARC_REG_BASRB 0xffffffe8 // 8 bit +#define CYGARC_REG_BBRB 0xffffffa8 // 16 bit +#define CYGARC_REG_BDRB 0xffffff90 // 32 bit +#define CYGARC_REG_BDMRB 0xffffff94 // 32 bit + + +#define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A +#define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B +#define CYGARC_REG_BRCR_PCBA 0x0400 // post execute channel A +#define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B +#define CYGARC_REG_BRCR_PCBB 0x0040 // post execute channel B +#define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select + +#if (CYGARC_SH_MOD_UBC == 1) +#define CYGARC_REG_BAMRA_BASMA 0x04 // BASRA masked +#define CYGARC_REG_BAMRA_BARA_UNMASKED 0x00 // BARA not masked +#define CYGARC_REG_BAMRA_BARA_10BIT 0x01 // Lowest 10 bit masked +#define CYGARC_REG_BAMRA_BARA_12BIT 0x02 // Lowest 12 bit masked +#define CYGARC_REG_BAMRA_BARA_MASKED 0x03 // All bits masked +#else +// mask is fully configurable in other versions of the UBC +#endif + +#define CYGARC_REG_BBRA_DFETCH 0x0020 // Break on DFETCH +#define CYGARC_REG_BBRA_IFETCH 0x0010 // Break on IFETCH +#define CYGARC_REG_BBRA_WRITE 0x0008 // Break on WRITE +#define CYGARC_REG_BBRA_READ 0x0004 // Break on READ +#define CYGARC_REG_BBRA_SIZE_LONG 0x0003 // Break on long access +#define CYGARC_REG_BBRA_SIZE_WORD 0x0002 // Break on word access +#define CYGARC_REG_BBRA_SIZE_BYTE 0x0001 // Break on byte access +#define CYGARC_REG_BBRA_SIZE_ANY 0x0000 // Break on any size + + +//---------------------------------------------------------------------------- +// Other types +#if (CYGARC_SH_MOD_UBC >= 3) +#define CYGARC_REG_BETR 0xffffff9c // 16 bit +#define CYGARC_REG_BRSR 0xffffffac // 32 bit +#define CYGARC_REG_BRDR 0xffffffbc // 32 bit + +#define CYGARC_REG_BBRA_DMA 0x0080 // Break on DMAC cycle +#define CYGARC_REG_BBRA_CPU 0x0040 // Break on CPU cycle +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/sh3_sci.h @@ -0,0 +1,81 @@ +//============================================================================= +// +// sh3_sci.h +// +// Simple driver for the SH Serial Communication Interface (SCI) +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-05-17 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH3_SCI_PORTS + +//-------------------------------------------------------------------------- +// SCI register offsets +#if (CYGARC_SH_MOD_SCI >= 2) +# define _REG_SCSPTR -0x4 // serial port register +#endif +#define _REG_SCSMR 0x0 // serial mode register +#define _REG_SCBRR 0x2 // bit rate register +#define _REG_SCSCR 0x4 // serial control register +#define _REG_SCTDR 0x6 // transmit data register +#define _REG_SCSSR 0x8 // serial status register +#define _REG_SCRDR 0xa // receive data register + +//-------------------------------------------------------------------------- + +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +//-------------------------------------------------------------------------- + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +// This one should only be used by old-stub compatibility code! +externC void cyg_hal_plf_sci_init_channel(const channel_data_t* chan); +#endif + +externC cyg_uint8 cyg_hal_plf_sci_getc(void* __ch_data); +externC void cyg_hal_plf_sci_putc(void* __ch_data, cyg_uint8 c); +externC void cyg_hal_plf_sci_init(int sci_index, int comm_index, + int rcv_vect, cyg_uint8* base); + + +#endif // CYGNUM_HAL_SH_SH3_SCI_PORTS +//----------------------------------------------------------------------------- +// end of sh3_sci.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/sh3_scif.h @@ -0,0 +1,88 @@ +//============================================================================= +// +// sh3_scif.h +// +// Simple driver for the SH3 Serial Communication Interface with FIFO +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-03-30 +// Description: Simple driver for the SH Serial Communication Interface +// The driver can be used for either the SCIF or the IRDA +// modules (the latter can act as the former). +// Clients of this file can configure the behavior with: +// CYGNUM_SCIF_PORTS: number of SCI ports +// +// Note: It should be possible to configure a channel to IRDA mode. +// Worry about that when some board needs it. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH3_SCIF_PORTS + +//-------------------------------------------------------------------------- +// SCIF register offsets +#define _REG_SCSMR 0x00 +#define _REG_SCBRR 0x02 +#define _REG_SCSCR 0x04 +#define _REG_SCFTDR 0x06 +#define _REG_SCSSR 0x08 +#define _REG_SCFRDR 0x0a +#define _REG_SCFCR 0x0c +#define _REG_SCFDR 0x0e + +//-------------------------------------------------------------------------- + +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +//-------------------------------------------------------------------------- + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +// This one should only be used by old-stub compatibility code! +externC void cyg_hal_plf_scif_init_channel(const channel_data_t* chan); +#endif + +externC cyg_uint8 cyg_hal_plf_scif_getc(void* __ch_data); +externC void cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c); +void cyg_hal_plf_scif_init(int scif_index, int comm_index, + int rcv_vect, cyg_uint8* base); + + +#endif // CYGNUM_HAL_SH_SH3_SCIF_PORTS +//----------------------------------------------------------------------------- +// end of sh3_scif.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/var_cache.h @@ -0,0 +1,295 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H + +//============================================================================= +// +// var_cache.h +// +// HAL variant cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-04-23 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros + +#include CYGBLD_HAL_CPU_MODULES_H // cache module specs + +#include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions + +//----------------------------------------------------------------------------- +// Cache dimensions - one unified cache + +#define HAL_CACHE_UNIFIED + +#define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE +#define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE +#define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS + +// Cache addressing information +#define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE +#define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP +#define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP + +// Writing this to a cache address entry forces a flush of the line if +// it is dirty. +#define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH + +#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of cache + +// This is all handled in assembly (see variant.S) due to a requirement about +// not fiddling the cache from cachable memory. + +externC void cyg_hal_cache_enable(void); +externC void cyg_hal_cache_disable(void); +externC void cyg_hal_cache_invalidate_all(void); +externC void cyg_hal_cache_sync(void); +externC void cyg_hal_cache_sync_region(cyg_haladdress base, + cyg_haladdrword len); +externC void cyg_hal_cache_write_mode(int mode); + +// Enable the cache +#define HAL_UCACHE_ENABLE() cyg_hal_cache_enable() + +// Disable the cache +#define HAL_UCACHE_DISABLE() cyg_hal_cache_disable() + +// Invalidate the entire cache +#define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all() + +// Synchronize the contents of the cache with memory. +#define HAL_UCACHE_SYNC() cyg_hal_cache_sync() + +// Query the state of the cache (does not affect the caching) +#define HAL_UCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \ + (_state_) &= ~CYGARC_REG_CCR_CE; \ + CYG_MACRO_END + +// Set the cache refill burst size +//#define HAL_UCACHE_BURST_SIZE(_size_) + +// Set the cache write mode +#define HAL_UCACHE_WRITE_MODE( _mode_ ) \ + CYG_MACRO_START \ + cyg_uint32 _m_; \ + if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \ + _m_ = CYGARC_REG_CCR_WT; \ + else \ + _m_ = CYGARC_REG_CCR_CB; \ + cyg_hal_cache_write_mode(_m_); \ + CYG_MACRO_END + +#define HAL_UCACHE_WRITETHRU_MODE 0 +#define HAL_UCACHE_WRITEBACK_MODE 1 + +// This macro allows the client to specify separate modes for the two +// regions. +#define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_) + +// Load the contents of the given address range into the cache +// and then lock the cache so that it stays there. +//#define HAL_UCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_UCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_UCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_UCACHE_FLUSH( _base_ , _size_ ) \ + cyg_hal_cache_sync_region((cyg_haladdress) _base_, (cyg_haladdrword)_size_) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_UCACHE_STORE( _base_ , _size_ ) + + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_UCACHE_ZERO( _base_ , _size_ ) + + +//----------------------------------------------------------------------------- +// Data and instruction cache macros map onto the both-cache macros + +//----------------------------------------------------------------------------- +// Global control of data cache + +#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE +#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS +#define HAL_DCACHE_SETS HAL_UCACHE_SETS + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE +#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS +#define HAL_ICACHE_SETS HAL_UCACHE_SETS + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. + +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/var_intr.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_VAR_INTR_H +#define CYGONCE_VAR_INTR_H + +//========================================================================== +// +// var_intr.h +// +// HAL variant interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, +// Date: 1999-04-24 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_CPU_MODULES_H // INTC module selection + +//---------------------------------------------------------------------------- +// Additional vectors provided by INTC V2 + +#if (CYGARC_SH_MOD_INTC >= 2) +#define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32 +#define CYGNUM_HAL_INTERRUPT_HUDI_HUDI 33 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 34 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 35 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 36 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 37 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 38 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 39 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6C0 40 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41 +#define CYGNUM_HAL_INTERRUPT_PINT_PINT07 42 +#define CYGNUM_HAL_INTERRUPT_PINT_PINT8F 43 +#define CYGNUM_HAL_INTERRUPT_RESERVED_740 44 +#define CYGNUM_HAL_INTERRUPT_RESERVED_760 45 +#define CYGNUM_HAL_INTERRUPT_RESERVED_780 46 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7A0 47 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7C0 48 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7E0 59 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI0 50 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI1 51 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI2 52 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI3 53 +#define CYGNUM_HAL_INTERRUPT_IRDA_ERI1 54 +#define CYGNUM_HAL_INTERRUPT_IRDA_RXI1 55 +#define CYGNUM_HAL_INTERRUPT_IRDA_BRI1 56 +#define CYGNUM_HAL_INTERRUPT_IRDA_TXI1 57 +#define CYGNUM_HAL_INTERRUPT_SCIF_ERI2 58 +#define CYGNUM_HAL_INTERRUPT_SCIF_RXI2 59 +#define CYGNUM_HAL_INTERRUPT_SCIF_BRI2 60 +#define CYGNUM_HAL_INTERRUPT_SCIF_TXI2 61 +#define CYGNUM_HAL_INTERRUPT_ADC_ADI 62 + +#undef CYGNUM_HAL_ISR_MAX +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC_ADI + +#endif // CYGARC_SH_MOD_INTC >= 2 + +//---------------------------------------------------------------------------- +// Additional vectors provided by INTC V3 + +#if (CYGARC_SH_MOD_INTC >= 3) +#define CYGNUM_HAL_INTERRUPT_LCDC_LCDI 63 +#define CYGNUM_HAL_INTERRUPT_PCC_PCC0 64 +#define CYGNUM_HAL_INTERRUPT_PCC_PCC1 65 + +#undef CYGNUM_HAL_ISR_MAX +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PCC_PCC1 + +#endif // CYGARC_SH_MOD_INTC >= 3 + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/var_regs.h @@ -0,0 +1,100 @@ +#ifndef CYGONCE_VAR_SH_REGS_H +#define CYGONCE_VAR_SH_REGS_H +//============================================================================= +// +// sh_regs.h +// +// SH CPU definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-04-24 +// Purpose: Define CPU memory mapped registers etc. +// Usage: #include <cyg/hal/sh_regs.h> +// Notes: +// This file describes registers for on-core modules found in all +// the SH3 CPUs supported by the HAL. For each CPU is defined a +// module specification file (mod_<CPU model number>.h) which lists +// modules (and their version if applicable) included in that +// particular CPU model. Note that the versioning is ad hoc; +// it doesn't reflect Hitachi internal versioning in any way. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Find out which modules are supported by the chosen CPU +#include <pkgconf/system.h> +#include CYGBLD_HAL_CPU_MODULES_H + +//========================================================================== +// CPU Definitions +//========================================================================== + +//-------------------------------------------------------------------------- +// Status register +#define CYGARC_REG_SR_MD 0x40000000 +#define CYGARC_REG_SR_RB 0x20000000 +#define CYGARC_REG_SR_BL 0x10000000 +#define CYGARC_REG_SR_M 0x00000200 +#define CYGARC_REG_SR_Q 0x00000100 +#define CYGARC_REG_SR_IMASK 0x000000f0 +#define CYGARC_REG_SR_I3 0x00000080 +#define CYGARC_REG_SR_I2 0x00000040 +#define CYGARC_REG_SR_I1 0x00000020 +#define CYGARC_REG_SR_I0 0x00000010 +#define CYGARC_REG_SR_S 0x00000002 +#define CYGARC_REG_SR_T 0x00000001 + + +//========================================================================== +// Module Definitions +//========================================================================== + +#include <cyg/hal/mod_regs_bsc.h> +#include <cyg/hal/mod_regs_cac.h> +#include <cyg/hal/mod_regs_cpg.h> +#include <cyg/hal/mod_regs_intc.h> +#include <cyg/hal/mod_regs_mmu.h> +#include <cyg/hal/mod_regs_rtc.h> +#include <cyg/hal/mod_regs_ser.h> +#include <cyg/hal/mod_regs_tmu.h> +#include <cyg/hal/mod_regs_ubc.h> + +#ifdef CYGARC_SH_MOD_DMAC +#include <cyg/hal/mod_regs_dma.h> +#endif +#ifdef CYGARC_SH_MOD_PFC +#include <cyg/hal/mod_regs_pfc.h> +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_SH_REGS_H +// End of var_regs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/include/variant.inc @@ -0,0 +1,188 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## SH3 variant assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-10-30 +## Purpose: SH3 variant definitions and init code +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the SH3 CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/sh_regs.h> + +#=========================================================================== +# SR initialization value +# zero all bits except: +# MD = Processor operation mode field (privileged mode) +# I0-3 = Mask out all interrupts but NMI. +# +# When saving or restoring the state of an exception or interrupt, the bit +# CYGARC_REG_SR_RB is also set, switching the register bank. When this bit +# is set, interrupts must be disabled. +# +# Note: We could also use the BL bit to prevent interrupts, but that would +# also prevent the use of breakpoints. + +#define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK) +#define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) + +##----------------------------------------------------------------------------- +## Hardware init macros +#ifndef CYGPKG_HAL_SH_POST_RESET_INIT + .macro hal_post_reset_init + # Initialize CPU + mov.l $nCYG_SR,r1 ! Put CPU in a well-known state + ldc r1,sr + mov #0,r0 + mov #CYGARC_REG_CCR,r1 ! Disable cache + mov.l r0,@r1 + mov #CYGARC_REG_MMUCR,r1 ! Disable MMU + mov.l r0,@r1 + mov #CYGARC_REG_BBRA,r1 ! Disable UBC Channel A + mov.w r0,@r1 + mov #CYGARC_REG_BBRB,r1 ! Disable UBC Channel B + mov.w r0,@r1 + mov #CYGARC_REG_BRCR,r1 ! Reset UBC common register + mov.w r0,@r1 + mov.l $CYGARC_REG_TSTR,r1 ! Disable timers + mov.b r0,@r1 + mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRB,r1 + mov.w r0,@r1 +#if (CYGARC_SH_MOD_INTC >= 2) + mov.l $CYGARC_REG_IPRC,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRD,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRE,r1 + mov.w r0,@r1 +#if (CYGARC_SH_MOD_INTC >= 3) + mov.l $CYGARC_REG_IPRF,r1 + mov.w r0,@r1 +#endif + mov.w $nCYG_ICR1_INIT,r0 + mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode + mov.w r0,@r1 +#endif + mov.w $nCYG_WTCSR,r0 ! Clear watchdog + mov #CYGARC_REG_WTCSR,r1 + mov.w r0,@r1 + + # Initialize VBR if necessary +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + mov.l $__reset,r1 ! Set VBR + ldc r1,vbr +#endif + bra 1f + nop + +$nCYG_WTCSR: + .word 0xa500 ! clear all CSR bits + + .align 2 +$nCYG_SR: + .long CYG_SR +$CYGARC_REG_TSTR: + .long CYGARC_REG_TSTR +$CYGARC_REG_IPRA: + .long CYGARC_REG_IPRA +$CYGARC_REG_IPRB: + .long CYGARC_REG_IPRB +#if (CYGARC_SH_MOD_INTC >= 2) +$CYGARC_REG_IPRC: + .long CYGARC_REG_IPRC +$CYGARC_REG_IPRD: + .long CYGARC_REG_IPRD +$CYGARC_REG_IPRE: + .long CYGARC_REG_IPRE +$CYGARC_REG_ICR1: + .long CYGARC_REG_ICR1 +$nCYG_ICR1_INIT: + .word CYGARC_REG_ICR1_INIT + .align 2 +#endif +#if (CYGARC_SH_MOD_INTC >= 3) +$CYGARC_REG_IPRF: + .long CYGARC_REG_IPRF +#endif +$__reset: + .long __reset + +1: + .endm +#define CYGPKG_HAL_SH_POST_RESET_INIT +#endif + +##----------------------------------------------------------------------------- +## Interrupt decode macros + .macro hal_intc_decode tmp,inum +#if (CYGARC_SH_MOD_INTC >= 2) + mov.l $nCYGARC_REG_INTEVT2,\tmp +#else + mov #CYGARC_REG_INTEVT,\tmp +#endif + mov.l @\tmp,\inum + mov #-5,\tmp ! divide cause by 0x20 + shld \tmp,\inum + add #-14,\inum ! adjust so NMI becomes 0 + + .endm + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + .macro hal_intc_translate inum,vnum + mov #0,\vnum ! Just vector zero is supported + .endm +#else + .macro hal_intc_translate inum,vnum + mov \inum,\vnum ! Vector == interrupt number + shll2 \vnum ! get from vector number to ISR index + .endm +#endif + +#------------------------------------------------------------------------------ +#endif // CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/src/sh3_sci.c @@ -0,0 +1,307 @@ +//============================================================================= +// +// sh3_sci.c +// +// Simple driver for the SH Serial Communication Interface (SCI) +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-05-17 +// Description: Simple driver for the SH Serial Communication Interface +// Clients of this file can configure the behavior with: +// CYGNUM_SCI_PORTS: number of SCI ports +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH3_SCI_PORTS + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP +#include <cyg/hal/hal_if.h> // Calling-if API +#include <cyg/hal/sh_regs.h> // serial register definitions + +#include <cyg/hal/sh3_sci.h> // our header + +//-------------------------------------------------------------------------- + +#ifndef CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE +# define CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE 38400 +#endif + +void +cyg_hal_plf_sci_init_channel(const channel_data_t* chan) +{ + cyg_uint8 tmp; + cyg_uint8* base = chan->base; + + // Disable Tx/Rx interrupts, but enable Tx/Rx + HAL_WRITE_UINT8(base+_REG_SCSCR, + CYGARC_REG_SCSCR_TE|CYGARC_REG_SCSCR_RE); + + // 8-1-no parity. + HAL_WRITE_UINT8(base+_REG_SCSMR, 0); + + // Set speed to CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE + HAL_READ_UINT8(base+_REG_SCSMR, tmp); + tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK; + tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE); + HAL_WRITE_UINT8(base+_REG_SCSMR, tmp); + HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE)); +} + +static cyg_bool +cyg_hal_plf_sci_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 sr; + + HAL_READ_UINT8(base+_REG_SCSSR, sr); + if ((sr & CYGARC_REG_SCSSR_RDRF) == 0) + return false; + + HAL_READ_UINT8(base+_REG_SCRDR, *ch); + + // Clear buffer full flag. + HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_RDRF); + + return true; +} + +cyg_uint8 +cyg_hal_plf_sci_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_sci_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +void +cyg_hal_plf_sci_putc(void* __ch_data, cyg_uint8 c) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 sr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(base+_REG_SCSSR, sr); + } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0); + + HAL_WRITE_UINT8(base+_REG_SCTDR, c); + + // Clear empty flag. + HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_TDRE); + + // Hang around until the character has been safely sent. + do { + HAL_READ_UINT8(base+_REG_SCSSR, sr); + } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0); + + CYGARC_HAL_RESTORE_GP(); +} + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +static channel_data_t channels[CYGNUM_HAL_SH_SH3_SCI_PORTS]; + +static void +cyg_hal_plf_sci_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_sci_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_sci_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_sci_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_sci_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_sci_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_sci_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 scr; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); + scr |= CYGARC_REG_SCSCR_RIE; + HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); + scr &= ~CYGARC_REG_SCSCR_RIE; + HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + cyg_uint8 c, sr; + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + int res = 0; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + HAL_READ_UINT8(base+_REG_SCSSR, sr); + if (sr & CYGARC_REG_SCSSR_RDRF) { + HAL_READ_UINT8(base+_REG_SCRDR, c); + + // Clear buffer full flag. + HAL_WRITE_UINT8(base+_REG_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +void +cyg_hal_plf_sci_init(int sci_index, int comm_index, + int rcv_vect, cyg_uint8* base) +{ + channel_data_t* chan = &channels[sci_index]; + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Initialize channel table + chan->base = base; + chan->isr_vector = rcv_vect; + chan->msec_timeout = 1000; + + // Disable interrupts. + HAL_INTERRUPT_MASK(chan->isr_vector); + + // Init channel + + cyg_hal_plf_sci_init_channel(chan); + + // Setup procs in the vector table + + // Initialize channel procs + CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_sci_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_sci_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_sci_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_sci_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_sci_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_sci_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_sci_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +#endif // CYGNUM_HAL_SH_SH3_SCI_PORTS + +//----------------------------------------------------------------------------- +// end of sh_sci.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/src/sh3_scif.c @@ -0,0 +1,344 @@ +//============================================================================= +// +// sh3_scif.c +// +// Simple driver for the SH3 Serial Communication Interface with FIFO +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-03-30 +// Description: Simple driver for the SH Serial Communication Interface +// The driver can be used for either the SCIF or the IRDA +// modules (the latter can act as the former). +// Clients of this file can configure the behavior with: +// CYGNUM_SCIF_PORTS: number of SCI ports +// +// Note: It should be possible to configure a channel to IRDA mode. +// Worry about that when some board needs it. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH3_SCIF_PORTS + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP +#include <cyg/hal/hal_if.h> // Calling-if API +#include <cyg/hal/sh_regs.h> // serial register definitions +#include <cyg/hal/sh_stub.h> // target_register_t + +#include <cyg/hal/sh3_scif.h> // our header + +//-------------------------------------------------------------------------- + +#ifndef CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE +# define CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE 38400 +#endif + +void +cyg_hal_plf_scif_init_channel(const channel_data_t* chan) +{ + cyg_uint8* base = chan->base; + cyg_uint8 tmp; + cyg_uint16 sr; + + // Disable everything. + HAL_WRITE_UINT8(base+_REG_SCSCR, 0); + + // Reset FIFO. + HAL_WRITE_UINT8(base+_REG_SCFCR, + CYGARC_REG_SCFCR2_TFRST|CYGARC_REG_SCFCR2_RFRST); + + // 8-1-no parity. + HAL_WRITE_UINT8(base+_REG_SCSMR, 0); + + // Set speed to CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE + HAL_READ_UINT8(base+_REG_SCSMR, tmp); + tmp &= ~CYGARC_REG_SCSMR2_CKSx_MASK; + tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE); + HAL_WRITE_UINT8(base+_REG_SCSMR, tmp); + HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE)); + + // Let things settle: Here we should should wait the equivalent of + // one bit interval, + // i.e. 1/CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE second, but + // until we have something like the Linux delay loop, it's hard to + // do reliably. So just move on and hope for the best (this is + // unlikely to cause problems since the CPU has just come out of + // reset anyway). + + // Clear status register (read back first). + HAL_READ_UINT16(base+_REG_SCSSR, sr); + HAL_WRITE_UINT16(base+_REG_SCSSR, 0); + + // Bring FIFO out of reset and set to trigger on every char in + // FIFO (or C-c input would not be processed). + HAL_WRITE_UINT8(base+_REG_SCFCR, + CYGARC_REG_SCFCR2_RTRG_1|CYGARC_REG_SCFCR2_TTRG_1); + + // Leave Tx/Rx interrupts disabled, but enable Tx/Rx + HAL_WRITE_UINT8(base+_REG_SCSCR, + CYGARC_REG_SCSCR2_TE|CYGARC_REG_SCSCR2_RE); +} + +//static +cyg_bool +cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint16 fdr, sr; + + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + if (0 == (fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK)) + return false; + + HAL_READ_UINT8(base+_REG_SCFRDR, *ch); + + // Clear DR/RDF flags + HAL_READ_UINT16(base+_REG_SCSSR, sr); + HAL_WRITE_UINT16(base+_REG_SCSSR, + CYGARC_REG_SCSSR2_CLEARMASK & ~(CYGARC_REG_SCSSR2_RDF | CYGARC_REG_SCSSR2_DR)); + + return true; +} + +cyg_uint8 +cyg_hal_plf_scif_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_scif_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +void +cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint16 fdr, sr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + } while (((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) >> CYGARC_REG_SCFDR2_TCOUNT_shift) == 16); + + HAL_WRITE_UINT8(base+_REG_SCFTDR, c); + + // Clear FIFO-empty/transmit end flags (read back SR first) + HAL_READ_UINT16(base+_REG_SCSSR, sr); + HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCSSR2_CLEARMASK + & ~(CYGARC_REG_SCSSR2_TDFE | CYGARC_REG_SCSSR2_TEND )); + + // Hang around until the character has been safely sent. + do { + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + } while ((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) != 0); + + CYGARC_HAL_RESTORE_GP(); +} + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +static channel_data_t channels[CYGNUM_HAL_SH_SH3_SCIF_PORTS]; + +static void +cyg_hal_plf_scif_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_scif_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_scif_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_scif_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_scif_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_scif_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 scr; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); + scr |= CYGARC_REG_SCSCR2_RIE; + HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT8(chan->base+_REG_SCSCR, scr); + scr &= ~CYGARC_REG_SCSCR2_RIE; + HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + cyg_uint8 c; + cyg_uint16 fdr, sr; + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + int res = 0; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) != 0) { + HAL_READ_UINT8(base+_REG_SCFRDR, c); + + // Clear buffer full flag (read back first). + HAL_READ_UINT16(base+_REG_SCSSR, sr); + HAL_WRITE_UINT16(base+_REG_SCSSR, + CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +void +cyg_hal_plf_scif_init(int scif_index, int comm_index, + int rcv_vect, cyg_uint8* base) +{ + channel_data_t* chan = &channels[scif_index]; + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Initialize channel table + chan->base = base; + chan->isr_vector = rcv_vect; + chan->msec_timeout = 1000; + + // Disable interrupts. + HAL_INTERRUPT_MASK(chan->isr_vector); + + // Init channel + cyg_hal_plf_scif_init_channel(chan); + + // Setup procs in the vector table + + // Initialize channel procs + CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +#endif // CYGNUM_HAL_SH_SH3_SCIF_PORTS + +//----------------------------------------------------------------------------- +// end of sh3_scif.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/src/var_misc.c @@ -0,0 +1,439 @@ +//========================================================================== +// +// var_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, jlarmour, nickg +// Date: 1999-04-03 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> // diag_printf + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_cache.h> // HAL cache +#include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions + +//--------------------------------------------------------------------------- +// Initial cache enabling + +#ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK +# define CACHE_MODE_P0 0 +#else +# define CACHE_MODE_P0 CYGARC_REG_CCR_WT +#endif + +#ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK +# define CACHE_MODE_P1 CYGARC_REG_CCR_CB +#else +# define CACHE_MODE_P1 0 +#endif + +externC void +cyg_var_enable_caches(void) +{ + // Initialize cache. + HAL_UCACHE_INVALIDATE_ALL(); + + // Set cache modes + HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1); + +#ifdef CYGHWR_HAL_SH_CACHE_ENABLE + // Enable cache. + HAL_UCACHE_ENABLE(); +#endif +} + +//--------------------------------------------------------------------------- +void +hal_variant_init(void) +{ +} + +//--------------------------------------------------------------------------- +// Interrupt function support + +#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +externC cyg_uint8 cyg_hal_ILVL_table[]; +#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \ + /* Update the ILVL table, so it is easy for the interrupt entry */ \ + /* code to find out the level of a given interrupt source. */ \ + cyg_hal_ILVL_table[(_vector_)] = (_level_) +#else +#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) +#endif + +void +hal_interrupt_set_level(int vector, int level) +{ + cyg_uint16 iprX; + + CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level"); + CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) + && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); + + HAL_UPDATE_ILVL_TABLE(vector, level); + + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Cannot change levels */ + break; + + /* IPRA */ + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU0_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU1_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2: + case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU2_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_RTC_ATI: + case CYGNUM_HAL_INTERRUPT_RTC_PRI: + case CYGNUM_HAL_INTERRUPT_RTC_CUI: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_RTC_MASK; + iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + + /* IPRB */ + case CYGNUM_HAL_INTERRUPT_SCI_ERI: + case CYGNUM_HAL_INTERRUPT_SCI_RXI: + case CYGNUM_HAL_INTERRUPT_SCI_TXI: + case CYGNUM_HAL_INTERRUPT_SCI_TEI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_SCI_MASK; + iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + case CYGNUM_HAL_INTERRUPT_WDT_ITI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_WDT_MASK; + iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + case CYGNUM_HAL_INTERRUPT_REF_RCMI: + case CYGNUM_HAL_INTERRUPT_REF_ROVI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_REF_MASK; + iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + +#if (CYGARC_SH_MOD_INTC >= 2) +#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL + /* IPRC */ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK; + iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK; + iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK; + iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK; + iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; +#endif + /* IPRD */ + case CYGNUM_HAL_INTERRUPT_PINT_PINT07: + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); + iprX &= ~CYGARC_REG_IPRD_PINT07_MASK; + iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); + break; + case CYGNUM_HAL_INTERRUPT_PINT_PINT8F: + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); + iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK; + iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); + iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK; + iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); + iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK; + iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); + break; + + /* IPRE */ + case CYGNUM_HAL_INTERRUPT_DMAC_DEI0: + case CYGNUM_HAL_INTERRUPT_DMAC_DEI1: + case CYGNUM_HAL_INTERRUPT_DMAC_DEI2: + case CYGNUM_HAL_INTERRUPT_DMAC_DEI3: + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); + iprX &= ~CYGARC_REG_IPRE_DMAC_MASK; + iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); + break; + case CYGNUM_HAL_INTERRUPT_IRDA_ERI1: + case CYGNUM_HAL_INTERRUPT_IRDA_RXI1: + case CYGNUM_HAL_INTERRUPT_IRDA_BRI1: + case CYGNUM_HAL_INTERRUPT_IRDA_TXI1: + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); + iprX &= ~CYGARC_REG_IPRE_IRDA_MASK; + iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); + break; + case CYGNUM_HAL_INTERRUPT_SCIF_ERI2: + case CYGNUM_HAL_INTERRUPT_SCIF_RXI2: + case CYGNUM_HAL_INTERRUPT_SCIF_BRI2: + case CYGNUM_HAL_INTERRUPT_SCIF_TXI2: + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); + iprX &= ~CYGARC_REG_IPRE_SCIF_MASK; + iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); + break; + case CYGNUM_HAL_INTERRUPT_ADC_ADI: + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); + iprX &= ~CYGARC_REG_IPRE_ADC_MASK; + iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); + break; +#endif // (CYGARC_SH_MOD_INTC >= 2) + +#if (CYGARC_SH_MOD_INTC >= 3) + /* IPRF */ + case CYGNUM_HAL_INTERRUPT_LCDC_LCDI: + HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); + iprX &= ~CYGARC_REG_IPRF_LCDI_MASK; + iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); + break; + case CYGNUM_HAL_INTERRUPT_PCC_PCC0: + HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); + iprX &= ~CYGARC_REG_IPRF_PCC0_MASK; + iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); + break; + case CYGNUM_HAL_INTERRUPT_PCC_PCC1: + HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); + iprX &= ~CYGARC_REG_IPRF_PCC1_MASK; + iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); + break; +#endif // (CYGARC_SH_MOD_INTC >= 3) + + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + /* Do nothing for these reserved vectors. */ + break; + + default: + CYG_FAIL("Unknown interrupt vector"); + break; + } +} + +void +hal_interrupt_mask(int vector) +{ + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Can only be masked by fiddling Imask in SR. */ + break; + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: + HAL_INTERRUPT_SET_LEVEL((vector), 0); + break; + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + /* Do nothing for these reserved vectors. */ + break; + default: + CYG_FAIL("Unknown interrupt vector"); + break; + } +} + +void +hal_interrupt_unmask(int vector) +{ + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Can only be unmasked by fiddling Imask in SR. */ + break; + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: + HAL_INTERRUPT_SET_LEVEL((vector), 1); + break; + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + /* Do nothing for these reserved vectors. */ + break; + default: + CYG_FAIL("Unknown interrupt vector"); + break; + } +} + +void +hal_interrupt_acknowledge(int vector) +{ +#if (CYGARC_SH_MOD_INTC >= 2) + if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 + && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { + + cyg_uint8 irr0; + + HAL_READ_UINT8(CYGARC_REG_IRR0, irr0); + switch ( vector ) { +#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: + irr0 &= ~CYGARC_REG_IRR0_IRQ0; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: + irr0 &= ~CYGARC_REG_IRR0_IRQ1; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: + irr0 &= ~CYGARC_REG_IRR0_IRQ2; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: + irr0 &= ~CYGARC_REG_IRR0_IRQ3; + break; +#endif + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: + irr0 &= ~CYGARC_REG_IRR0_IRQ4; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: + irr0 &= ~CYGARC_REG_IRR0_IRQ5; + break; + default: + CYG_FAIL("Unhandled interrupt vector"); + } + HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0); + } +#endif +} + +// Note: The PINTs can be masked and configured individually, even +// though there are only two vectors. Maybe add some fake vectors just +// for masking/configuring? +void +hal_interrupt_configure(int vector, int level, int up) +{ +#if (CYGARC_SH_MOD_INTC >= 2) + if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 + && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { + + cyg_uint16 icr1, ss, mask; + ss = 0; + mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL; + if (up) ss |= CYGARC_REG_ICR1_SENSE_UP; + if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL; + CYG_ASSERT(!(up && level), "Cannot trigger on high level!"); + + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; + break; +#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; + break; + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: + ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; + mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; + break; +#endif + default: + CYG_FAIL("Unhandled interrupt vector"); + } + + HAL_READ_UINT16(CYGARC_REG_ICR1, icr1); + icr1 &= ~mask; + icr1 |= ss; + HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1); + } +#endif +} + +//--------------------------------------------------------------------------- +// End of hal_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/src/var_mk_defs.c @@ -0,0 +1,84 @@ +//========================================================================== +// +// var_mk_defs.c +// +// HAL (variant) "make defs" program +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Date: 2000-02-21 +// Purpose: SH architecture dependent definition generator +// Description: This file contains code that can be compiled by the target +// compiler and used to generate machine specific definitions +// suitable for use in assembly code. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_cache.h> // HAL header +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +# include <cyg/kernel/instrmnt.h> +#endif + +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * This technique was first used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + */ + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + // Caching details + DEFINE(CYGARC_REG_CACHE_ADDRESS_FLUSH, CYGARC_REG_CACHE_ADDRESS_FLUSH); + DEFINE(CYGARC_REG_CACHE_ADDRESS_BASE,CYGARC_REG_CACHE_ADDRESS_BASE); + DEFINE(CYGARC_REG_CACHE_ADDRESS_TOP,CYGARC_REG_CACHE_ADDRESS_TOP); + DEFINE(CYGARC_REG_CACHE_ADDRESS_STEP,CYGARC_REG_CACHE_ADDRESS_STEP); + DEFINE(HAL_UCACHE_SIZE, HAL_UCACHE_SIZE); + DEFINE(HAL_UCACHE_WAYS, HAL_UCACHE_WAYS); + DEFINE(HAL_UCACHE_LINE_SIZE, HAL_UCACHE_LINE_SIZE); + +} + +//-------------------------------------------------------------------------- +// EOF var_mk_defs.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh3/current/src/variant.S @@ -0,0 +1,192 @@ +##========================================================================== +## +## variant.S +## +## SH3 variant assembly code +## +##========================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors: jskov +## Date: 2000-10-30 +## Purpose: SH3 misc assembly code +######DESCRIPTIONEND#### +## +##========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sh.h> + +#include <cyg/hal/sh_regs.h> +#include <cyg/hal/sh3_offsets.inc> + +#--------------------------------------------------------------------------- +# Cache operations +# These need to be written in assembly to ensure they do not rely on data +# in cachable space (i.e., code must use registers exclusively, not the stack). + +# This macro must be used at the top of each cache function. It ensures +# that the code gets executed from a shadow region where caching is disabled +# (0xA0000000). + .macro GOTO_NONCACHED_SHADOW + mova 10f,r0 + mov.l $MASK,r1 + and r1,r0 + mov.l $BASE,r1 + or r1,r0 + jmp @r0 + nop + .align 2 +10: + .endm + + .globl _cyg_hal_cache_enable +_cyg_hal_cache_enable: + GOTO_NONCACHED_SHADOW + mov #CYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_CE,r2 + mov.l r2,@r1 + nop + rts + nop + + .globl _cyg_hal_cache_disable +_cyg_hal_cache_disable: + GOTO_NONCACHED_SHADOW + mov #CYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_CE,r2 + not r2,r2 + and r2,r0 + mov.l r0,@r1 + nop + rts + nop + + .globl _cyg_hal_cache_invalidate_all +_cyg_hal_cache_invalidate_all: + GOTO_NONCACHED_SHADOW + mov #CYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_CF,r2 + or r2,r0 + mov.l r0,@r1 + nop ! Nothing in the docs suggest we need + nop ! nops here, but without them, the + nop ! CPU crashes. + rts + nop + + .globl _cyg_hal_cache_sync +_cyg_hal_cache_sync: + GOTO_NONCACHED_SHADOW + mov.l $CYGARC_REG_CACHE_ADDRESS_FLUSH,r0 + mov.l $CYGARC_REG_CACHE_ADDRESS_BASE,r1 + mov.l $CYGARC_REG_CACHE_ADDRESS_TOP,r2 + mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3 +1: cmp/hi r1,r2 + bf 2f + mov.l r0,@r1 + bra 1b + add r3,r1 ! delay slot! +2: nop + rts + nop + + ! r4 = base + ! r5 = size + .globl _cyg_hal_cache_sync_region +_cyg_hal_cache_sync_region: + GOTO_NONCACHED_SHADOW + mov.l 10f,r0 + and r4,r0 ! array index + mov.l 11f,r1 + add r0,r1 ! base (aligned, A set) + + ! make sure top is aligned to start of _next_ cache line + mov r1,r0 + add r5,r0 ! top (non-aligned) + add #2*HAL_UCACHE_LINE_SIZE-1,r0 + mov.l 13f,r2 + and r0,r2 + + mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3 + mov.l 12f,r5 +1: cmp/hi r1,r2 + bf 3f + mov r4,r0 ! create address tag + and r5,r0 + mov.l r0,@r1 ! store tag in array, causing (sync+)invalidate + ! if the tag matches any of the lines + add r3,r4 ! inc address tag + bra 1b + add r3,r1 ! inc array index, delay slot! +3: nop + rts + nop + + .align 2 +10: .long ((HAL_UCACHE_SIZE/HAL_UCACHE_WAYS)-1)&~0xf ! mask +11: .long CYGARC_REG_CACHE_ADDRESS_BASE|CYGARC_REG_CACHE_ADDRESS_ADDRESS +12: .long CYGARC_REG_CACHE_ADDRESS_TAG_Mask +13: .long ~(HAL_UCACHE_LINE_SIZE-1) + + .globl _cyg_hal_cache_write_mode +_cyg_hal_cache_write_mode: + GOTO_NONCACHED_SHADOW + # Mode argument in r4. + # Read current state and mask out the two caching mode bits + mov #CYGARC_REG_CCR,r1 + mov.l @r1,r3 + mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2 + and r2,r4 + not r2,r2 + and r2,r3 + # Or in the new settings and restore to CCR + or r4,r3 + mov.l r3,@r1 + nop + rts + nop + + .align 2 +$CYGARC_REG_CACHE_ADDRESS_FLUSH: + .long CYGARC_REG_CACHE_ADDRESS_FLUSH +$CYGARC_REG_CACHE_ADDRESS_BASE: + .long CYGARC_REG_CACHE_ADDRESS_BASE +$CYGARC_REG_CACHE_ADDRESS_TOP: + .long CYGARC_REG_CACHE_ADDRESS_TOP +$CYGARC_REG_CACHE_ADDRESS_STEP: + .long CYGARC_REG_CACHE_ADDRESS_STEP + + +$MASK: + .long 0x1fffffff ! mask off top 3 bits +$BASE: + .long 0xa0000000 ! base of non-cachable memory
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/ChangeLog @@ -0,0 +1,39 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * Many changes to bring the variant HAL up to date with the later + SH arch HAL changes. Rewrote caching code to handle the split + cache. + +2000-08-16 Haruki Kashiwaya <kashiwaya@redhat.com> + + * Set up directory structure. + +2000-04-18 Ryozaburo Suzuki <ryos@atom-tc.or.jp> + + * Contributed sources for the CqREEK/SH-4 platform. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl @@ -0,0 +1,145 @@ +# ==================================================================== +# +# hal_sh_sh4.cdl +# +# SH4 architectural HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: jskov +# Contributors: +# Date: 1999-10-29 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SH_SH4 { + display "SH4 architecture" + parent CYGPKG_HAL_SH + hardware + include_dir cyg/hal + define_header hal_sh_sh4.h + description " + The SH4 (SuperH 4) architecture HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + + compile sh4_scif.c var_misc.c variant.S + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_sh_sh4.h>" + } + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + <PREFIX>/include/cyg/hal/sh4_offsets.inc : <PACKAGE>/src/var_mk_defs.c + $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $< + fgrep .equ var_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 sh4_offsets.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm sh4_offsets.tmp var_mk_defs.tmp + } + + # CPU variant supported + cdl_component CYGPKG_HAL_SH_7750 { + display "SH 7750 microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7750 + description " + The SH4 7750 microprocessor. This is an embedded part that in + addition to the SH4 processor core has built in peripherals + such as memory controllers, DMA controllers, serial ports and + timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7750.h>" + } + } + + cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS { + display "SH on-chip generic clock controls" + description " + The various clocks used by the system are controlled by + these options, some of which are derived from platform + settings." + flavor none + no_define + + cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 { + display "TMU counter 0 prescaling" + description " + The peripheral clock is driving the counter used for + the real-time clock, prescaled by this factor." + flavor data + legal_values { 4 16 64 256 } + default_value 4 + } + + cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT { + display "The clock output from PLL1" + no_define + flavor data + calculated { CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_1 } + } + + cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED { + display "Processor clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_IFC } + description " + The core (CPU, cache and MMU) speed is computed from + the input clock speed and the IFC divider setting." + } + + cdl_option CYGHWR_HAL_SH_BOARD_SPEED { + display "Platform bus clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_BFC } + description " + The bus speed is computed from + the input clock speed and the BFC divider setting." + } + + cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED { + display "Processor on-chip peripheral clock speed (MHz)" + flavor data + calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_PFC } + description " + The peripheral speed is computed from the input clock + speed and the PFC divider setting." + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_7750.h @@ -0,0 +1,96 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7750.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:Haruki Kashiwaya +// Date: 2000-08-09 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_CPG 1 +#define CYGARC_SH_MOD_SCIF 1 + + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +//============================================================================= +// Icache +// Cache dimenions +#define CYGARC_SH_MOD_CAC_I_SIZE 8192 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_I_LINE_SIZE 32 // Size of a cache line +#define CYGARC_SH_MOD_CAC_I_WAYS 1 // Associativity of the cache + +// Cache addressing information +// entry: bits 12 - 5 +#define CYGARC_SH_MOD_ICAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_ICAC_ADDRESS_TOP 0xf0002000 +#define CYGARC_SH_MOD_ICAC_ADDRESS_STEP 0x00000020 +// V : bit 0 +// Writing zero to V forces an invalidate of the line +#define CYGARC_SH_MOD_ICAC_ADDRESS_FLUSH 0x00000000 + + +//============================================================================= +// Dcache +// Cache dimenions +#define CYGARC_SH_MOD_CAC_D_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_D_LINE_SIZE 32 // Size of a cache line +#define CYGARC_SH_MOD_CAC_D_WAYS 1 // Associativity of the cache + +// Cache addressing information +// entry: bits 13 - 5 +#define CYGARC_SH_MOD_DCAC_ADDRESS_BASE 0xf4000000 +#define CYGARC_SH_MOD_DCAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_DCAC_ADDRESS_STEP 0x00000020 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_DCAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_77xx_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_bsc.h @@ -0,0 +1,176 @@ +//============================================================================= +// +// mod_regs_bsc.h +// +// BSC (bus state controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Register definitions +#define CYGARC_REG_BCR1 0xFF800000 +#define CYGARC_REG_BCR2 0xFF800004 +#define CYGARC_REG_WCR1 0xFF800008 +#define CYGARC_REG_WCR2 0xFF80000C +#define CYGARC_REG_WCR3 0xFF800010 +#define CYGARC_REG_MCR 0xFF800014 +#define CYGARC_REG_PCR 0xFF800018 +#define CYGARC_REG_RTCSR 0xFF80001C +#define CYGARC_REG_RTCNT 0xFF800020 +#define CYGARC_REG_RTCOR 0xFF800024 +#define CYGARC_REG_RFCR 0xFF800028 + +#define CYGARC_REG_SDMR2 0xFF90008c + +#define CYGARC_REG_SDMR_AREA2_BASE 0xff900000 +#define CYGARC_REG_SDMR_AREA3_BASE 0xff940000 + +#define CYGARC_REG_BCR1_DRAMTP2 0x0010 +#define CYGARC_REG_BCR1_DRAMTP1 0x0008 +#define CYGARC_REG_BCR1_DRAMTP0 0x0004 + +// Bus widths for areas +#define CYGARC_REG_BCR2_A6_8 0x1000 +#define CYGARC_REG_BCR2_A6_16 0x2000 +#define CYGARC_REG_BCR2_A6_32 0x3000 +#define CYGARC_REG_BCR2_A5_8 0x0400 +#define CYGARC_REG_BCR2_A5_16 0x0800 +#define CYGARC_REG_BCR2_A5_32 0x0c00 +#define CYGARC_REG_BCR2_A4_8 0x0100 +#define CYGARC_REG_BCR2_A4_16 0x0200 +#define CYGARC_REG_BCR2_A4_32 0x0300 +#define CYGARC_REG_BCR2_A3_8 0x0040 +#define CYGARC_REG_BCR2_A3_16 0x0080 +#define CYGARC_REG_BCR2_A3_32 0x00c0 +#define CYGARC_REG_BCR2_A2_8 0x0010 +#define CYGARC_REG_BCR2_A2_16 0x0020 +#define CYGARC_REG_BCR2_A2_32 0x0030 + +// Memory type selection and other IO behavior controls +#define CYGARC_REG_BCR1_PULA 0x8000 // Pin A25 to A0 Pull-Up +#define CYGARC_REG_BCR1_PULD 0x4000 // Pin D31 to D0 Pull-Up +#define CYGARC_REG_BCR1_HIZMEM 0x2000 // Hi-Z memory control +#define CYGARC_REG_BCR1_HIZCNT 0x1000 // High-Z Control +#define CYGARC_REG_BCR1_ENDIAN 0x0800 // Endian Flag +#define CYGARC_REG_BCR1_A0_BST_MASK 0x0600 // Area 0 Burst ROM Control +#define CYGARC_REG_BCR1_A0_BST_4 0x0200 +#define CYGARC_REG_BCR1_A0_BST_8 0x0400 +#define CYGARC_REG_BCR1_A0_BST_16 0x0600 +#define CYGARC_REG_BCR1_A5_BST_MASK 0x0180 // Area 5 Burst ROM Control +#define CYGARC_REG_BCR1_A5_BST_4 0x0080 +#define CYGARC_REG_BCR1_A5_BST_8 0x0100 +#define CYGARC_REG_BCR1_A5_BST_16 0x0180 +#define CYGARC_REG_BCR1_A6_BST_MASK 0x0060 // Area 6 Burst ROM Control +#define CYGARC_REG_BCR1_A6_BST_4 0x0020 +#define CYGARC_REG_BCR1_A6_BST_8 0x0040 +#define CYGARC_REG_BCR1_A6_BST_16 0x0060 +#define CYGARC_REG_BCR1_DRAMTP_MASK 0x001c // Area 2, Area 3 Memory Type +#define CYGARC_REG_BCR1_A5PCM 0x0002 // Area 5 Bus Type +#define CYGARC_REG_BCR1_A6PCM 0x0001 // Area 6 Bus Type + +// Intercycle wait states +#define CYGARC_REG_WCR1_WAITSEL 0x8000 // WAIT Sampling Timing Select +#define CYGARC_REG_WCR1_A6I_MASK 0x3000 // Intercycle Idle Specification +#define CYGARC_REG_WCR1_A6I_SHIFT 12 +#define CYGARC_REG_WCR1_A5I_MASK 0x0c00 +#define CYGARC_REG_WCR1_A5I_SHIFT 10 +#define CYGARC_REG_WCR1_A4I_MASK 0x0300 +#define CYGARC_REG_WCR1_A4I_SHIFT 8 +#define CYGARC_REG_WCR1_A3I_MASK 0x00c0 +#define CYGARC_REG_WCR1_A3I_SHIFT 6 +#define CYGARC_REG_WCR1_A2I_MASK 0x0030 +#define CYGARC_REG_WCR1_A2I_SHIFT 4 +#define CYGARC_REG_WCR1_A0I_MASK 0x0003 +#define CYGARC_REG_WCR1_A0I_SHIFT 0 + +#define CYGARC_REG_WCR1_0WS 0 +#define CYGARC_REG_WCR1_1WS 1 +#define CYGARC_REG_WCR1_2WS 2 +#define CYGARC_REG_WCR1_3WS 3 + + +// Wait states +#define CYGARC_REG_WCR2_A6_MASK 0xe000 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A6_SHIFT 13 +#define CYGARC_REG_WCR2_A5_MASK 0x1c00 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A5_SHIFT 10 +#define CYGARC_REG_WCR2_A4_MASK 0x0380 // Wait states +#define CYGARC_REG_WCR2_A4_SHIFT 7 +#define CYGARC_REG_WCR2_A3_MASK 0x0060 // Wait states / CAS latency +#define CYGARC_REG_WCR2_A3_SHIFT 5 +#define CYGARC_REG_WCR2_A2_MASK 0x0018 // Wait states / CAS latency +#define CYGARC_REG_WCR2_A2_SHIFT 3 +#define CYGARC_REG_WCR2_A0_MASK 0x0007 // Wait states + burst pitch +#define CYGARC_REG_WCR2_A0_SHIFT 0 + +#define CYGARC_REG_WCR2_0WS 0 +#define CYGARC_REG_WCR2_1WS 1 +#define CYGARC_REG_WCR2_2WS 2 +#define CYGARC_REG_WCR2_3WS 3 +#define CYGARC_REG_WCR2_4WS 4 +#define CYGARC_REG_WCR2_6WS 5 +#define CYGARC_REG_WCR2_8WS 6 +#define CYGARC_REG_WCR2_10WS 7 + + + +//----------------------------------------------------------------------------- +// Calculate constants needed to drive the proper SDRAM refresh rate. Argument +// is delay between required refresh events in microseconds (us). Should be +// available off the SDRAM spec sheet. +// These should be a part of a fully CDLicized memory controller setup. +#define CYGARC_RTCSR_PRESCALE(_r_) \ +(((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \ + ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096) + +// These two macros provide the static values we need to stuff into the +// registers. +#define CYGARC_RTCSR_CKSx(_r_) \ + (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \ + ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \ + ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \ + ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \ + (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \ + (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 ) + +#define CYGARC_RTCSR_N(_r_) \ + (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_cac.h @@ -0,0 +1,61 @@ +//============================================================================= +// +// mod_regs_cac.h +// +// CAC (cache) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Besides the below, cache sizes are defined in the CPU variant module +// headers (mod_77xx.h). + +//-------------------------------------------------------------------------- +// Cache registers +#define CYGARC_REG_CCR 0xFF00001C + +#define CYGARC_REG_CCR_IIX 0x00008000 // IC index enable +#define CYGARC_REG_CCR_ICI 0x00000800 // IC invalidation +#define CYGARC_REG_CCR_ICE 0x00000100 // IC Enable +#define CYGARC_REG_CCR_OIX 0x00000080 // OC index enable +#define CYGARC_REG_CCR_ORA 0x00000020 // OC RAM enable +#define CYGARC_REG_CCR_OCI 0x00000008 // OC Invalidation +#define CYGARC_REG_CCR_CB 0x00000004 // Copy-Back enable +#define CYGARC_REG_CCR_WT 0x00000002 // Write Through enable +#define CYGARC_REG_CCR_OCE 0x00000001 // OC Enable + +#define CYGARC_REG_CCR_CE 0x00000101 // IC, OC Enable +#define CYGARC_REG_CCR_CF 0x00000808 // IC, OC Invalidation +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_cpg.h @@ -0,0 +1,154 @@ +//============================================================================= +// +// mod_regs_cpg.h +// +// CPG (clock pulse generator) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Oscillator control registers +#define CYGARC_REG_FRQCR 0xFFC00000 +#define CYGARC_REG_STBCR 0xFFC00004 +#define CYGARC_REG_WTCNT 0xFFC00008 // read 8bit, write 16bit +#define CYGARC_REG_WTCSR 0xFFC0000C // read 8bit, write 16bit +#define CYGARC_REG_STBCR2 0xFFC00010 + +#define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write + +#define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write +#define CYGARC_REG_WTCSR_TME 0x80 // timer enable +#define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0) +#define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0) +#define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow +#define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow +#define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2 +#define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1 +#define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0 +#define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask +// This is the period (in us) between watchdog reset and overflow. +// Note: We use max timeout delay for now. +#define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay + +#define CYGARC_REG_WTCSR_PERIOD ((1000000000/(CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/4096))*256) + +// Translate various CDL clock configurations to register equivalents +// for the various CPG versions +#if (CYGARC_SH_MOD_CPG == 1) // ---------------------------- V1 + +// PLL1 +#if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400 +#else +# error "Unsupported PLL1 setting" +#endif + +// PLL2 +#if (CYGHWR_HAL_SH_OOC_PLL_2 == 0) +# define CYGARC_REG_FRQCR_INIT_PLL2 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_2 == 1) +# define CYGARC_REG_FRQCR_INIT_PLL2 0x0200 +#else +# error "Unsupported PLL2 setting" +#endif + +// Divider IFC +#if (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0040 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 3) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0080 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x00c0 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 6) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0100 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 8) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0140 +#else +# error "Unsupported Divider IFC setting" +#endif + +// Divider BFC +#if (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 1) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0008 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 3) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0010 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0018 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 6) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0020 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 8) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0028 +#else +# error "Unsupported Divider BFC setting" +#endif + +// Divider PFC +#if (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 2) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0000 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 3) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0001 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 4) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0002 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 6) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0003 +#elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 8) +# define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0004 +#else +# error "Unsupported Divider PFC setting" +#endif + + +// CKOEN +#ifdef CYGHWR_HAL_SH_OOC_CKIO +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0800 +#else +# define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000 +#endif + +#else + +# error "Unsupported CPG version" + +#endif + +// Init value +#define CYGARC_REG_FRQCR_INIT (CYGARC_REG_FRQCR_INIT_PLL1|CYGARC_REG_FRQCR_INIT_PLL2|CYGARC_REG_FRQCR_INIT_DIVIDER_IFC|CYGARC_REG_FRQCR_INIT_DIVIDER_BFC|CYGARC_REG_FRQCR_INIT_DIVIDER_PFC|CYGARC_REG_FRQCR_INIT_CKOEN)
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_dma.h @@ -0,0 +1,111 @@ +//============================================================================= +// +// mod_regs_dma.h +// +// DMA (direct memory access) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// DMA Controller registers + +#define CYGARC_REG_SAR0 0xa4000020 +#define CYGARC_REG_DAR0 0xa4000024 +#define CYGARC_REG_DMATCR0 0xa4000028 +#define CYGARC_REG_CHCR0 0xa400002c +#define CYGARC_REG_SAR1 0xa4000030 +#define CYGARC_REG_DAR1 0xa4000034 +#define CYGARC_REG_DMATCR1 0xa4000038 +#define CYGARC_REG_CHCR1 0xa400003c +#define CYGARC_REG_SAR2 0xa4000040 +#define CYGARC_REG_DAR2 0xa4000044 +#define CYGARC_REG_DMATCR2 0xa4000048 +#define CYGARC_REG_CHCR2 0xa400004c +#define CYGARC_REG_SAR3 0xa4000050 +#define CYGARC_REG_DAR3 0xa4000054 +#define CYGARC_REG_DMATCR3 0xa4000058 +#define CYGARC_REG_CHCR3 0xa400005c +#define CYGARC_REG_DMAOR 0xa4000060 + +// Offsets from base register +#define CYGARC_REG_SAR 0x00 +#define CYGARC_REG_DAR 0x04 +#define CYGARC_REG_DMATCR 0x08 +#define CYGARC_REG_CHCR 0x0c + + +// DMA Channel Control Register. If there's a digit suffix to CHCR the flag +// is only valid in the listed channels. +#define CYGARC_REG_CHCR3_DI 0x00100000 // direct/indirect selection +#define CYGARC_REG_CHCR2_RO 0x00080000 // source address reload +#define CYGARC_REG_CHCR01_RL 0x00040000 // request check level +#define CYGARC_REG_CHCR01_AM 0x00020000 // acknowledge mode +#define CYGARC_REG_CHCR01_AL 0x00010000 // acknowledge level +#define CYGARC_REG_CHCR_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR_DM0 0x00004000 +#define CYGARC_REG_CHCR_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR_SM0 0x00001000 +#define CYGARC_REG_CHCR_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR_RS2 0x00000400 +#define CYGARC_REG_CHCR_RS1 0x00000200 +#define CYGARC_REG_CHCR_RS0 0x00000100 +#define CYGARC_REG_CHCR01_DS 0x00000040 // DREQ select +#define CYGARC_REG_CHCR_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR_TS0 0x00000008 +#define CYGARC_REG_CHCR_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR_DE 0x00000001 // DMAC enable + +// Resource select options +#define CYGARC_REG_CHCR_RS_EXT_DUAL 0x00000000 +#define CYGARC_REG_CHCR_RS_EXT_EX_DAC 0x00000100 +#define CYGARC_REG_CHCR_RS_EXT_DAC_EX 0x00000300 +#define CYGARC_REG_CHCR_RS_AUTO 0x00000400 +#define CYGARC_REG_CHCR_RS_IRDA_TX 0x00000a00 +#define CYGARC_REG_CHCR_RS_IRDA_RX 0x00000b00 +#define CYGARC_REG_CHCR_RS_SCIF_TX 0x00000c00 +#define CYGARC_REG_CHCR_RS_SCIF_RX 0x00000d00 +#define CYGARC_REG_CHCR_RS_AD 0x00000e00 +#define CYGARC_REG_CHCR_RS_CMT 0x00000f00 + + +// DMA Operation Register +#define CYGARC_REG_DMAOR_PR1 0x0200 // priority level +#define CYGARC_REG_DMAOR_PR0 0x0100 +#define CYGARC_REG_DMAOR_AE 0x0004 // address error flag +#define CYGARC_REG_DMAOR_NMIF 0x0002 // NMI flag +#define CYGARC_REG_DMAOR_DME 0x0001 // DMA master enable
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_intc.h @@ -0,0 +1,76 @@ +//============================================================================= +// +// mod_regs_intc.h +// +// INTC (interrupt controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Interrupt registers, module type 1 +#define CYGARC_REG_EXCEVT 0xFF000024 +#define CYGARC_REG_INTEVT 0xFF000028 + +#define CYGARC_REG_ICR 0xFFD00000 +#define CYGARC_REG_IPRA 0xFFD00004 +#define CYGARC_REG_IPRB 0xFFD00008 +#define CYGARC_REG_IPRC 0xFFD0000C + +#define CYGARC_REG_IPRA_TMU0_MASK 0xf000 +#define CYGARC_REG_IPRA_TMU0_PRI1 0x1000 +#define CYGARC_REG_IPRA_TMU1_MASK 0x0f00 +#define CYGARC_REG_IPRA_TMU1_PRI1 0x0100 +#define CYGARC_REG_IPRA_TMU2_MASK 0x00f0 +#define CYGARC_REG_IPRA_TMU2_PRI1 0x0010 +#define CYGARC_REG_IPRA_RTC_MASK 0x000f +#define CYGARC_REG_IPRA_RTC_PRI1 0x0001 + +#define CYGARC_REG_IPRB_WDT_MASK 0xf000 +#define CYGARC_REG_IPRB_WDT_PRI1 0x1000 +#define CYGARC_REG_IPRB_REF_MASK 0x0f00 +#define CYGARC_REG_IPRB_REF_PRI1 0x0100 +#define CYGARC_REG_IPRB_SCI_MASK 0x00f0 +#define CYGARC_REG_IPRB_SCI_PRI1 0x0010 + +#define CYGARC_REG_IPRC_GPIO_MASK 0xF000 +#define CYGARC_REG_IPRC_GPIO_PRI1 0x1000 +#define CYGARC_REG_IPRC_DMAC_MASK 0x0F00 +#define CYGARC_REG_IPRC_DMAC_PRI1 0x0100 +#define CYGARC_REG_IPRC_SCIF_MASK 0x00F0 +#define CYGARC_REG_IPRC_SCIF_PRI1 0x0010 +#define CYGARC_REG_IPRC_HUDI_MASK 0x000F +#define CYGARC_REG_IPRC_HUDI_PRI1 0x0001 +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_mmu.h @@ -0,0 +1,52 @@ +//============================================================================= +// +// mod_regs_mmu.h +// +// MMU Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// MMU control registers +#define CYGARC_REG_MMUCR 0xFF000010 + +#define CYGARC_REG_MMUCR_LRUI_MASK 0xFC000000 +#define CYGARC_REG_MMUCR_URB_MASK 0x00FC0000 +#define CYGARC_REG_MMUCR_URC_MASK 0x0000FC00 +#define CYGARC_REG_MMUCR_SQMD 0x00000200 +#define CYGARC_REG_MMUCR_SV 0x00000100 +#define CYGARC_REG_MMUCR_TI 0x00000004 +#define CYGARC_REG_MMUCR_AT 0x00000001
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_pfc.h @@ -0,0 +1,100 @@ +//============================================================================= +// +// mod_regs_pfc.h +// +// PFC (pin function controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#define CYGARC_REG_PACR 0xa4000100 // port A control +#define CYGARC_REG_PBCR 0xa4000102 // port B control +#define CYGARC_REG_PCCR 0xa4000104 // port C control +#define CYGARC_REG_PDCR 0xa4000106 // port D control +#define CYGARC_REG_PECR 0xa4000108 // port E control +#define CYGARC_REG_PFCR 0xa400010a // port F control +#define CYGARC_REG_PGCR 0xa400010c // port G control +#define CYGARC_REG_PHCR 0xa400010e // port H control +#define CYGARC_REG_PJCR 0xa4000110 // port J control +#define CYGARC_REG_PKCR 0xa4000112 // port K control +#define CYGARC_REG_PLCR 0xa4000114 // port L control +#define CYGARC_REG_SCPCR 0xa4000116 // SC port control + +#define CYGARC_REG_PADR 0xa4000120 // port A data +#define CYGARC_REG_PBDR 0xa4000122 // port B data +#define CYGARC_REG_PCDR 0xa4000124 // port C data +#define CYGARC_REG_PDDR 0xa4000126 // port D data +#define CYGARC_REG_PEDR 0xa4000128 // port E data +#define CYGARC_REG_PFDR 0xa400012a // port F data +#define CYGARC_REG_PGDR 0xa400012c // port G data +#define CYGARC_REG_PHDR 0xa400012e // port H data +#define CYGARC_REG_PJDR 0xa4000130 // port J data +#define CYGARC_REG_PKDR 0xa4000132 // port K data +#define CYGARC_REG_PLDR 0xa4000134 // port L data +#define CYGARC_REG_SCPDR 0xa4000136 // SC port data + + +// Port C +#define CYGARC_REG_PCCR_PC7_MASK 0xc000 +#define CYGARC_REG_PCCR_PC7_shift 14 +#define CYGARC_REG_PCCR_PC6_MASK 0x3000 +#define CYGARC_REG_PCCR_PC6_shift 12 +#define CYGARC_REG_PCCR_PC5_MASK 0x0c00 +#define CYGARC_REG_PCCR_PC5_shift 10 +#define CYGARC_REG_PCCR_PC4_MASK 0x0300 +#define CYGARC_REG_PCCR_PC4_shift 8 +#define CYGARC_REG_PCCR_PC3_MASK 0x00c0 +#define CYGARC_REG_PCCR_PC3_shift 6 +#define CYGARC_REG_PCCR_PC2_MASK 0x0030 +#define CYGARC_REG_PCCR_PC2_shift 4 +#define CYGARC_REG_PCCR_PC1_MASK 0x000c +#define CYGARC_REG_PCCR_PC1_shift 2 +#define CYGARC_REG_PCCR_PC0_MASK 0x0003 +#define CYGARC_REG_PCCR_PC0_shift 0 + +#define CYGARC_REG_PCCR_MD_OTHER 0x0 +#define CYGARC_REG_PCCR_MD_OUT 0x1 +#define CYGARC_REG_PCCR_MD_IN_ON 0x2 +#define CYGARC_REG_PCCR_MD_IN_OFF 0x3 + +#define CYGARC_REG_PCDR_PC7DT 0x80 +#define CYGARC_REG_PCDR_PC6DT 0x40 +#define CYGARC_REG_PCDR_PC5DT 0x20 +#define CYGARC_REG_PCDR_PC4DT 0x10 +#define CYGARC_REG_PCDR_PC3DT 0x08 +#define CYGARC_REG_PCDR_PC2DT 0x04 +#define CYGARC_REG_PCDR_PC1DT 0x02 +#define CYGARC_REG_PCDR_PC0DT 0x01 +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_rtc.h @@ -0,0 +1,77 @@ +//============================================================================= +// +// mod_regs_rtc.h +// +// RTC (real time clock) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// RealTime Clock + +#define CYGARC_REG_RC64CNT 0xfffffec0 +#define CYGARC_REG_RSECCNT 0xfffffec2 +#define CYGARC_REG_RMINCNT 0xfffffec4 +#define CYGARC_REG_RHRCNT 0xfffffec6 +#define CYGARC_REG_RWKCNT 0xfffffec8 +#define CYGARC_REG_RDAYCNT 0xfffffeca +#define CYGARC_REG_RMONCNT 0xfffffecc +#define CYGARC_REG_RYRCNT 0xfffffece +#define CYGARC_REG_RSECAR 0xfffffed0 +#define CYGARC_REG_RMINAR 0xfffffed2 +#define CYGARC_REG_RHRAR 0xfffffed4 +#define CYGARC_REG_RWKAR 0xfffffed6 +#define CYGARC_REG_RDAYAR 0xfffffed8 +#define CYGARC_REG_RMONAR 0xfffffeda +#define CYGARC_REG_RCR1 0xfffffedc +#define CYGARC_REG_RCR2 0xfffffede + + +#define CYGARC_REG_RCR1_CF 0x80 // carry flag +#define CYGARC_REG_RCR1_CIE 0x10 // carry interrupt enable +#define CYGARC_REG_RCR1_AIE 0x08 // alarm interrupt enable +#define CYGARC_REG_RCR1_AF 0x01 // alarm flag + +#define CYGARC_REG_RCR2_PEF 0x80 // periodic interrupt flag +#define CYGARC_REG_RCR2_PES2 0x40 // periodic interrupt setting +#define CYGARC_REG_RCR2_PES1 0x20 +#define CYGARC_REG_RCR2_PES0 0x10 +#define CYGARC_REG_RCR2_RTCEN 0x08 // RTC enable +#define CYGARC_REG_RCR2_ADJ 0x04 // second adjustment +#define CYGARC_REG_RCR2_RESET 0x02 // reset +#define CYGARC_REG_RCR2_START 0x01 // start + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_ser.h @@ -0,0 +1,277 @@ +//============================================================================= +// +// mod_regs_ser.h +// +// SCI, SCIF, and IRDA (serial) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// Note: All three serial module definitions kept in the same file +// since they share some of the information. +//####DESCRIPTIONEND#### +// +//============================================================================= + +//++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//-------------------------------------------------------------------------- +// Serial registers. All 8 bit registers. +#define CYGARC_REG_SCSMR1 0xFFE00000 // serial mode register +#define CYGARC_REG_SCBRR1 0xFFE00004 // bit rate register +#define CYGARC_REG_SCSCR1 0xFFE00008 // serial control register +#define CYGARC_REG_SCTDR1 0xFFE0000C // transmit data register +#define CYGARC_REG_SCSSR1 0xFFE00010 // serial status register +#define CYGARC_REG_SCRDR1 0xFFE00014 // receive data register +#define CYGARC_REG_SCRCMR1 0xFFE00018 +#define CYGARC_REG_SCSPTR1 0xFFE0001C // serial port register + +// Serial Mode Register +#define CYGARC_REG_SCSMR1_CA 0x80 // communication mode +#define CYGARC_REG_SCSMR1_CHR 0x40 // character length (7 if set) +#define CYGARC_REG_SCSMR1_PE 0x20 // parity enable +#define CYGARC_REG_SCSMR1_OE 0x10 // parity mode +#define CYGARC_REG_SCSMR1_STOP 0x08 // stop bit length +#define CYGARC_REG_SCSMR1_MP 0x04 // multiprocessor mode +#define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR1_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR1_MPIE 0x08 // multiprocessor interrupt enable +#define CYGARC_REG_SCSCR1_TEIE 0x04 // transmit-end interrupt enable +#define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR1_TDRE 0x80 // transmit data register empty +#define CYGARC_REG_SCSSR1_RDRF 0x40 // receive data register full +#define CYGARC_REG_SCSSR1_ORER 0x20 // overrun error +#define CYGARC_REG_SCSSR1_FER 0x10 // framing error +#define CYGARC_REG_SCSSR1_PER 0x08 // parity error +#define CYGARC_REG_SCSSR1_TEND 0x04 // transmit end +#define CYGARC_REG_SCSSR1_MPB 0x02 // multiprocessor bit +#define CYGARC_REG_SCSSR1_MPBT 0x01 // multiprocessor bit transfer + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR1_CLEARMASK 0xf8 + + +// Baud rate values calculation, depending on peripheral clock (Pf) +// n is CKS setting (0-3) +// N = (Pf/(64*2^(2n-1)*B))-1 +// With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get +// N = (Pf/(32*_CKS*B))-1 +// +// The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS +// setting for the given baud rate and peripheral clock. +// +// The error of the CKS+count value can be computed by: +// E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100 +// +#define CYGARC_SCBRR_PRESCALE(_b_) \ +((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \ + (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \ + (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64) + +// These two macros provide the static values we need to stuff into the +// registers. +#define CYGARC_SCBRR_CKSx(_b_) \ + ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \ + (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \ + (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3) +#define CYGARC_SCBRR_N(_b_) \ + (((_b_) < 4800) ? 0 : \ + ((_b_) > 115200) ? 0 : \ + ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1)) + + +//++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_IRDA + +//-------------------------------------------------------------------------- +// IrDA (infrared data association). Can also act as regular serial w FIFO + +#define CYGARC_REG_SCSMR1 0xFFE00000 // serial mode register +#define CYGARC_REG_SCBRR1 0xFFE00004 // bit rate register +#define CYGARC_REG_SCSCR1 0xFFE00008 // serial control register +#define CYGARC_REG_SCTDR1 0xFFE0000C // transmit data register +#define CYGARC_REG_SCSSR1 0xFFE00010 // serial status register +#define CYGARC_REG_SCRDR1 0xFFE00014 // receive data register +#define CYGARC_REG_SCRCMR1 0xFFE00018 +#define CYGARC_REG_SCSPTR1 0xFFE0001C // serial port register + +// Serial Mode Register +#define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode +#define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width +#define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?) +#define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR1_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR1_PER_shift 12 +#define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR1_FER_shift 8 +#define CYGARC_REG_SCSSR1_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR1_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR1_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR1_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test + + +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR1_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR1_TCOUNT_shift 8 + +#endif // CYGARC_SH_MOD_IRDA + +//++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_SCIF + +//-------------------------------------------------------------------------- +// Serial w FIFO registers + +#define CYGARC_REG_SCSMR2 0xffe80000 // Serial mode +#define CYGARC_REG_SCBRR2 0xffe80004 // Bit rate +#define CYGARC_REG_SCSCR2 0xffe80008 // Serial control +#define CYGARC_REG_SCFTDR2 0xffe8000c // Transmit FIFO data +#define CYGARC_REG_SCFSR2 0xffe80010 // Serial status +#define CYGARC_REG_SCFRDR2 0xffe80014 // Receive data FIFO +#define CYGARC_REG_SCFCR2 0xffe80018 // FIFO control register +#define CYGARC_REG_SCFDR2 0xffe8001c // FIFO data count set +#define CYGARC_REG_SCSPTR2 0xffe80020 // serial port register +#define CYGARC_REG_SCLSR2 0xffe80024 // line status register + +// Serial Mode Register +#define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set) +#define CYGARC_REG_SCSMR2_PE 0x20 // parity enable +#define CYGARC_REG_SCSMR2_OE 0x10 // parity mode +#define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length +#define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR2_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR2_PER_shift 12 +#define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR2_FER_shift 8 +#define CYGARC_REG_SCSSR2_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR2_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR2_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR2_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test + + +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR2_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR2_TCOUNT_shift 8 + +#endif // CYGARC_SH_MOD_SCIF
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_tmu.h @@ -0,0 +1,79 @@ +//============================================================================= +// +// mod_regs_tmu.h +// +// TMU (timer unit) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// TMU registers +#define CYGARC_REG_TOCR 0xFFD80000 // 8 bit +#define CYGARC_REG_TSTR 0xFFD80004 // 8 bit +#define CYGARC_REG_TCOR0 0xFFD80008 // 32 bit +#define CYGARC_REG_TCNT0 0xFFD8000C // 32 bit +#define CYGARC_REG_TCR0 0xFFD80010 // 16 bit +#define CYGARC_REG_TCOR1 0xFFD80014 // 32 bit +#define CYGARC_REG_TCNT1 0xFFD80018 // 32 bit +#define CYGARC_REG_TCR1 0xFFD8001C // 16 bit +#define CYGARC_REG_TCOR2 0xFFD80020 // 32 bit +#define CYGARC_REG_TCNT2 0xFFD80024 // 32 bit +#define CYGARC_REG_TCR2 0xFFD80028 // 16 bit +#define CYGARC_REG_TCPR2 0xFFD8002C // 32 bit + +// TSTR +#define CYGARC_REG_TSTR_STR0 0x0001 +#define CYGARC_REG_TSTR_STR1 0x0002 +#define CYGARC_REG_TSTR_STR2 0x0004 + +// TCR0/1/2 +#define CYGARC_REG_TCR_TPSC0 0x0001 +#define CYGARC_REG_TCR_TPSC1 0x0002 +#define CYGARC_REG_TCR_TPSC2 0x0004 +#define CYGARC_REG_TCR_CKEG0 0x0008 +#define CYGARC_REG_TCR_CKEG1 0x0010 +#define CYGARC_REG_TCR_UNIE 0x0020 +#define CYGARC_REG_TCR_UNF 0x0100 + +#define CYGARC_REG_TCR_TPSC_4 (0) +#define CYGARC_REG_TCR_TPSC_16 (CYGARC_REG_TCR_TPSC0) +#define CYGARC_REG_TCR_TPSC_64 (CYGARC_REG_TCR_TPSC1) +#define CYGARC_REG_TCR_TPSC_256 (CYGARC_REG_TCR_TPSC0|CYGARC_REG_TCR_TPSC1) + +// TCR2 additional bits +#define CYGARC_REG_TCR_ICPE0 0x0040 +#define CYGARC_REG_TCR_ICPE1 0x0080 +#define CYGARC_REG_TCR_ICPF 0x0200
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_ubc.h @@ -0,0 +1,75 @@ +//============================================================================= +// +// mod_regs_ubc.h +// +// UBC (user break controller) Module register definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-10-30 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// User Break Control +#define CYGARC_REG_BARA 0xFF200000 // 32 bit +#define CYGARC_REG_BAMRA 0xFF200004 // 8 bit +#define CYGARC_REG_BBRA 0xFF200008 // 16 bit + +#define CYGARC_REG_BARB 0xFF20000C // 32 bit +#define CYGARC_REG_BAMRB 0xFF200010 // 8 bit + +#define CYGARC_REG_BBRB 0xFF200014 // 16 bit +#define CYGARC_REG_BDRB 0xFF200018 // 32 bit +#define CYGARC_REG_BDMRB 0xFF20001C // 32 bit + +#define CYGARC_REG_BRCR 0xFF200020 // 16 bit + + +#define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A +#define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B +#define CYGARC_REG_BRCR_PCBA 0x0400 // post execute channel A +#define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B +#define CYGARC_REG_BRCR_PCBB 0x0040 // post execute channel B +#define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select +#define CYGARC_REG_BRCR_UBDE 0x0001 // User Break Debug Enable + + +#define CYGARC_REG_BBRA_DFETCH 0x0020 // Break on DFETCH +#define CYGARC_REG_BBRA_IFETCH 0x0010 // Break on IFETCH +#define CYGARC_REG_BBRA_WRITE 0x0008 // Break on WRITE +#define CYGARC_REG_BBRA_READ 0x0004 // Break on READ +#define CYGARC_REG_BBRA_SIZE_QUAD 0x0040 // Break on quad word access +#define CYGARC_REG_BBRA_SIZE_LONG 0x0003 // Break on long word access +#define CYGARC_REG_BBRA_SIZE_WORD 0x0002 // Break on word access +#define CYGARC_REG_BBRA_SIZE_BYTE 0x0001 // Break on byte access +#define CYGARC_REG_BBRA_SIZE_ANY 0x0000 // Break on any size
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/sh4_scif.h @@ -0,0 +1,86 @@ +//============================================================================= +// +// sh4_scif.h +// +// Simple driver for the sh4 Serial Communication Interface with FIFO +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:Haruki Kashiwaya +// Date: 2000-08-09 +// Description: Simple driver for the SH Serial Communication Interface +// The driver can be used for the SCIF modules. +// Clients of this file can configure the behavior with: +// CYGNUM_SCIF_PORTS: number of SCI ports +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH4_SCIF_PORTS + +//-------------------------------------------------------------------------- +// SCIF register offsets +#define _REG_SCSMR 0x00 +#define _REG_SCBRR 0x04 +#define _REG_SCSCR 0x08 +#define _REG_SCFTDR 0x0c +#define _REG_SCFSR 0x10 +#define _REG_SCFRDR 0x14 +#define _REG_SCFCR 0x18 +#define _REG_SCFDR 0x1c +#define _REG_SCSPTR 0x20 +#define _REG_SCLSR 0x24 + +//-------------------------------------------------------------------------- + +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +//-------------------------------------------------------------------------- + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +// This one should only be used by old-stub compatibility code! +externC void cyg_hal_plf_scif_init_channel(const channel_data_t* chan); +#endif + +externC cyg_uint8 cyg_hal_plf_scif_getc(void* __ch_data); +externC void cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c); +void cyg_hal_plf_scif_init(int scif_index, int comm_index, + int rcv_vect, cyg_uint8* base); + + +#endif // CYGNUM_HAL_SH_SH4_SCIF_PORTS +//----------------------------------------------------------------------------- +// end of sh4_scif.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/var_cache.h @@ -0,0 +1,234 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg, jskov +// Date: 2000-04-02 +// Purpose: Variant cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations on the SH variant CPUs. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/sh_regs.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +#ifndef HAL_DCACHE_DEFINED + +#define HAL_DCACHE_SIZE CYGARC_SH_MOD_CAC_D_SIZE +#define HAL_DCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_D_LINE_SIZE +#define HAL_DCACHE_WAYS CYGARC_SH_MOD_CAC_D_WAYS +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) + +// Cache addressing information +#define CYGARC_REG_DCACHE_ADDRESS_BASE CYGARC_SH_MOD_DCAC_ADDRESS_BASE +#define CYGARC_REG_DCACHE_ADDRESS_TOP CYGARC_SH_MOD_DCAC_ADDRESS_TOP +#define CYGARC_REG_DCACHE_ADDRESS_STEP CYGARC_SH_MOD_DCAC_ADDRESS_STEP +#define CYGARC_REG_DCACHE_ADDRESS_FLUSH CYGARC_SH_MOD_DCAC_ADDRESS_FLUSH + +#define HAL_DCACHE_DEFINED +#endif + +#ifndef HAL_ICACHE_DEFINED + +#define HAL_ICACHE_SIZE CYGARC_SH_MOD_CAC_I_SIZE +#define HAL_ICACHE_LINE_SIZE CYGARC_SH_MOD_CAC_I_LINE_SIZE +#define HAL_ICACHE_WAYS CYGARC_SH_MOD_CAC_I_WAYS +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +// Cache addressing information +#define CYGARC_REG_ICACHE_ADDRESS_BASE CYGARC_SH_MOD_ICAC_ADDRESS_BASE +#define CYGARC_REG_ICACHE_ADDRESS_TOP CYGARC_SH_MOD_ICAC_ADDRESS_TOP +#define CYGARC_REG_ICACHE_ADDRESS_STEP CYGARC_SH_MOD_ICAC_ADDRESS_STEP +#define CYGARC_REG_ICACHE_ADDRESS_FLUSH CYGARC_SH_MOD_ICAC_ADDRESS_FLUSH + +#define HAL_ICACHE_DEFINED +#endif + + +//----------------------------------------------------------------------------- +// Global control of cache + +// This is all handled in assembly (see variant.S) due to a requirement about +// not fiddling the cache from cachable memory. + +externC void cyg_hal_dcache_enable(void); +externC void cyg_hal_dcache_disable(void); +externC void cyg_hal_dcache_invalidate_all(void); +externC void cyg_hal_dcache_sync(void); +externC void cyg_hal_dcache_sync_region(cyg_haladdress base, + cyg_haladdrword len); +externC void cyg_hal_dcache_write_mode(int mode); + +// Enable the cache +#define HAL_DCACHE_ENABLE() cyg_hal_dcache_enable() + +// Disable the cache +#define HAL_DCACHE_DISABLE() cyg_hal_dcache_disable() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() cyg_hal_dcache_invalidate_all() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() cyg_hal_dcache_sync() + +// Query the state of the cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \ + (_state_) &= ~CYGARC_REG_CCR_OCE; \ + CYG_MACRO_END + +// Set the cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Set the cache write mode +#define HAL_ICACHE_WRITE_MODE( _mode_ ) \ + CYG_MACRO_START \ + cyg_uint32 _m_; \ + if (HAL_DCACHE_WRITETHRU_MODE == _mode_) \ + _m_ = CYGARC_REG_CCR_WT; \ + else \ + _m_ = CYGARC_REG_CCR_CB; \ + cyg_hal_cache_write_mode(_m_); \ + CYG_MACRO_END + +#define HAL_DCACHE_WRITETHRU_MODE 0 +#define HAL_DCACHE_WRITEBACK_MODE 1 + +// This macro allows the client to specify separate modes for the two +// regions. +#define HAL_DCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_dcache_write_mode(_mode_) + +// Load the contents of the given address range into the cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + cyg_hal_dcache_sync_region((cyg_haladdress)_base_, (cyg_haladdrword)_size_) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +externC void cyg_hal_icache_enable(void); +externC void cyg_hal_icache_disable(void); +externC void cyg_hal_icache_invalidate_all(void); + +// Enable the cache +#define HAL_ICACHE_ENABLE() cyg_hal_dcache_enable() + +// Disable the cache +#define HAL_ICACHE_DISABLE() cyg_hal_dcache_disable() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() cyg_hal_icache_invalidate_all() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() + +// Query the state of the cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \ + (_state_) &= ~CYGARC_REG_CCR_ICE; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. + +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/var_intr.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// var_intr.h +// +// SH4 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, +// Date: 1999-04-24 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_CPU_MODULES_H // INTC module selection + +// More include statements below. First part of this file must be +// usable for both assembly and C files, so only use defines here. +#include <cyg/hal/plf_intr.h> + +//-------------------------------------------------------------------------- +// Additional SH4 exception vectors. +// These are identified with event values 0x800 and 0x820, so we need to +// extend the decode macros accordingly. Performance wise it's not an +// issue - these are exceptions, not interrupts. No critical fast path. +#define CYGNUM_HAL_VECTOR_FPU_EXCEPTION 9 // FPU exception +#define CYGNUM_HAL_VECTOR_TLB_MUTI_HIT 10 // mutible TLB hit +#define CYGNUM_HAL_VECTOR_FPU_DISABLE 17 +#define CYGNUM_HAL_VECTOR_SLOT_FPU_DISABLE 18 + +#define CYG_VECTOR_IS_INTERRUPT(v) \ + ((CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v)) && ((v) < CYGNUM_HAL_VECTOR_FPU_DISABLE)) + +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SLOT_FPU_DISABLE + +#define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VECTOR_POWERON+1) + +#define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32 +#define CYGNUM_HAL_INTERRUPT_RESERVED_5E0 33 +#define CYGNUM_HAL_INTERRUPT_HUDI 34 +#define CYGNUM_HAL_INTERRUPT_GPIO 35 +#define CYGNUM_HAL_INTERRUPT_DMAC_DMTE0 36 +#define CYGNUM_HAL_INTERRUPT_DMAC_DMTE1 37 +#define CYGNUM_HAL_INTERRUPT_DMAC_DMTE2 38 +#define CYGNUM_HAL_INTERRUPT_DMAC_DMTE3 39 +#define CYGNUM_HAL_INTERRUPT_DMAC_DMAE 40 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41 +#define CYGNUM_HAL_INTERRUPT_SCIF_ERI 42 +#define CYGNUM_HAL_INTERRUPT_SCIF_RXI 43 +#define CYGNUM_HAL_INTERRUPT_SCIF_BRI 44 +#define CYGNUM_HAL_INTERRUPT_SCIF_TXI 45 + +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_SCIF_TXI + +// Exception vectors. These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception() + +// These are in addition to the exceptions defined by the architecture. + +#define CYGNUM_HAL_EXCEPTION_FPU_EXCEPTION 9 // fpu exception +#define CYGNUM_HAL_EXCEPTION_TLB_MULTI_HIT 10 // TLB multi hit exception +#define CYGNUM_HAL_EXCEPTION_FPU_DISABLE 17 +#define CYGNUM_HAL_EXCEPTION_SLOT_FPU_DISABLE 18 + +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_SLOT_FPU_DISABLE + + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +// End of hal_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/var_regs.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H +//============================================================================= +// +// var_regs.h +// +// SH4 CPU definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:Ryozaburo Suzuki +// Date: 2000-04-18 +// Purpose: Define CPU memory mapped registers etc. +// Usage: Included via the acrhitecture register header: +// #include <cyg/hal/sh_regs.h> +// Notes: +// This file describes registers for on-core modules found in all +// the SH4 CPUs supported by the HAL. For each CPU is defined a +// module specification file (mod_<CPU model number>.h) which lists +// modules (and their version if applicable) included in that +// particular CPU model. Note that the versioning is ad hoc; +// it doesn't reflect Hitachi internal versioning in any way. +// +//####DESCRIPTIONEND#### +// + +// Find out which modules are supported by the chosen CPU +#include <pkgconf/system.h> +#include CYGBLD_HAL_CPU_MODULES_H + +//========================================================================== +// CPU Definitions +//========================================================================== + +//-------------------------------------------------------------------------- +// Status register +#define CYGARC_REG_SR_MD 0x40000000 +#define CYGARC_REG_SR_RB 0x20000000 +#define CYGARC_REG_SR_BL 0x10000000 +#define CYGARC_REG_SR_M 0x00000200 +#define CYGARC_REG_SR_Q 0x00000100 +#define CYGARC_REG_SR_IMASK 0x000000f0 +#define CYGARC_REG_SR_I3 0x00000080 +#define CYGARC_REG_SR_I2 0x00000040 +#define CYGARC_REG_SR_I1 0x00000020 +#define CYGARC_REG_SR_I0 0x00000010 +#define CYGARC_REG_SR_S 0x00000002 +#define CYGARC_REG_SR_T 0x00000001 +#define CYGARC_REG_SR_FD 0x00008000 + +//========================================================================== +// Module Definitions +//========================================================================== + +#include <cyg/hal/mod_regs_bsc.h> +#include <cyg/hal/mod_regs_cac.h> +#include <cyg/hal/mod_regs_cpg.h> +#include <cyg/hal/mod_regs_intc.h> +#include <cyg/hal/mod_regs_mmu.h> +#include <cyg/hal/mod_regs_rtc.h> +#include <cyg/hal/mod_regs_ser.h> +#include <cyg/hal/mod_regs_tmu.h> +#include <cyg/hal/mod_regs_ubc.h> + +#endif // CYGONCE_HAL_VAR_REGS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/variant.inc @@ -0,0 +1,167 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## SH4 variant assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-10-30 +## Purpose: SH4 variant definitions and init code +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the SH3 CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/sh_regs.h> + +#=========================================================================== +# SR initialization value +# zero all bits except: +# MD = Processor operation mode field (privileged mode) +# I0-3 = Mask out all interrupts but NMI. +# +# When saving or restoring the state of an exception or interrupt, the bit +# CYGARC_REG_SR_RB is also set, switching the register bank. When this bit +# is set, interrupts must be disabled. +# +# Note: We could also use the BL bit to prevent interrupts, but that would +# also prevent the use of breakpoints. + +#define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK) +#define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) + +##----------------------------------------------------------------------------- +## Hardware init macros +#ifndef CYGPKG_HAL_SH_POST_RESET_INIT + .macro hal_post_reset_init + # Initialize CPU + mov.l $nCYG_SR,r1 ! Put CPU in a well-known state + ldc r1,sr + mov #0,r0 + mov.l $nCYGARC_REG_CCR,r1 ! Disable cache + mov.l r0,@r1 + mov.l $nCYGARC_REG_MMUCR,r1 ! Disable MMU + mov.l r0,@r1 + mov.l $nCYGARC_REG_BBRA,r1 ! Disable UBC Channel A + mov.w r0,@r1 + mov.l $nCYGARC_REG_BBRB,r1 ! Disable UBC Channel B + mov.w r0,@r1 + mov.l $nCYGARC_REG_BRCR,r1 ! Reset UBC common register + mov.w r0,@r1 + mov.l $CYGARC_REG_TSTR,r1 ! Disable timers + mov.b r0,@r1 + mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRB,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRC,r1 + mov.w r0,@r1 + mov.w $nCYG_WTCSR,r0 ! Clear watchdog + mov.l $nCYGARC_REG_WTCSR,r1 + mov.w r0,@r1 + + # Initialize VBR if necessary +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + mov.l $__reset,r1 ! Set VBR + ldc r1,vbr +#endif + bra 1f + nop + +$nCYG_WTCSR: + .word 0xa500 ! clear all CSR bits + + .align 2 +$nCYG_SR: + .long CYG_SR +$nCYGARC_REG_CCR: + .long CYGARC_REG_CCR +$nCYGARC_REG_MMUCR: + .long CYGARC_REG_MMUCR +$nCYGARC_REG_BBRA: + .long CYGARC_REG_BBRA +$nCYGARC_REG_BBRB: + .long CYGARC_REG_BBRB +$nCYGARC_REG_BRCR: + .long CYGARC_REG_BRCR +$CYGARC_REG_TSTR: + .long CYGARC_REG_TSTR +$CYGARC_REG_IPRA: + .long CYGARC_REG_IPRA +$CYGARC_REG_IPRB: + .long CYGARC_REG_IPRB +$CYGARC_REG_IPRC: + .long CYGARC_REG_IPRC +$nCYGARC_REG_WTCSR: + .long CYGARC_REG_WTCSR +$__reset: + .long __reset + +1: + .endm +#define CYGPKG_HAL_SH_POST_RESET_INIT +#endif + +##----------------------------------------------------------------------------- +## Interrupt decode macros + .macro hal_intc_decode tmp,inum + mov.l $nCYGARC_REG_INTEVT,\tmp + mov.l @\tmp,\inum + mov #-5,\tmp ! divide cause by 0x20 + shld \tmp,\inum + add #-14,\inum ! adjust so NMI becomes 0 + .endm + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + .macro hal_intc_translate inum,vnum + mov #0,\vnum ! Just vector zero is supported + .endm +#else + .macro hal_intc_translate inum,vnum + mov \inum,\vnum ! Vector == interrupt number + shll2 \vnum ! get from vector number to ISR index + .endm +#endif + +#------------------------------------------------------------------------------ +#endif // CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/src/sh4_scif.c @@ -0,0 +1,333 @@ +//============================================================================= +// +// sh4_scif.c +// +// Simple driver for the SH4 Serial Communication Interface with FIFO +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:Haruki Kashiwaya +// Date: 2000-08-09 +// Description: Simple driver for the SH Serial Communication Interface +// The driver can be used for the SCIF modules. +// Clients of this file can configure the behavior with: +// CYGNUM_SCIF_PORTS: number of SCI ports +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGNUM_HAL_SH_SH4_SCIF_PORTS + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP +#include <cyg/hal/hal_if.h> // Calling-if API +#include <cyg/hal/sh_regs.h> // serial register definitions +#include <cyg/hal/sh_stub.h> // target_register_t + +#include <cyg/hal/sh4_scif.h> // our header + +//-------------------------------------------------------------------------- + +void +cyg_hal_plf_scif_init_channel(const channel_data_t* chan) +{ + cyg_uint8* base = chan->base; + cyg_uint16 tmp; + cyg_uint16 sr; + + // Disable everything. + HAL_WRITE_UINT16(base+_REG_SCSCR, 0); + + // Reset FIFO. + HAL_WRITE_UINT16(base+_REG_SCFCR, + CYGARC_REG_SCFCR2_TFRST|CYGARC_REG_SCFCR2_RFRST); + + // 8-1-no parity. + HAL_WRITE_UINT16(base+_REG_SCSMR, 0); + + // Set speed to 38400 + HAL_READ_UINT16(base+_REG_SCSMR, tmp); + tmp &= ~CYGARC_REG_SCSMR2_CKSx_MASK; + tmp |= CYGARC_SCBRR_CKSx(38400); + HAL_WRITE_UINT16(base+_REG_SCSMR, tmp); + HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(38400)); + + // Let things settle: Here we should should wait the equivalent of + // one bit interval, i.e. 1/38400 second, but until we have + // something like the Linux delay loop, it's hard to do reliably. So + // just move on and hope for the best (this is unlikely to cause + // problems since the CPU has just come out of reset anyway). + + // Clear status register (read back first). + HAL_READ_UINT16(base+_REG_SCFSR, sr); + HAL_WRITE_UINT16(base+_REG_SCFSR, 0); + + // Bring FIFO out of reset and set to trigger on every char in + // FIFO (or C-c input would not be processed). + HAL_WRITE_UINT16(base+_REG_SCFCR, + CYGARC_REG_SCFCR2_RTRG_1|CYGARC_REG_SCFCR2_TTRG_1); + + // Leave Tx/Rx interrupts disabled, but enable Tx/Rx + HAL_WRITE_UINT16(base+_REG_SCSCR, + CYGARC_REG_SCSCR2_TE|CYGARC_REG_SCSCR2_RE); +} + +static cyg_bool +cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint16 fdr, sr; + + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) == 0) + return false; + + HAL_READ_UINT8(base+_REG_SCFRDR, *ch); + + // Clear FIFO full flag (read before clearing) + HAL_READ_UINT16(base+_REG_SCFSR, sr); + HAL_WRITE_UINT16(base+_REG_SCFSR, + CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF); + + return true; +} + +cyg_uint8 +cyg_hal_plf_scif_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_scif_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +void +cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint16 fdr, sr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + } while (((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) >> CYGARC_REG_SCFDR2_TCOUNT_shift) == 16); + + HAL_WRITE_UINT8(base+_REG_SCFTDR, c); + + // Clear FIFO-empty/transmit end flags (read back SR first) + HAL_READ_UINT16(base+_REG_SCFSR, sr); + HAL_WRITE_UINT16(base+_REG_SCFSR, CYGARC_REG_SCSSR2_CLEARMASK + & ~(CYGARC_REG_SCSSR2_TDFE | CYGARC_REG_SCSSR2_TEND )); + + // Hang around until the character has been safely sent. + do { + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + } while ((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) != 0); + + CYGARC_HAL_RESTORE_GP(); +} + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \ + || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES) + +static channel_data_t channels[CYGNUM_HAL_SH_SH4_SCIF_PORTS]; + +static void +cyg_hal_plf_scif_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_scif_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_scif_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_scif_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_scif_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_scif_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 scr; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT16(chan->base+_REG_SCSCR, scr); + scr |= CYGARC_REG_SCSCR2_RIE; + HAL_WRITE_UINT16(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT16(chan->base+_REG_SCSCR, scr); + scr &= ~CYGARC_REG_SCSCR2_RIE; + HAL_WRITE_UINT16(chan->base+_REG_SCSCR, scr); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + cyg_uint8 c; + cyg_uint16 fdr, sr; + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + int res = 0; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + HAL_READ_UINT16(base+_REG_SCFDR, fdr); + if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) != 0) { + HAL_READ_UINT8(base+_REG_SCFRDR, c); + + // Clear buffer full flag (read back first). + HAL_READ_UINT16(base+_REG_SCFSR, sr); + HAL_WRITE_UINT16(base+_REG_SCFSR, + CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +void +cyg_hal_plf_scif_init(int scif_index, int comm_index, + int rcv_vect, cyg_uint8* base) +{ + channel_data_t* chan = &channels[scif_index]; + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Initialize channel table + chan->base = base; + chan->isr_vector = rcv_vect; + chan->msec_timeout = 1000; + + // Disable interrupts. + HAL_INTERRUPT_MASK(chan->isr_vector); + + // Init channel + cyg_hal_plf_scif_init_channel(chan); + + // Setup procs in the vector table + + // Initialize channel procs + CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES + +#endif // CYGNUM_HAL_SH_SH4_SCIF_PORTS + +//----------------------------------------------------------------------------- +// end of sh4_scif.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/src/var_misc.c @@ -0,0 +1,272 @@ +//========================================================================== +// +// var_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, jlarmour, nickg +// Date: 1999-04-03 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> // diag_printf + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_cache.h> // HAL cache +#include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions + +//--------------------------------------------------------------------------- +// Initial cache enabling + +#ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK +# define CACHE_MODE_P0 0 +#else +# define CACHE_MODE_P0 CYGARC_REG_CCR_WT +#endif + +#ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK +# define CACHE_MODE_P1 CYGARC_REG_CCR_CB +#else +# define CACHE_MODE_P1 0 +#endif + +externC void +cyg_var_enable_caches(void) +{ + // Initialize cache. + HAL_DCACHE_INVALIDATE_ALL(); + HAL_ICACHE_INVALIDATE_ALL(); + + // Set cache modes + HAL_DCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1); + +#ifdef CYGHWR_HAL_SH_CACHE_ENABLE + // Enable cache. + HAL_ICACHE_ENABLE(); + HAL_DCACHE_ENABLE(); +#endif +} + +//--------------------------------------------------------------------------- +void +hal_variant_init(void) +{ +} + +//--------------------------------------------------------------------------- + +#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +externC cyg_uint8 cyg_hal_ILVL_table[]; +#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \ + /* Update the ILVL table, so it is easy for the interrupt entry */ \ + /* code to find out the level of a given interrupt source. */ \ + cyg_hal_ILVL_table[(_vector_)] = (_level_) +#else +#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) +#endif + +void +hal_interrupt_set_level(int vector, int level) +{ + cyg_uint16 iprX; + + CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level"); + CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) + && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); + + HAL_UPDATE_ILVL_TABLE(vector, level); + + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Cannot change levels */ + break; + + /* IPRA */ + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU0_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU1_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2: + case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_TMU2_MASK; + iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + case CYGNUM_HAL_INTERRUPT_RTC_ATI: + case CYGNUM_HAL_INTERRUPT_RTC_PRI: + case CYGNUM_HAL_INTERRUPT_RTC_CUI: + HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); + iprX &= ~CYGARC_REG_IPRA_RTC_MASK; + iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); + break; + + /* IPRB */ + case CYGNUM_HAL_INTERRUPT_SCI_ERI: + case CYGNUM_HAL_INTERRUPT_SCI_RXI: + case CYGNUM_HAL_INTERRUPT_SCI_TXI: + case CYGNUM_HAL_INTERRUPT_SCI_TEI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_SCI_MASK; + iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + case CYGNUM_HAL_INTERRUPT_WDT_ITI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_WDT_MASK; + iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + case CYGNUM_HAL_INTERRUPT_REF_RCMI: + case CYGNUM_HAL_INTERRUPT_REF_ROVI: + HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); + iprX &= ~CYGARC_REG_IPRB_REF_MASK; + iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); + break; + + /* IPRC */ + case CYGNUM_HAL_INTERRUPT_HUDI: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_HUDI_MASK; + iprX |= (level)*CYGARC_REG_IPRC_HUDI_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_GPIO: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_GPIO_MASK; + iprX |= (level)*CYGARC_REG_IPRC_GPIO_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_DMAC_DMTE0: + case CYGNUM_HAL_INTERRUPT_DMAC_DMTE1: + case CYGNUM_HAL_INTERRUPT_DMAC_DMTE2: + case CYGNUM_HAL_INTERRUPT_DMAC_DMTE3: + case CYGNUM_HAL_INTERRUPT_DMAC_DMAE: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_DMAC_MASK; + iprX |= (level)*CYGARC_REG_IPRC_DMAC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_SCIF_ERI: + case CYGNUM_HAL_INTERRUPT_SCIF_RXI: + case CYGNUM_HAL_INTERRUPT_SCIF_BRI: + case CYGNUM_HAL_INTERRUPT_SCIF_TXI: + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); + iprX &= ~CYGARC_REG_IPRC_DMAC_MASK; + iprX |= (level)*CYGARC_REG_IPRC_DMAC_PRI1; + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); + break; + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_5C0: + case CYGNUM_HAL_INTERRUPT_RESERVED_5E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_6E0: + /* Do nothing for these reserved vectors. */ + break; + } +} + +void +hal_interrupt_mask(int vector) +{ + switch( vector ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Can only be masked by fiddling Imask in SR. */ + break; + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: + HAL_INTERRUPT_SET_LEVEL((vector), 0); + break; + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + /* Do nothing for these reserved vectors. */ + break; + default: + CYG_FAIL("Unknown interrupt vector"); + break; + } +} + +void +hal_interrupt_unmask(int vector) +{ + switch( (vector) ) { + case CYGNUM_HAL_INTERRUPT_NMI: + /* fall through */ + case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: + /* Can only be unmasked by fiddling Imask in SR. */ + break; + case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: + HAL_INTERRUPT_SET_LEVEL((vector), 1); + break; + case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: + case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: + /* Do nothing for these reserved vectors. */ + break; + default: + CYG_FAIL("Unknown interrupt vector"); + break; + } +} + + +void +hal_interrupt_acknowledge(int vector) +{ +} + +void +hal_interrupt_configure(int vector, int level, int up) +{ +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/src/var_mk_defs.c @@ -0,0 +1,91 @@ +//========================================================================== +// +// var_mk_defs.c +// +// HAL (variant) "make defs" program +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Date: 2000-02-21 +// Purpose: SH architecture dependent definition generator +// Description: This file contains code that can be compiled by the target +// compiler and used to generate machine specific definitions +// suitable for use in assembly code. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_cache.h> // HAL header +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +# include <cyg/kernel/instrmnt.h> +#endif + +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * This technique was first used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + */ + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + // Caching details + DEFINE(HAL_ICACHE_SIZE, HAL_ICACHE_SIZE); + DEFINE(HAL_ICACHE_WAYS, HAL_ICACHE_WAYS); + DEFINE(HAL_ICACHE_LINE_SIZE, HAL_ICACHE_LINE_SIZE); + DEFINE(CYGARC_REG_ICACHE_ADDRESS_BASE,CYGARC_REG_ICACHE_ADDRESS_BASE); + DEFINE(CYGARC_REG_ICACHE_ADDRESS_TOP,CYGARC_REG_ICACHE_ADDRESS_TOP); + DEFINE(CYGARC_REG_ICACHE_ADDRESS_STEP,CYGARC_REG_ICACHE_ADDRESS_STEP); + DEFINE(CYGARC_REG_ICACHE_ADDRESS_FLUSH, CYGARC_REG_ICACHE_ADDRESS_FLUSH); + + DEFINE(HAL_DCACHE_SIZE, HAL_DCACHE_SIZE); + DEFINE(HAL_DCACHE_WAYS, HAL_DCACHE_WAYS); + DEFINE(HAL_DCACHE_LINE_SIZE, HAL_DCACHE_LINE_SIZE); + DEFINE(CYGARC_REG_DCACHE_ADDRESS_BASE,CYGARC_REG_DCACHE_ADDRESS_BASE); + DEFINE(CYGARC_REG_DCACHE_ADDRESS_TOP,CYGARC_REG_DCACHE_ADDRESS_TOP); + DEFINE(CYGARC_REG_DCACHE_ADDRESS_STEP,CYGARC_REG_DCACHE_ADDRESS_STEP); + DEFINE(CYGARC_REG_DCACHE_ADDRESS_FLUSH, CYGARC_REG_DCACHE_ADDRESS_FLUSH); +} + +//-------------------------------------------------------------------------- +// EOF var_mk_defs.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/src/variant.S @@ -0,0 +1,213 @@ +##========================================================================== +## +## variant.S +## +## SH4 variant assembly code +## +##========================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors: jskov +## Date: 2000-10-31 +## Purpose: SH4 misc assembly code +######DESCRIPTIONEND#### +## +##========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sh.h> + +#include <cyg/hal/sh_regs.h> +#include <cyg/hal/sh4_offsets.inc> + +#--------------------------------------------------------------------------- +# Cache operations +# These need to be written in assembly to ensure they do not rely on data +# in cachable space (i.e., code must use registers exclusively, not the stack). + +# This macro must be used at the top of each cache function. It ensures +# that the code gets executed from a shadow region where caching is disabled +# (0xA0000000). + .macro GOTO_NONCACHED_SHADOW + mova 10f,r0 + mov.l $MASK,r1 + and r1,r0 + mov.l $BASE,r1 + or r1,r0 + jmp @r0 + nop + .align 2 +10: + .endm + + .globl _cyg_hal_dcache_enable +_cyg_hal_dcache_enable: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_OCE,r2 + mov.l r2,@r1 + nop + rts + nop + + .globl _cyg_hal_dcache_disable +_cyg_hal_dcache_disable: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_OCE,r2 + not r2,r2 + and r2,r0 + mov.l r0,@r1 + nop + rts + nop + + .globl _cyg_hal_dcache_invalidate_all +_cyg_hal_dcache_invalidate_all: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov #CYGARC_REG_CCR_OCI,r2 + or r2,r0 + mov.l r0,@r1 + nop ! Nothing in the docs suggest we need + nop ! nops here, but without them, the + nop ! CPU crashes. + rts + nop + + .globl _cyg_hal_dcache_sync +_cyg_hal_dcache_sync: + GOTO_NONCACHED_SHADOW + mov.l $CYGARC_REG_DCACHE_ADDRESS_FLUSH,r0 + mov.l $CYGARC_REG_DCACHE_ADDRESS_BASE,r1 + mov.l $CYGARC_REG_DCACHE_ADDRESS_TOP,r2 + mov.l $CYGARC_REG_DCACHE_ADDRESS_STEP,r3 +1: cmp/hi r1,r2 + bf 2f + mov.l r0,@r1 + bra 1b + add r3,r1 ! delay slot! +2: nop + rts + nop + + .align 2 +$CYGARC_REG_DCACHE_ADDRESS_FLUSH: + .long CYGARC_REG_DCACHE_ADDRESS_FLUSH +$CYGARC_REG_DCACHE_ADDRESS_BASE: + .long CYGARC_REG_DCACHE_ADDRESS_BASE +$CYGARC_REG_DCACHE_ADDRESS_TOP: + .long CYGARC_REG_DCACHE_ADDRESS_TOP +$CYGARC_REG_DCACHE_ADDRESS_STEP: + .long CYGARC_REG_DCACHE_ADDRESS_STEP + + + ! r4 = base + ! r5 = size + .globl _cyg_hal_dcache_sync_region +_cyg_hal_dcache_sync_region: + GOTO_NONCACHED_SHADOW +1: ocbp @r4 ! operand cache block purge + add #CYGARC_SH_MOD_DCAC_ADDRESS_STEP,r4 + add #-CYGARC_SH_MOD_DCAC_ADDRESS_STEP,r5 + cmp/pl r5 + bt 1b + rts + nop + + .globl _cyg_hal_dcache_write_mode +_cyg_hal_dcache_write_mode: + GOTO_NONCACHED_SHADOW + # Mode argument in r4. + # Read current state and mask out the two caching mode bits + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r3 + mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2 + and r2,r4 + not r2,r2 + and r2,r3 + # Or in the new settings and restore to CCR + or r4,r3 + mov.l r3,@r1 + nop + rts + nop + + + .globl _cyg_hal_icache_enable +_cyg_hal_icache_enable: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov.l $nCYGARC_REG_CCR_ICE,r2 + mov.l r2,@r1 + nop + rts + nop + + .globl _cyg_hal_icache_disable +_cyg_hal_icache_disable: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov.l $nCYGARC_REG_CCR_ICE,r2 + not r2,r2 + and r2,r0 + mov.l r0,@r1 + nop + rts + nop + + .globl _cyg_hal_icache_invalidate_all +_cyg_hal_icache_invalidate_all: + GOTO_NONCACHED_SHADOW + mov.l $nCYGARC_REG_CCR,r1 + mov.l @r1,r0 + mov.l $nCYGARC_REG_CCR_ICI,r2 + or r2,r0 + mov.l r0,@r1 + nop ! Nothing in the docs suggest we need + nop ! nops here, but without them, the + nop ! CPU crashes. + rts + nop + + .align 2 +$MASK: + .long 0x1fffffff ! mask off top 3 bits +$BASE: + .long 0xa0000000 ! base of non-cachable memory +$nCYGARC_REG_CCR: + .long CYGARC_REG_CCR +$nCYGARC_REG_CCR_ICE: + .long CYGARC_REG_CCR_ICE +$nCYGARC_REG_CCR_ICI: + .long CYGARC_REG_CCR_ICI
--- a/packages/io/fileio/current/ChangeLog +++ b/packages/io/fileio/current/ChangeLog @@ -1,3 +1,15 @@ +2000-11-01 Jonathan Larmour <jlarmour@redhat.com> + + * src/io.cxx (readwrite): Ensure we call FILEIO_RETURN_VALUE() to + get correct cleanup + (fpathconf): Ditto + (lseek): Ditto + + * src/file.cxx (open): If applicable, refer to stdin, stdout and stderr + here to ensure they are pulled in, in case selective linking would + otherwise eliminate them. This is to ensure they get allocated to + fd's 0, 1 and 2. + 2000-10-13 Nick Garnett <nickg@cygnus.co.uk> * src/io.cxx (readwrite): Merged both read() and write() functions
--- a/packages/io/fileio/current/src/file.cxx +++ b/packages/io/fileio/current/src/file.cxx @@ -47,6 +47,7 @@ #include <pkgconf/hal.h> #include <pkgconf/kernel.h> #include <pkgconf/io_fileio.h> +#include <pkgconf/isoinfra.h> #include <cyg/kernel/ktypes.h> // base kernel types #include <cyg/infra/cyg_trac.h> // tracing macros @@ -54,6 +55,7 @@ #include <string.h> // string functions #include <dirent.h> +#include <stdio.h> // stdin, stdout, stderr #include "fio.h" // Private header @@ -168,6 +170,14 @@ static Cyg_Mutex getcwd_lock CYGBLD_ATTR { FILEIO_ENTRY(); + // we want to be sure we pull in stdin/out/err, so they can be + // assigned to fds 0, 1 and 2 +#ifdef CYGINT_ISO_STDIO_STREAMS + CYG_REFERENCE_OBJECT(stdin); + CYG_REFERENCE_OBJECT(stdout); + CYG_REFERENCE_OBJECT(stderr); +#endif + CYG_CANCELLATION_POINT; int ret = 0;
--- a/packages/io/fileio/current/src/io.cxx +++ b/packages/io/fileio/current/src/io.cxx @@ -126,8 +126,7 @@ static ssize_t readwrite( int fd, void * CYG_CANCELLATION_POINT; - CYG_REPORT_RETVAL(cnt); - return cnt; + FILEIO_RETURN_VALUE(cnt); } //========================================================================== @@ -200,8 +199,7 @@ static ssize_t readwrite( int fd, void * if( ret != 0 ) FILEIO_RETURN(ret); - CYG_REPORT_RETVAL(pos); - return pos; + FILEIO_RETURN_VALUE(pos); } //========================================================================== @@ -347,8 +345,7 @@ static ssize_t readwrite( int fd, void * if( ret != 0 ) FILEIO_RETURN(ret); - CYG_REPORT_RETVAL(info.value); - return info.value; + FILEIO_RETURN_VALUE(info.value); } //==========================================================================
deleted file mode 100644 --- a/packages/io/flash/current/src/flash.h +++ /dev/null @@ -1,19 +0,0 @@ - -#define FLASH_Read_ID 0x90 -#define FLASH_Read_Query 0x98 -#define FLASH_Read_Status 0x70 -#define FLASH_Clear_Status 0x50 -#define FLASH_Status_Ready 0x80 -#define FLASH_Write 0xE8 -#define FLASH_Program 0x10 -#define FLASH_Block_Erase 0x20 -#define FLASH_Clear_Locks 0x60 -#define FLASH_Confirm 0xD0 -#define FLASH_Configure 0xB8 -#define FLASH_Configure_ReadyWait 0x00 -#define FLASH_Configure_PulseOnErase 0x01 -#define FLASH_Configure_PulseOnProgram 0x02 -#define FLASH_Configure_PulseOnBoth 0x03 -#define FLASH_Reset 0xFF - -#define FLASH_BLOCK_SIZE 0x10000
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -153,6 +153,10 @@ 2000-05-28 Gary Thomas <gthomas@redhat * tests/ser_test_protocol.inl: Rename NEC V85x drivers. +2000-05-25 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Added rules for REF4955. + 2000-05-08 Jesper Skov <jskov@redhat.com> * cdl/io_serial.cdl: active_if CYGPKG_IO
--- a/packages/isoinfra/current/ChangeLog +++ b/packages/isoinfra/current/ChangeLog @@ -1,3 +1,11 @@ +2000-11-01 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/isoinfra.cdl: Add CYGINT_ISO_STDIO_STREAMS and + CYGBLD_ISO_STDIO_STREAMS_HEADER. + Change flavor of other stdio interfaces to booldata + * include/stdio.h: Use #ifdefs not #ifs on interfaces to reflect above + Add CYGINT_ISO_STDIO_STREAMS and CYGBLD_ISO_STDIO_STREAMS_HEADER. + 2000-10-05 Nick Garnett <nickg@cygnus.co.uk> * include/sys/types.h: Changed type of pid_t to plain int. It
--- a/packages/isoinfra/current/cdl/isoinfra.cdl +++ b/packages/isoinfra/current/cdl/isoinfra.cdl @@ -149,6 +149,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_FILETYPES { display "Number of implementations of stdio file types" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_FILETYPES } } @@ -158,8 +159,23 @@ cdl_package CYGPKG_ISOINFRA { default_value 0 } + cdl_interface CYGINT_ISO_STDIO_STREAMS { + display "Stdio standard streams implementations" + flavor booldata + requires { 1 >= CYGINT_ISO_STDIO_STREAMS } + } + + cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + display "Stdio standard streams implementation header" + description "This header file must define stdin, stdout + and stderr." + flavor booldata + default_value 0 + } + cdl_interface CYGINT_ISO_STDIO_FILEOPS { display "Number of implementations of stdio file operations" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_FILEOPS } } @@ -176,6 +192,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_FILEACCESS { display "Number of implementations of stdio file access \ functionals" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_FILEACCESS } } @@ -191,6 +208,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_FORMATTED_IO { display "Number of implementations of stdio formatted I/O" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_FORMATTED_IO } } @@ -202,6 +220,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_CHAR_IO { display "Number of implementations of stdio character I/O" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_CHAR_IO } } @@ -213,6 +232,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_DIRECT_IO { display "Number of implementations of stdio direct I/O" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_DIRECT_IO } } @@ -224,6 +244,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_FILEPOS { display "Number of implementations of stdio file positioning" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_FILEPOS } } @@ -235,6 +256,7 @@ cdl_package CYGPKG_ISOINFRA { cdl_interface CYGINT_ISO_STDIO_ERROR { display "Number of implementations of stdio error handling" + flavor booldata requires { 1 >= CYGINT_ISO_STDIO_ERROR } }
--- a/packages/isoinfra/current/include/stdio.h +++ b/packages/isoinfra/current/include/stdio.h @@ -60,49 +60,55 @@ #define __need_size_t #include <stddef.h> -#if CYGINT_ISO_STDIO_FILETYPES +#ifdef CYGINT_ISO_STDIO_FILETYPES # ifdef CYGBLD_ISO_STDIO_FILETYPES_HEADER # include CYGBLD_ISO_STDIO_FILETYPES_HEADER # endif #endif -#if CYGINT_ISO_STDIO_FILEOPS +#ifdef CYGINT_ISO_STDIO_STREAMS +# ifdef CYGBLD_ISO_STDIO_STREAMS_HEADER +# include CYGBLD_ISO_STDIO_STREAMS_HEADER +# endif +#endif + +#ifdef CYGINT_ISO_STDIO_FILEOPS # ifdef CYGBLD_ISO_STDIO_FILEOPS_HEADER # include CYGBLD_ISO_STDIO_FILEOPS_HEADER # endif #endif -#if CYGINT_ISO_STDIO_FILEACCESS +#ifdef CYGINT_ISO_STDIO_FILEACCESS # ifdef CYGBLD_ISO_STDIO_FILEACCESS_HEADER # include CYGBLD_ISO_STDIO_FILEACCESS_HEADER # endif #endif -#if CYGINT_ISO_STDIO_FORMATTED_IO +#ifdef CYGINT_ISO_STDIO_FORMATTED_IO # ifdef CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER # include CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER # endif #endif -#if CYGINT_ISO_STDIO_CHAR_IO +#ifdef CYGINT_ISO_STDIO_CHAR_IO # ifdef CYGBLD_ISO_STDIO_CHAR_IO_HEADER # include CYGBLD_ISO_STDIO_CHAR_IO_HEADER # endif #endif -#if CYGINT_ISO_STDIO_DIRECT_IO +#ifdef CYGINT_ISO_STDIO_DIRECT_IO # ifdef CYGBLD_ISO_STDIO_DIRECT_IO_HEADER # include CYGBLD_ISO_STDIO_DIRECT_IO_HEADER # endif #endif -#if CYGINT_ISO_STDIO_FILEPOS +#ifdef CYGINT_ISO_STDIO_FILEPOS # ifdef CYGBLD_ISO_STDIO_FILEPOS_HEADER # include CYGBLD_ISO_STDIO_FILEPOS_HEADER # endif #endif -#if CYGINT_ISO_STDIO_ERROR +#ifdef CYGINT_ISO_STDIO_ERROR # ifdef CYGBLD_ISO_STDIO_ERROR_HEADER # include CYGBLD_ISO_STDIO_ERROR_HEADER # endif
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -300,6 +300,10 @@ 2000-06-08 Jesper Skov <jskov@redhat.c * src/debug/dbg-thread-demux.c: Use generic HAL feature to allow ROM/RAM intercalling. +2000-06-06 Jesper Skov <jskov@redhat.com> + + * tests/kcache1.c (entry0): Skip invalidate tests on TX49. Too slow. + 2000-05-30 Gary Thomas <gthomas@redhat.com> * tests/dhrystone.c: Increase number of test loops for faster @@ -344,6 +348,10 @@ 2000-05-20 Jonathan Larmour <jlarmour@ (Cyg_SchedulerThreadQueue_Implementation::enqueue): Add, like old one, except make it FIFO instead of LIFO by inserting at end of queue +2000-05-16 Jesper Skov <jskov@redhat.com> + + * tests/dhrystone.c: More loops on the TX49 + 2000-05-15 Jonathan Larmour <jlarmour@redhat.co.uk> * cdl/counters.cdl (CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY):
--- a/packages/kernel/current/tests/dhrystone.c +++ b/packages/kernel/current/tests/dhrystone.c @@ -80,6 +80,8 @@ dtime(void) #define PASSES 100000 #elif defined(CYGPKG_HAL_V85X_V850_CEB) #define PASSES 20000 +#elif defined(CYGPKG_HAL_MIPS_TX49_REF4955) +#define PASSES 1000000 #elif defined(CYGPKG_HAL_POWERPC_MPC8xx) #define PASSES 250000 #else
--- a/packages/kernel/current/tests/kcache1.c +++ b/packages/kernel/current/tests/kcache1.c @@ -324,6 +324,12 @@ static void entry0( cyg_addrword_t data if (cyg_test_is_simulator) CYG_TEST_PASS_FINISH("End of test"); +#if defined(CYGPKG_HAL_MIPS_TX49) + // The TX49 has a large cache, and even with reduced loop count, + // 90+ seconds elapses between each INFO output. + CYG_TEST_PASS_FINISH("End of test"); +#endif + cyg_test_is_simulator = 1; #endif #ifdef HAL_ICACHE_INVALIDATE_ALL
--- a/packages/language/c/libc/stdio/current/ChangeLog +++ b/packages/language/c/libc/stdio/current/ChangeLog @@ -1,3 +1,22 @@ +2000-11-01 Jonathan Larmour <jlarmour@redhat.com> + + * include/stdio.h: Make FILE array type larger to be more resistant + against small data sections. + Lose the cyg_libc_stdio_stdin/out/err definitions with macros for + stdin/stdout/err since it can cause problems with libgcc exception + code. Instead just make these extern FILE *s. + * src/common/stderr.cxx: + * src/common/stdin.cxx: + * src/common/stdout.cxx: + Define objects with init priority corresponding to order the fd's + should be allocated where applicable. + Define actual stdin, stdout, stderr externally visible constants to + point to the streams. + + * cdl/stdio.cdl: Support CYGINT_ISO_STDIO_STREAMS interface + + * src/common/fopen.cxx (fdopen): return f as intended + 2000-10-23 Jesper Skov <jskov@redhat.com> * include/streambuf.inl: Adjust assertions to cope with buffers
--- a/packages/language/c/libc/stdio/current/cdl/stdio.cdl +++ b/packages/language/c/libc/stdio/current/cdl/stdio.cdl @@ -56,6 +56,7 @@ cdl_package CYGPKG_LIBC_STDIO { implements CYGINT_ISO_STDIO_CHAR_IO implements CYGINT_ISO_STDIO_DIRECT_IO implements CYGINT_ISO_STDIO_ERROR + implements CYGINT_ISO_STDIO_STREAMS requires { CYGBLD_ISO_STDIO_FILETYPES_HEADER == \ "<cyg/libc/stdio/stdio.h>" } requires { CYGBLD_ISO_STDIO_FILEACCESS_HEADER == \ @@ -68,6 +69,8 @@ cdl_package CYGPKG_LIBC_STDIO { "<cyg/libc/stdio/stdio.h>" } requires { CYGBLD_ISO_STDIO_ERROR_HEADER == \ "<cyg/libc/stdio/stdio.h>" } + requires { CYGBLD_ISO_STDIO_STREAMS_HEADER == \ + "<cyg/libc/stdio/stdio.h>" } requires CYGPKG_ISOINFRA requires CYGINT_ISO_ERRNO_CODES requires CYGINT_ISO_ERRNO
--- a/packages/language/c/libc/stdio/current/include/stdio.h +++ b/packages/language/c/libc/stdio/current/include/stdio.h @@ -91,30 +91,19 @@ typedef cyg_ucount32 fpos_t; // The array size is irrelevant other than being more than 8, and is present // to stop references to FILEs being marked as able to be put in the small // data section. We can't just mark it as in the ".data" section as on some -// targets it may actually be ".common". Maybe this doesn't matter? -// FIXME: This doesn't work if things are larger than 16 are put in sdata, -// e.g. on mips by specifying -G 32 -typedef CYG_ADDRESS FILE[16]; +// targets it may actually be ".common". +typedef CYG_ADDRESS FILE[9999]; // EXTERNAL VARIABLES // Default file streams for input/output. These only need to be // expressions, not l-values - ISO C standard chap. 7.9.1 // -// cyg_libc_stdio_stdin/out/err aren't really files of course, -// but they are only named here so that we can take the address of -// them, in which case it doesn't matter what type they point to really -// // CYGPRI_LIBC_STDIO_NO_DEFAULT_STREAMS is used when initializing -// cyg_libc_stdio_stdin/out/err privately inside the C library +// stdin/out/err privately inside the C library #ifndef CYGPRI_LIBC_STDIO_NO_DEFAULT_STREAMS -extern FILE cyg_libc_stdio_stdin, cyg_libc_stdio_stdout, - cyg_libc_stdio_stderr; - -#define stdin (&cyg_libc_stdio_stdin) -#define stdout (&cyg_libc_stdio_stdout) -#define stderr (&cyg_libc_stdio_stderr) +__externC FILE *stdin, *stdout, *stderr; #endif // FUNCTION PROTOTYPES
--- a/packages/language/c/libc/stdio/current/src/common/fopen.cxx +++ b/packages/language/c/libc/stdio/current/src/common/fopen.cxx @@ -242,6 +242,7 @@ externC FILE *fdopen( int fd, const char Cyg_StdioStream *real_stream = (Cyg_StdioStream *)f; fpos_t pos = 0; real_stream->set_position( pos, SEEK_CUR ); + return f; } #endif // def CYGPKG_LIBC_STDIO_FILEIO
--- a/packages/language/c/libc/stdio/current/src/common/stderr.cxx +++ b/packages/language/c/libc/stdio/current/src/common/stderr.cxx @@ -64,12 +64,18 @@ #include <cyg/libc/stdio/stdiofiles.hxx> // C library files #include <cyg/libc/stdio/stdiosupp.hxx> // Cyg_libc_stdio_find_filename() +// CONSTANTS + +// add 2 to the priority to allow it to be the fd 2 if necessary +#define PRIO (CYG_INIT_LIBC+2) + // STATICS Cyg_StdioStream -cyg_libc_stdio_stderr CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC) = Cyg_StdioStream( +cyg_libc_stdio_stderr CYGBLD_ATTRIB_INIT_PRI(PRIO) = Cyg_StdioStream( Cyg_libc_stdio_find_filename(CYGDAT_LIBC_STDIO_DEFAULT_CONSOLE, - Cyg_StdioStream::CYG_STREAM_WRITE, false, false), + Cyg_StdioStream::CYG_STREAM_WRITE, + false, false), Cyg_StdioStream::CYG_STREAM_WRITE, false, false, _IONBF, 0, NULL ); // CLASSES @@ -86,6 +92,10 @@ public: // And here's an instance of the class just to make the code run static cyg_libc_dummy_stderr_init_class cyg_libc_dummy_stderr_init - CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC); + CYGBLD_ATTRIB_INIT_PRI(PRIO); + +// and finally stderr itself +__externC Cyg_StdioStream * const stderr; +Cyg_StdioStream * const stderr=&cyg_libc_stdio_stderr; // EOF stderr.cxx
--- a/packages/language/c/libc/stdio/current/src/common/stdin.cxx +++ b/packages/language/c/libc/stdio/current/src/common/stdin.cxx @@ -64,10 +64,15 @@ #include <cyg/libc/stdio/stdiofiles.hxx> // C library files #include <cyg/libc/stdio/stdiosupp.hxx> // Cyg_libc_stdio_find_filename() +// CONSTANTS + +// Use default libc priority to allow it to be the fd 0 if necessary +#define PRIO (CYG_INIT_LIBC) + // STATICS Cyg_StdioStream -cyg_libc_stdio_stdin CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC) = Cyg_StdioStream( +cyg_libc_stdio_stdin CYGBLD_ATTRIB_INIT_PRI(PRIO) = Cyg_StdioStream( Cyg_libc_stdio_find_filename(CYGDAT_LIBC_STDIO_DEFAULT_CONSOLE, Cyg_StdioStream::CYG_STREAM_READ, false, false), Cyg_StdioStream::CYG_STREAM_READ, false, false, _IOLBF ); @@ -87,5 +92,10 @@ public: // And here's an instance of the class just to make the code run static cyg_libc_dummy_stdin_init_class cyg_libc_dummy_stdin_init - CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC); + CYGBLD_ATTRIB_INIT_PRI(PRIO); + +// and finally stdin itself +__externC Cyg_StdioStream * const stdin; +Cyg_StdioStream * const stdin=&cyg_libc_stdio_stdin; + // EOF stdin.cxx
--- a/packages/language/c/libc/stdio/current/src/common/stdout.cxx +++ b/packages/language/c/libc/stdio/current/src/common/stdout.cxx @@ -64,12 +64,18 @@ #include <cyg/libc/stdio/stdiofiles.hxx> // C library files #include <cyg/libc/stdio/stdiosupp.hxx> // Cyg_libc_stdio_find_filename() +// CONSTANTS + +// add 1 to the priority to allow it to be the fd 1 if necessary +#define PRIO (CYG_INIT_LIBC+1) + // STATICS Cyg_StdioStream -cyg_libc_stdio_stdout CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC) = Cyg_StdioStream( +cyg_libc_stdio_stdout CYGBLD_ATTRIB_INIT_PRI(PRIO) = Cyg_StdioStream( Cyg_libc_stdio_find_filename(CYGDAT_LIBC_STDIO_DEFAULT_CONSOLE, - Cyg_StdioStream::CYG_STREAM_WRITE, false, false), + Cyg_StdioStream::CYG_STREAM_WRITE, + false, false), Cyg_StdioStream::CYG_STREAM_WRITE, false, false, _IOLBF ); // CLASSES @@ -86,6 +92,10 @@ public: // And here's an instance of the class just to make the code run static cyg_libc_dummy_stdout_init_class cyg_libc_dummy_stdout_init - CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_LIBC); + CYGBLD_ATTRIB_INIT_PRI(PRIO); + +// and finally stdout itself +__externC Cyg_StdioStream * const stdout; +Cyg_StdioStream * const stdout=&cyg_libc_stdio_stdout; // EOF stdout.cxx
--- a/packages/services/memalloc/common/current/ChangeLog +++ b/packages/services/memalloc/common/current/ChangeLog @@ -1,3 +1,8 @@ +2000-11-01 Jesper Skov <jskov@redhat.com> + + * tests/realloc.c (main): Use reasonable factor when making too + large realloc (targets with 64MB would cause an overflow). + 2000-10-31 Jonathan Larmour <jlarmour@redhat.com> * tests/testaux.hxx: Prototype cyg_hal_invoke_constructors()
--- a/packages/services/memalloc/common/current/tests/realloc.c +++ b/packages/services/memalloc/common/current/tests/realloc.c @@ -168,7 +168,7 @@ main( int argc, char *argv[] ) CYG_TEST_PASS_FAIL( fill_with_alphabet( str, size/4, 1 ), "reallocation quarter size usability"); - CYG_TEST_PASS_FAIL( realloc( str, size*100 ) == NULL, + CYG_TEST_PASS_FAIL( realloc( str, size*4 ) == NULL, "reallocing allocation that is too large" ); CYG_TEST_PASS_FAIL( compare_with_alphabet( str, size/4, 1 ), "Checking old contents maintained despite failure" );
--- a/packages/templates/all/ChangeLog +++ b/packages/templates/all/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Update inferred values for current CDL. + 2000-07-22 Jonathan Larmour <jlarmour@redhat.co.uk> * current.ect: Don't include signals package by default as it conflicts
--- a/packages/templates/all/current.ect +++ b/packages/templates/all/current.ect @@ -165,3 +165,11 @@ cdl_option CYGSEM_KERNEL_SCHED_ASR_GLOBA inferred_value 1 }; +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_SIGSETJMP_HEADER { + inferred_value 1 <cyg/posix/sigsetjmp.h> +}; +
--- a/packages/templates/default/ChangeLog +++ b/packages/templates/default/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Update inferred values for stdio streams header + 2000-08-02 Jonathan Larmour <jlarmour@redhat.co.uk> * current.ect: Update inferred values for current CDL
--- a/packages/templates/default/current.ect +++ b/packages/templates/default/current.ect @@ -119,3 +119,7 @@ cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER cdl_option CYGBLD_ISO_SETJMP_HEADER { inferred_value 1 <cyg/libc/setjmp/setjmp.h> }; + +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +};
--- a/packages/templates/elix/ChangeLog +++ b/packages/templates/elix/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Update values for current CDL + 2000-10-11 Jonathan Larmour <jlarmour@redhat.com> * current.ect: CYGPKG_NET_ETH_DRIVERS has been renamed to
--- a/packages/templates/elix/current.ect +++ b/packages/templates/elix/current.ect @@ -173,3 +173,15 @@ cdl_option CYGBLD_ISO_PTHREAD_IMPL_HEADE cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADER { inferred_value 1 <cyg/posix/limits.h> }; + +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_SIGSETJMP_HEADER { + inferred_value 1 <cyg/posix/sigsetjmp.h> +}; + +cdl_option CYGBLD_ISO_OPEN_MAX_HEADER { + inferred_value 1 <cyg/fileio/limits.h> +};
--- a/packages/templates/net/ChangeLog +++ b/packages/templates/net/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Update inferred values for current CDL + 2000-08-03 Gary Thomas <gthomas@redhat.com> * current.ect: Ethernet drivers have moved.
--- a/packages/templates/net/current.ect +++ b/packages/templates/net/current.ect @@ -175,5 +175,14 @@ cdl_option CYGSEM_KERNEL_SCHED_ASR_GLOBA inferred_value 1 }; +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; +cdl_option CYGBLD_ISO_SIGSETJMP_HEADER { + inferred_value 1 <cyg/posix/sigsetjmp.h> +}; +cdl_option CYGBLD_ISO_OPEN_MAX_HEADER { + inferred_value 1 <cyg/fileio/limits.h> +};
--- a/packages/templates/posix/ChangeLog +++ b/packages/templates/posix/ChangeLog @@ -1,3 +1,7 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Update inferred values for current CDL + 2000-07-24 Jonathan Larmour <jlarmour@redhat.co.uk> * current.ect: Add CYGPKG_LIBC_STARTUP and CYGPKG_LIBC_STARTUP because
--- a/packages/templates/posix/current.ect +++ b/packages/templates/posix/current.ect @@ -112,3 +112,10 @@ cdl_option CYGBLD_ISO_POSIX_LIMITS_HEADE inferred_value 1 <cyg/posix/limits.h> }; +cdl_option CYGBLD_ISO_SIGSETJMP_HEADER { + inferred_value 1 <cyg/posix/sigsetjmp.h> +}; + +cdl_option CYGBLD_ISO_OPEN_MAX_HEADER { + inferred_value 1 <cyg/fileio/limits.h> +};
--- a/packages/templates/stubs/ChangeLog +++ b/packages/templates/stubs/ChangeLog @@ -1,3 +1,8 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Add inferred values for CDL that confuses the + config tool inference engine at present. + 2000-07-20 Nick Garnett <nickg@cygnus.co.uk> * current.ect: Added ISOINFRA package.
--- a/packages/templates/stubs/current.ect +++ b/packages/templates/stubs/current.ect @@ -21,3 +21,20 @@ This is the eCos stubs configuration. It cdl_option CYGBLD_BUILD_GDB_STUBS { user_value 1 ; }; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + inferred_value 1 <cyg/error/codes.h> +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + inferred_value 1 <cyg/error/errno.h> +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + inferred_value 1 <cyg/error/strerror.h> +}; + +cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO { + inferred_value 0 +}; +
--- a/packages/templates/uitron/ChangeLog +++ b/packages/templates/uitron/ChangeLog @@ -1,3 +1,8 @@ +2000-11-03 Jonathan Larmour <jlarmour@redhat.com> + + * current.ect: Add inferred values for CDL that confuses the + config tool inference engine at present. + 2000-09-07 Jonathan Larmour <jlarmour@redhat.com> * current.ect: Add libc signals package because there's no real reason
--- a/packages/templates/uitron/current.ect +++ b/packages/templates/uitron/current.ect @@ -35,3 +35,96 @@ features." ; }; +cdl_option CYGBLD_ISO_CTYPE_HEADER { + inferred_value 1 <cyg/libc/i18n/ctype.inl> +}; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + inferred_value 1 <cyg/error/codes.h> +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + inferred_value 1 <cyg/error/errno.h> +}; + +cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER { + inferred_value 1 <cyg/libc/stdio/stdio.h> +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + inferred_value 1 <cyg/libc/stdlib/atox.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + inferred_value 1 <cyg/libc/stdlib/abs.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + inferred_value 1 <cyg/libc/stdlib/div.inl> +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + inferred_value 1 <cyg/error/strerror.h> +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER { + inferred_value 1 <cyg/libc/time/time.h> +}; + +cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER { + inferred_value 1 <cyg/libc/time/time.h> +}; + +cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER { + inferred_value 1 <cyg/libc/signals/signal.h> +}; + +cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER { + inferred_value 1 <cyg/libc/signals/signal.h> +}; + +cdl_option CYGBLD_ISO_SETJMP_HEADER { + inferred_value 1 <cyg/libc/setjmp/setjmp.h> +}; + +