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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 842a82a508f3
children
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg, jskov,
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47 // jlarmour
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48 // Date: 1999-02-19
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49 // Purpose: Define Interrupt support
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // interrupts and the clock.
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52 //
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53 // Usage:
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54 // #include <cyg/hal/hal_intr.h>
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55 // ...
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56 //
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57 //
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58 //####DESCRIPTIONEND####
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59 //
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60 //==========================================================================
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61
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62 #include <pkgconf/hal.h>
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63
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64 #include <cyg/infra/cyg_type.h> // types
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65
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66 #include <cyg/hal/ppc_regs.h> // register definitions
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67
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68 #include <cyg/hal/var_intr.h> // variant extensions
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70 //--------------------------------------------------------------------------
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71 // PowerPC exception vectors. These correspond to VSRs and are the values
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72 // to use for HAL_VSR_GET/SET
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73
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74 #define CYGNUM_HAL_VECTOR_RESERVED_0 0
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75 #define CYGNUM_HAL_VECTOR_RESET 1
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76 #define CYGNUM_HAL_VECTOR_MACHINE_CHECK 2
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77 #define CYGNUM_HAL_VECTOR_DSI 3
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78 #define CYGNUM_HAL_VECTOR_ISI 4
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79 #define CYGNUM_HAL_VECTOR_INTERRUPT 5
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80 #define CYGNUM_HAL_VECTOR_ALIGNMENT 6
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81 #define CYGNUM_HAL_VECTOR_PROGRAM 7
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82 #define CYGNUM_HAL_VECTOR_FP_UNAVAILABLE 8
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83 #define CYGNUM_HAL_VECTOR_DECREMENTER 9
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84 #define CYGNUM_HAL_VECTOR_RESERVED_A 10
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85 #define CYGNUM_HAL_VECTOR_RESERVED_B 11
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86 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 12
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87 #define CYGNUM_HAL_VECTOR_TRACE 13
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88 #define CYGNUM_HAL_VECTOR_FP_ASSIST 14
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89
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90 #ifdef CYGHWR_HAL_POWERPC_BOOK_E
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91
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92 // Additional exceptions on Book E CPUs. The numbers here do not
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93 // necessarily correspond to the IVOR register number for the
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94 // exception, but they must correspond to the table position in the
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95 // rom_vectors table defined in vectors.S.
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96
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97 #define CYGNUM_HAL_VECTOR_RESERVED_F 15
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98 #define CYGNUM_HAL_VECTOR_CRITICAL_INPUT 16
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99 #define CYGNUM_HAL_VECTOR_AP_UNAVAILABLE 17
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100 #define CYGNUM_HAL_VECTOR_FIT 18
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101 #define CYGNUM_HAL_VECTOR_WATCHDOG 19
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102 #define CYGNUM_HAL_VECTOR_DTLB_MISS 20
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103 #define CYGNUM_HAL_VECTOR_ITLB_MISS 21
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104 #define CYGNUM_HAL_VECTOR_DEBUG 22
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105 #define CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE 23
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106 #define CYGNUM_HAL_VECTOR_SPE_FP_DATA 24
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107 #define CYGNUM_HAL_VECTOR_SPE_FP_ROUND 25
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108
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109 #ifndef CYGNUM_HAL_VSR_MAX
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110 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SPE_FP_ROUND
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111 #endif
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112
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113 #endif
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114
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115
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116 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESERVED_0
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117 #ifndef CYGNUM_HAL_VSR_MAX
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118 # define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST
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119 #endif
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120 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
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121
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122 #ifndef CYG_VECTOR_IS_INTERRUPT
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123 # define CYG_VECTOR_IS_INTERRUPT(v) \
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124 (CYGNUM_HAL_VECTOR_INTERRUPT == (v) \
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125 || CYGNUM_HAL_VECTOR_DECREMENTER == (v))
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126 #endif
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127
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128 // The decoded interrupts.
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129 // Define decrementer as the first interrupt since it is guaranteed to
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130 // be defined on all PowerPCs. External may expand into several interrupts
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131 // depending on interrupt controller capabilities.
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132
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133 #ifndef CYGHWR_HAL_POWERPC_BOOK_E
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134
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135 #define CYGNUM_HAL_INTERRUPT_DECREMENTER 0
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136 #define CYGNUM_HAL_INTERRUPT_EXTERNAL 1
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137
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138 #else
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139
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140 // For Book E processors, in addition the the decrementer, there are
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141 // also a fixed interval timer and a watchdog which can generate
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142 // asynchronous interrupts.
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143
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144 #define CYGNUM_HAL_INTERRUPT_DECREMENTER 0
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145 #define CYGNUM_HAL_INTERRUPT_INTERVAL 1
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146 #define CYGNUM_HAL_INTERRUPT_WATCHDOG 2
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147 #define CYGNUM_HAL_INTERRUPT_EXTERNAL 3
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148
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149 #endif
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150
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151 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER
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152 #ifndef CYGNUM_HAL_ISR_MAX
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153 # define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL
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154 #endif
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155 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 )
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156
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157 #ifndef CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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158 // Exception vectors. These are the values used when passed out to an
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159 // external exception handler using cyg_hal_deliver_exception()
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160
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161 #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
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162 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
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163 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI
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164 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI
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165 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT
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166 #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
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167 #define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
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168 #define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
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169 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
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170 #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
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171 #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
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172
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173 #ifdef CYGHWR_HAL_POWERPC_BOOK_E
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174
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175 #define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
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176 #define CYGNUM_HAL_EXCEPTION_CRITICAL_INPUT CYGNUM_HAL_VECTOR_CRITICAL_INPUT
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177 #define CYGNUM_HAL_EXCEPTION_AP_UNAVAILABLE CYGNUM_HAL_VECTOR_AP_UNAVAILABLE
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178 #define CYGNUM_HAL_EXCEPTION_FIT CYGNUM_HAL_VECTOR_FIT
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179 #define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG
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180 #define CYGNUM_HAL_EXCEPTION_DTLB_MISS CYGNUM_HAL_VECTOR_DTLB_MISS
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181 #define CYGNUM_HAL_EXCEPTION_ITLB_MISS CYGNUM_HAL_VECTOR_ITLB_MISS
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182 #define CYGNUM_HAL_EXCEPTION_DEBUG CYGNUM_HAL_VECTOR_DEBUG
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183 #define CYGNUM_HAL_EXCEPTION_SPE_UNAVAILABLE CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE
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184 #define CYGNUM_HAL_EXCEPTION_SPE_FP_DATA CYGNUM_HAL_VECTOR_SPE_FP_DATA
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185 #define CYGNUM_HAL_EXCEPTION_SPE_FP_ROUND CYGNUM_HAL_VECTOR_SPE_FP_ROUND
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186
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187 #endif
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188
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189 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
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190 #ifndef CYGNUM_HAL_EXCEPTION_MAX
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191 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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192 #endif
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193
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194 #define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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195
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196 #endif // CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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197
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198 #ifndef CYGHWR_HAL_POWERPC_BOOK_E
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199 // FIXME: This is still rather ugly. Should probably be made variant
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200 // specific using a decode_hal_exception macro or somesuch.
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201 // decoded exception vectors
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202 #define CYGNUM_HAL_EXCEPTION_TRAP (-1)
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203 #define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2)
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204 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3)
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205 #define CYGNUM_HAL_EXCEPTION_FPU (-4)
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206
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207 #undef CYGNUM_HAL_EXCEPTION_MIN
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208 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU
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209 #endif
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210
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211 #define CYGNUM_HAL_EXCEPTION_COUNT \
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212 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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213
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214 //--------------------------------------------------------------------------
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215 // Static data used by HAL
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216
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217 // ISR tables
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218 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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219 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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220 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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221 // VSR table
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222 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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223
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224 //--------------------------------------------------------------------------
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225 // Default ISRs
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226 // The #define is used to test whether this routine exists, and to allow
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227 // us to call it.
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228
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229 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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230 externC cyg_uint32 hal_default_decrementer_isr(CYG_ADDRWORD vector,
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231 CYG_ADDRWORD data);
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232
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233 #define HAL_DEFAULT_ISR hal_default_isr
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234
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235 //--------------------------------------------------------------------------
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236 // Interrupt state storage
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237
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238 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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239
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240 //--------------------------------------------------------------------------
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241 // Interrupt control macros
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242
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243 #if !defined(CYGHWR_HAL_POWERPC_BOOK_E)
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244 #define CYGARC_REG_MSR_INTBITS CYGARC_REG_MSR_EE
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245 #else
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246 #define CYGARC_REG_MSR_INTBITS (CYGARC_REG_MSR_EE|CYGARC_REG_MSR_CE)
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247 #endif
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248
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249 #define HAL_DISABLE_INTERRUPTS(_old_) \
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250 CYG_MACRO_START \
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251 cyg_uint32 tmp1 = ~CYGARC_REG_MSR_INTBITS; \
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252 cyg_uint32 tmp2; \
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253 asm volatile ( \
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254 "mfmsr %0;" \
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255 "mr %2,%0;" \
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256 "and %2,%2,%1;" \
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257 "mtmsr %2;" \
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258 : "=r"(_old_), "+r" (tmp1), "=r" (tmp2)); \
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259 CYG_MACRO_END
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260
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261 #define HAL_ENABLE_INTERRUPTS() \
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262 CYG_MACRO_START \
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263 cyg_uint32 tmp1; \
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264 cyg_uint32 tmp2 = CYGARC_REG_MSR_INTBITS; \
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265 asm volatile ( \
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266 "mfmsr %0;" \
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267 "or %0,%0,%1;" \
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268 "mtmsr %0;" \
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269 : "=r" (tmp1), "+r" (tmp2)); \
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270 CYG_MACRO_END
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271
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272 #define HAL_RESTORE_INTERRUPTS(_old_) \
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273 CYG_MACRO_START \
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274 cyg_uint32 tmp1; \
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275 cyg_uint32 tmp2 = ~CYGARC_REG_MSR_INTBITS; \
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276 asm volatile ( \
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277 "mfmsr %0;" \
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278 "and %0,%0,%1;" \
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279 "not %1,%1;" \
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280 "and %1,%1,%2;" \
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281 "or %0,%0,%1;" \
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282 "mtmsr %0;" \
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283 : "=&r" (tmp1), "+r" (tmp2) \
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284 : "r" (_old_)); \
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285 CYG_MACRO_END
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286
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287 #define HAL_QUERY_INTERRUPTS(_old_) \
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288 CYG_MACRO_START \
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289 cyg_uint32 tmp = CYGARC_REG_MSR_INTBITS; \
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290 asm volatile ( \
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291 "mfmsr %0;" \
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292 "and %0,%0,%1;" \
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293 : "=&r"(_old_) \
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294 : "r" (tmp)); \
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295 CYG_MACRO_END
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296
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297 //--------------------------------------------------------------------------
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298 // Machine check manipulation
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299 #define HAL_DISABLE_MACHINE_CHECK(_old_) \
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300 CYG_MACRO_START \
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301 cyg_uint32 tmp1, tmp2; \
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302 asm volatile ( \
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303 "mfmsr %0;" \
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304 "mr %2,%0;" \
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305 "li %1,0;" \
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306 "rlwimi %2,%1,0,19,19;" \
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307 "mtmsr %2;" \
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308 : "=r"(_old_), "=r" (tmp1), "=r" (tmp2)); \
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309 CYG_MACRO_END
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310
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311 #define HAL_ENABLE_MACHINE_CHECK() \
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312 CYG_MACRO_START \
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313 cyg_uint32 tmp1, tmp2; \
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314 asm volatile ( \
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315 "mfmsr %0;" \
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316 "lis %1,%1,0x0001;" \
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317 "rlwimi %0,%1,0,19,19;" \
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318 "mtmsr %0;" \
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319 : "=r" (tmp1), "=r" (tmp2)); \
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320 CYG_MACRO_END
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321
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322 #define HAL_QUERY_MACHINE_CHECK(_old_) \
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323 CYG_MACRO_START \
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324 cyg_uint32 tmp; \
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325 asm volatile ( \
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326 "mfmsr %0;" \
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327 "lis %1,0x0001;" \
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328 "and %0,%0,%1;" \
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329 : "=&r"(_old_), "=r" (tmp)); \
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330 CYG_MACRO_END
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331
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332 //--------------------------------------------------------------------------
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333 // Vector translation.
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334
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335 #ifndef HAL_TRANSLATE_VECTOR
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336 // Basic PowerPC configuration only has two vectors; decrementer and
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337 // external. Isr tables/chaining use same vector decoder.
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338 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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339 (_index_) = (_vector_)
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340 #endif
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341
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342 //--------------------------------------------------------------------------
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343 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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344
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345 externC void hal_interrupt_stack_call_pending_DSRs(void);
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346 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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347 hal_interrupt_stack_call_pending_DSRs()
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348
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349 // these are offered solely for stack usage testing
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350 // if they are not defined, then there is no interrupt stack.
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351 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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352 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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353 // use them to declare these extern however you want:
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354 // extern char HAL_INTERRUPT_STACK_BASE[];
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355 // extern char HAL_INTERRUPT_STACK_TOP[];
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356 // is recommended
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357 #endif
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358
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359 //--------------------------------------------------------------------------
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360 // Interrupt and VSR attachment macros
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361
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362 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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363 CYG_MACRO_START \
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364 cyg_uint32 _index_; \
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365 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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366 \
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367 if((hal_interrupt_handlers[_index_] \
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368 == (CYG_ADDRESS)hal_default_decrementer_isr) \
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369 || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \
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370 (_state_) = 0; \
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371 else \
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372 (_state_) = 1; \
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373 CYG_MACRO_END
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374
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375 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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376 CYG_MACRO_START \
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377 cyg_uint32 _index_; \
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378 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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379 \
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380 if((hal_interrupt_handlers[_index_] \
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381 == (CYG_ADDRESS)hal_default_decrementer_isr) \
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382 || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \
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383 { \
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384 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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385 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
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386 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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387 } \
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388 CYG_MACRO_END
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389
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390 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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391 CYG_MACRO_START \
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392 cyg_uint32 _index_; \
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393 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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394 \
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395 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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396 { \
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397 if (CYGNUM_HAL_INTERRUPT_DECREMENTER == (_vector_)) \
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398 hal_interrupt_handlers[_index_] = \
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399 (CYG_ADDRESS)hal_default_decrementer_isr; \
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400 else \
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401 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
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402 hal_interrupt_data[_index_] = 0; \
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403 hal_interrupt_objects[_index_] = 0; \
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404 } \
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405 CYG_MACRO_END
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406
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407 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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408 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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409
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410
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411 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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412 CYG_MACRO_START \
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413 if( _poldvsr_ != NULL ) \
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414 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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415 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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416 CYG_MACRO_END
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417
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418 // This is an ugly name, but what it means is: grab the VSR back to eCos
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419 // internal handling, or if you like, the default handler. But if
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420 // cooperating with GDB and CygMon, the default behaviour is to pass most
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421 // exceptions to CygMon. This macro undoes that so that eCos handles the
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422 // exception. So use it with care.
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423 externC void cyg_hal_default_interrupt_vsr( void );
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424 externC void cyg_hal_default_exception_vsr( void );
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425 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
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426 CYG_MACRO_START \
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427 if( (void*)_poldvsr_ != (void*)NULL ) \
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428 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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429 hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
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430 ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
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431 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
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432 CYG_MACRO_END
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433
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434
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435 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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436
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437 #define HAL_INTERRUPT_MASK( _vector_ )
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438
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439 #define HAL_INTERRUPT_UNMASK( _vector_ )
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440
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441 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
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442
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443 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
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444
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445 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
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446
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447 #endif
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448
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449 //--------------------------------------------------------------------------
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450 // Clock control
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451
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452 #ifndef CYGHWR_HAL_CLOCK_DEFINED
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453 // Note: variant or platform allowed to override these definitions
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454
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455 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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456 CYG_MACRO_START \
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457 asm volatile ( \
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458 "mtdec %0;" \
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459 : \
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460 : "r"(_period_) \
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461 ); \
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462 CYG_MACRO_END
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463
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464 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
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465 CYG_MACRO_START \
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466 cyg_uint32 tmp; \
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467 asm volatile ( \
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468 "mfdec %0;" \
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469 "add. %0,%0,%1;" \
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470 "bgt 1f;" \
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471 "mr %0,%1;" \
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472 "1: mtdec %0;" \
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473 : "=&r" (tmp) \
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474 : "r"(_period_) \
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475 : "cc" \
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476 ); \
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477 CYG_MACRO_END
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478
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479 #define HAL_CLOCK_READ( _pvalue_ ) \
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480 CYG_MACRO_START \
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481 register cyg_uint32 result; \
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482 asm volatile( \
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483 "mfdec %0;" \
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484 : "=r"(result) \
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485 ); \
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486 *(_pvalue_) = CYGNUM_HAL_RTC_PERIOD-result; \
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487 CYG_MACRO_END
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488
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489 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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490 #define HAL_CLOCK_LATENCY( _pvalue_ ) \
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491 CYG_MACRO_START \
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492 register cyg_int32 result; \
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493 asm volatile( \
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494 "mfdec %0;" \
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495 : "=r"(result) \
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496 ); \
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497 /* Pending DEC interrupts cannot be discarded. If dec is */ \
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498 /* positive it''s because a DEC interrupt occured while */ \
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499 /* eCos was getting ready to run. Just return 0 in that */ \
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500 /* case. */ \
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501 if (result > 0) \
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502 result = 0; \
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503 *(_pvalue_) = -result; \
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504 CYG_MACRO_END
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505 #endif
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506
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507 #ifndef HAL_DELAY_US
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508 externC void hal_delay_us(int);
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509 #define HAL_DELAY_US(n) hal_delay_us(n)
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510 #endif
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511
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512 // The vector used by the Real time clock
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513 #ifndef CYGNUM_HAL_INTERRUPT_RTC
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514 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_DECREMENTER
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515 #endif // CYGNUM_HAL_INTERRUPT_RTC
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516
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517 #endif // CYGHWR_HAL_CLOCK_DEFINED
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518
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519 //--------------------------------------------------------------------------
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520 // Variant functions
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521 externC void hal_variant_IRQ_init(void);
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522
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523 //--------------------------------------------------------------------------
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524 #endif // ifndef CYGONCE_HAL_INTR_H
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525 // End of hal_intr.h