Mercurial > ecos
changeset 2883:842a82a508f3
Add Book E architecture support. See the ChangeLog for full details.
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--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,17 @@ +2009-04-24 Nick Garnett <nickg@ecoscentric.com> + + * include/hal_arch.h (GDB_Registers): Redefine for Book E + processors which need a slightly different register vector layout + and size. + + * include/ppc_stub.h (REGSIZE, NUMREGS): Add definitions for Book + E processors. + +2009-01-15 Jonathan Larmour <jifl@eCosCentric.com> + + * include/arch.inc: Incorporate changes of 2008-09-23 and 2007-10-12 + into hal_vectors_init. + 2008-10-31 Jonathan Larmour <jifl@eCosCentric.com> * src/powerpc.ld (SECTION_data): Do not define _GLOBAL_OFFSET_TABLE_ @@ -11,13 +25,103 @@ 2008-10-10 Jonathan Larmour <jifl@eCos 2008-09-23 Shaun Louie <sal@microplex.com> - * src/vectors.S: Changed compile condition that determines whether - exception vectors should be copied to RAM. + * src/vectors.S: Changed compile condition that determines whether + exception vectors should be copied to RAM. + +2008-07-23 Nick Garnett <nickg@ecoscentric.com> + + * src/vectors.S: + * src/context.S: Modify invocation of hal_cpu_int_merge. + + * include/ppc_regs.h: Add full definitions of bits in TCR and TSR. + + * include/hal_intr.h: Define additional interval timer and + watchdog interrupt vectors for Book E processors. + Rewrite interrupt control macros to allow for multiple interrupt + enable bits in MSR. Mainly for Book E, which has both external and + critical interrupt control bits. + + * include/arch.inc: Rewrite interrupt control macros to allow for + multiple interrupt enable bits in MSR. Mainly for Book E, which + has both external and critical interrupt control bits. + + * src/hal_mk_defs.c (main): Add CYGNUM_HAL_VECTOR_FIT definition. + +2008-07-04 Nick Garnett <nickg@ecoscentric.com> + + * src/hal_misc.c (hal_enable_caches): Change ifdefs controlling + cache invalidation and enable to permit a JTAG startup type. + + * src/vectors.S (cyg_hal_default_critical_exception_vsr): Fix typo + in final branch destination. + +2007-11-29 Nick Garnett <nickg@ecoscentric.com> + + * include/hal_intr.h: For Book E processors, disable the negative + exception numbers. These cause various problems, in particular in + VSR setting routines. They are of little utility normally, so for + now are disabled. + + * include/ppc_regs.h (CYGARC_REG_ESR): Add definitions for + exception syndrome register. + + * src/ppc_stub.c (__computeSignal): + * src/hal_misc.c (cyg_hal_exception_handler): Disable decoding + program sub-exceptions from MSR/SRR1 in Book E processors. + +2007-11-28 Nick Garnett <nickg@ecoscentric.com> + + * src/vectors.S: Use CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT to place + vector trampolines and to generate vector numbers and table + offsets. + (rom_vectors): Add Book E vectors. + (_start): Replace inline code to copy vectors with call to + hal_vectors_init macro, which is processor type specific. + (cyg_hal_default_exception_vsr, cyg_hal_default_interrupt_vsr) + (cyg_hal_default_critical_exception_vsr) + (cyg_hal_default_critical_interrupt_vsr): Reorganize saving of PC + and MSR from SRR0/1 or CSRR0/1 to accommodate critical + exceptions. This includes adding extra critical + exception/interrupt VSRs. + + * src/ppc_stub.c (__get_trap_number): + Use CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT to generate vector number + from vector offset. + + * src/hal_mk_defs.c (main): Add Book E definitions. + + * src/hal_misc.c (hal_enable_caches): Add support for a unified + cache. + + * include/ppc_regs.h: Add variations for Book E processors. These + have slightly different bits in the MSR and extra SPRs for + decrementer and timebase control. + + * include/hal_intr.h: Add additional exception vectors for Book E + processors. + + * include/arch.inc: Add variants of hal_vectors_init for Book E + and non-Book E processors. + + * cdl/hal_powerpc.cdl: Add CYGHWR_HAL_POWERPC_BOOK_E and + CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT options to support Book E + processors. + Change CYGHWR_HAL_POWERPC_VECTOR_BASE to default_value from + calculated so that platform HALs can redfine it. + +2007-11-22 Nick Garnett <nickg@ecoscentric.com> + + * src/ppc_stub.c (__get_trap_number): Use + CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT to translate vector number. 2007-10-12 Gary Thomas <gary@mlbassoc.com> * src/vectors.S: Optimize system initialization of DATA/BSS/etc. +2006-08-24 Jonathan Larmour <jifl@eCosCentric.com> + + * include/hal_io.h: Add default definition of HAL_MEMORY_BARRIER(). + 2006-04-18 Gary Thomas <gary@mlbassoc.com> * include/hal_arch.h: Adjust stack sizes - they were too small @@ -41,6 +145,11 @@ 2005-06-03 Jonathan Larmour <jifl@eCos * src/powerpc.ld: gcc_except_table needs to be marked KEEP. +2005-06-02 Jonathan Larmour <jifl@eCosCentric.com> + + * include/arch.inc: Add multiple inclusion protection - recent + binutils now minds where it didn't before. + 2005-03-14 Peter Korsgaard <jacmetd@sunsite.dk> * src/redboot_linux_exec.c (do_exec): Correctly set bi_size. @@ -84,6 +193,11 @@ 2004-04-22 Jani Monoses <jani@iv.ro> * cdl/hal_powerpc.cdl : Invoke tail with stricter syntax that works in latest coreutils. +2004-01-05 Nick Garnett <nickg@calivar.com> + + * include/hal_intr.h: Changed use of + CYGNUM_KERNEL_COUNTERS_RTC_PERIOD to CYGNUM_HAL_RTC_PERIOD. + 2003-12-11 Gary Thomas <gary@mlbassoc.com> * include/hal_intr.h: Add macros to manipulate machine check enable @@ -1815,7 +1929,7 @@ Mon Aug 17 16:23:46 1998 Jesper Skov < // ####GPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by
--- a/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl +++ b/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl @@ -8,7 +8,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -144,13 +144,36 @@ cdl_package CYGPKG_HAL_POWERPC { 0xfff00000. The startup type and platform HAL controls which is used." flavor data - calculated { (! CYGHWR_HAL_POWERPC_FORCE_VECTOR_BASE_LOW && + default_value { (! CYGHWR_HAL_POWERPC_FORCE_VECTOR_BASE_LOW && (CYGHWR_HAL_POWERPC_FORCE_VECTOR_BASE_HIGH || (CYG_HAL_STARTUP != "RAM" && ! CYGSEM_HAL_POWERPC_COPY_VECTORS))) ? 0xfff00000 : 0x00000000 } } + cdl_option CYGHWR_HAL_POWERPC_BOOK_E { + display "Enable Book E support" + default_value 0 + description " + This option enables PowerPC Book E support in the architecture + HAL. Book E defines a number of changes to the PowerPC architecture + to better support embedded applications. These changes primarily + manifest themselves here in changes to the contents of the MSR and + exception delivery." + } + + cdl_option CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT { + display "Exception vector aligment" + flavor data + default_value (CYGHWR_HAL_POWERPC_BOOK_E ? 6 : 8) + description " + The standard AIM architecture has exception vectors placed at fixed + 256 byte intervals. The Book E processors allow these vectors to be + placed on any 16 byte offset. To keep the changes to the HAL minimal, + the vectors are still placed at fixed intervals, however, this interval + has been reduced to 64 bytes." + } + cdl_option CYGHWR_HAL_POWERPC_ENABLE_MMU { display "Enable MMU" default_value { !CYGHWR_HAL_POWERPC_DISABLE_MMU }
--- a/packages/hal/powerpc/arch/current/include/arch.inc +++ b/packages/hal/powerpc/arch/current/include/arch.inc @@ -10,7 +10,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -59,6 +59,7 @@ #include <cyg/hal/variant.inc> #include <cyg/hal/ppc_offsets.inc> +#include <cyg/hal/ppc_regs.h> #------------------------------------------------------------------------------ # Easier to read names for the registers @@ -194,11 +195,17 @@ name: ## operations that may have CPU specific implementations on different ## variants of the architecture. +#if !defined(CYGHWR_HAL_POWERPC_BOOK_E) +#define CYGARC_REG_MSR_INTBITS CYGARC_REG_MSR_EE +#else +#define CYGARC_REG_MSR_INTBITS (CYGARC_REG_MSR_EE|CYGARC_REG_MSR_CE) +#endif + # Enable interrupts .macro hal_cpu_int_enable mfmsr r0 - ori r3,r3,0x8000 - rlwimi r0,r3,0,16,16 + lwi r3,CYGARC_REG_MSR_INTBITS + or r0,r0,r3 sync mtmsr r0 sync @@ -207,8 +214,8 @@ name: # Disable interrupts .macro hal_cpu_int_disable mfmsr r0 - li r3,0 - rlwimi r0,r3,0,16,16 + lwi r3,~CYGARC_REG_MSR_INTBITS + and r0,r0,r3 sync mtmsr r0 sync @@ -216,15 +223,93 @@ name: # Merge the interrupt enable state of the status register in # \sr with the current sr. - .macro hal_cpu_int_merge sr + .macro hal_cpu_int_merge sr,wr mfmsr r0 - rlwimi r0,\sr,0,16,16 + lwi \wr,CYGARC_REG_MSR_INTBITS + and \wr,\wr,\sr + or r0,r0,\wr sync mtmsr r0 sync .endm #------------------------------------------------------------------------------ +# Book E variations +# +# These macros implement things that vary between the AIM architecture and +# Book E. + +#if !defined(CYGHWR_HAL_POWERPC_BOOK_E) + +#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS + + .macro hal_vectors_init + lwi r3,rom_vectors-4 + lwi r4,((CYGHWR_HAL_POWERPC_VECTOR_BASE)-4) + lwi r5,rom_vectors_end-4 + sub r5,r5,r3 # compute number of words to copy + srwi r5,r5,2 + mtctr r5 +0: lwzu r0,4(r3) + stwu r0,4(r4) + bdnz 0b + .endm + +#define HAL_VECTORS_INIT_DEFINED + +#endif + +#else // !defined(CYGHWR_HAL_POWERPC_BOOK_E) + +#if defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) + + .macro hal_ivor_init ivor,handler + lwi r3,__exception_\handler + and r3,r3,r4 + mtspr \ivor,r3 + .endm + + .macro hal_vectors_init + lwi r3,rom_vectors + lwi r4,0xFFFF0000 + and r3,r3,r4 + mtspr 63,r3 +#if defined(CYGHWR_HAL_POWERPC_NEED_VECTORS) + lwi r4,0x0000FFF0 + hal_ivor_init 400,critical_input + hal_ivor_init 401,machine_check + hal_ivor_init 402,data_storage + hal_ivor_init 403,instruction_storage + hal_ivor_init 404,external + hal_ivor_init 405,alignment + hal_ivor_init 406,program + hal_ivor_init 407,floatingpoint_unavailable + hal_ivor_init 408,system_call + hal_ivor_init 409,ap_unavailable + hal_ivor_init 410,decrementer + hal_ivor_init 411,interval_timer + hal_ivor_init 412,watchdog + hal_ivor_init 413,data_tlb_miss + hal_ivor_init 414,instruction_tlb_miss + hal_ivor_init 415,debug +#endif + .endm + +#define HAL_VECTORS_INIT_DEFINED + +#endif + +#endif // !defined(CYGHWR_HAL_POWERPC_BOOK_E) + + +#if !defined(HAL_VECTORS_INIT_DEFINED) + + .macro hal_vectors_init + .endm + +#endif + +#------------------------------------------------------------------------------ # end of arch.inc #endif // _CYGONCE_HAL_POWERPC_ARCH_INC_
--- a/packages/hal/powerpc/arch/current/include/hal_arch.h +++ b/packages/hal/powerpc/arch/current/include/hal_arch.h @@ -201,25 +201,44 @@ asm volatile (" .globl " #_label_ ";" //----------------------------------------------------------------------------- // Thread register state manipulation for GDB support. + +#ifndef CYGHWR_HAL_POWERPC_BOOK_E + typedef struct { cyg_uint32 gpr[32]; // General purpose registers - double f0[16]; // First sixteen floating point regs - cyg_uint32 pc; - cyg_uint32 msr; - cyg_uint32 cr; - cyg_uint32 lr; - cyg_uint32 ctr; - cyg_uint32 xer; - cyg_uint32 mq; + double f0[16]; // First sixteen floating point regs + cyg_uint32 pc; + cyg_uint32 msr; + cyg_uint32 cr; + cyg_uint32 lr; + cyg_uint32 ctr; + cyg_uint32 xer; + cyg_uint32 mq; #ifdef CYGHWR_HAL_POWERPC_FPU - double f16[16]; // Last sixteen floating point regs - // Could probably also be inserted in the middle - // Adding them at the end minimises the risk of - // breaking existing implementations that do not - // have floating point registers. + double f16[16]; // Last sixteen floating point regs + // Could probably also be inserted in the middle + // Adding them at the end minimises the risk of + // breaking existing implementations that do not + // have floating point registers. #endif } GDB_Registers; +#else + +typedef struct { + cyg_uint32 gpr[32]; // General purpose registers + cyg_uint32 ev[32]; // SPE register extensions (not currently supported) + cyg_uint32 pc; + cyg_uint32 msr; + cyg_uint32 cr; + cyg_uint32 lr; + cyg_uint32 ctr; + cyg_uint32 xer; +} GDB_Registers; + +#endif + + // Translate a stack pointer as saved by the thread context macros above into // a pointer to a HAL_SavedRegisters structure. #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
--- a/packages/hal/powerpc/arch/current/include/hal_intr.h +++ b/packages/hal/powerpc/arch/current/include/hal_intr.h @@ -11,7 +11,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -87,6 +87,32 @@ #define CYGNUM_HAL_VECTOR_TRACE 13 #define CYGNUM_HAL_VECTOR_FP_ASSIST 14 +#ifdef CYGHWR_HAL_POWERPC_BOOK_E + +// Additional exceptions on Book E CPUs. The numbers here do not +// necessarily correspond to the IVOR register number for the +// exception, but they must correspond to the table position in the +// rom_vectors table defined in vectors.S. + +#define CYGNUM_HAL_VECTOR_RESERVED_F 15 +#define CYGNUM_HAL_VECTOR_CRITICAL_INPUT 16 +#define CYGNUM_HAL_VECTOR_AP_UNAVAILABLE 17 +#define CYGNUM_HAL_VECTOR_FIT 18 +#define CYGNUM_HAL_VECTOR_WATCHDOG 19 +#define CYGNUM_HAL_VECTOR_DTLB_MISS 20 +#define CYGNUM_HAL_VECTOR_ITLB_MISS 21 +#define CYGNUM_HAL_VECTOR_DEBUG 22 +#define CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE 23 +#define CYGNUM_HAL_VECTOR_SPE_FP_DATA 24 +#define CYGNUM_HAL_VECTOR_SPE_FP_ROUND 25 + +#ifndef CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SPE_FP_ROUND +#endif + +#endif + + #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESERVED_0 #ifndef CYGNUM_HAL_VSR_MAX # define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST @@ -103,9 +129,25 @@ // Define decrementer as the first interrupt since it is guaranteed to // be defined on all PowerPCs. External may expand into several interrupts // depending on interrupt controller capabilities. + +#ifndef CYGHWR_HAL_POWERPC_BOOK_E + #define CYGNUM_HAL_INTERRUPT_DECREMENTER 0 #define CYGNUM_HAL_INTERRUPT_EXTERNAL 1 +#else + +// For Book E processors, in addition the the decrementer, there are +// also a fixed interval timer and a watchdog which can generate +// asynchronous interrupts. + +#define CYGNUM_HAL_INTERRUPT_DECREMENTER 0 +#define CYGNUM_HAL_INTERRUPT_INTERVAL 1 +#define CYGNUM_HAL_INTERRUPT_WATCHDOG 2 +#define CYGNUM_HAL_INTERRUPT_EXTERNAL 3 + +#endif + #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER #ifndef CYGNUM_HAL_ISR_MAX # define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL @@ -120,8 +162,7 @@ #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI -#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ - CYGNUM_HAL_VECTOR_ALIGNMENT +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE #define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A #define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B @@ -129,6 +170,22 @@ #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST +#ifdef CYGHWR_HAL_POWERPC_BOOK_E + +#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F +#define CYGNUM_HAL_EXCEPTION_CRITICAL_INPUT CYGNUM_HAL_VECTOR_CRITICAL_INPUT +#define CYGNUM_HAL_EXCEPTION_AP_UNAVAILABLE CYGNUM_HAL_VECTOR_AP_UNAVAILABLE +#define CYGNUM_HAL_EXCEPTION_FIT CYGNUM_HAL_VECTOR_FIT +#define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG +#define CYGNUM_HAL_EXCEPTION_DTLB_MISS CYGNUM_HAL_VECTOR_DTLB_MISS +#define CYGNUM_HAL_EXCEPTION_ITLB_MISS CYGNUM_HAL_VECTOR_ITLB_MISS +#define CYGNUM_HAL_EXCEPTION_DEBUG CYGNUM_HAL_VECTOR_DEBUG +#define CYGNUM_HAL_EXCEPTION_SPE_UNAVAILABLE CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE +#define CYGNUM_HAL_EXCEPTION_SPE_FP_DATA CYGNUM_HAL_VECTOR_SPE_FP_DATA +#define CYGNUM_HAL_EXCEPTION_SPE_FP_ROUND CYGNUM_HAL_VECTOR_SPE_FP_ROUND + +#endif + #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0 #ifndef CYGNUM_HAL_EXCEPTION_MAX #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX @@ -138,6 +195,7 @@ #endif // CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED +#ifndef CYGHWR_HAL_POWERPC_BOOK_E // FIXME: This is still rather ugly. Should probably be made variant // specific using a decode_hal_exception macro or somesuch. // decoded exception vectors @@ -148,7 +206,7 @@ #undef CYGNUM_HAL_EXCEPTION_MIN #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU - +#endif #define CYGNUM_HAL_EXCEPTION_COUNT \ ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) @@ -182,49 +240,58 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; //-------------------------------------------------------------------------- // Interrupt control macros +#if !defined(CYGHWR_HAL_POWERPC_BOOK_E) +#define CYGARC_REG_MSR_INTBITS CYGARC_REG_MSR_EE +#else +#define CYGARC_REG_MSR_INTBITS (CYGARC_REG_MSR_EE|CYGARC_REG_MSR_CE) +#endif + #define HAL_DISABLE_INTERRUPTS(_old_) \ CYG_MACRO_START \ - cyg_uint32 tmp1, tmp2; \ + cyg_uint32 tmp1 = ~CYGARC_REG_MSR_INTBITS; \ + cyg_uint32 tmp2; \ asm volatile ( \ "mfmsr %0;" \ "mr %2,%0;" \ - "li %1,0;" \ - "rlwimi %2,%1,0,16,16;" \ + "and %2,%2,%1;" \ "mtmsr %2;" \ - : "=r"(_old_), "=r" (tmp1), "=r" (tmp2)); \ + : "=r"(_old_), "+r" (tmp1), "=r" (tmp2)); \ CYG_MACRO_END -#define HAL_ENABLE_INTERRUPTS() \ - CYG_MACRO_START \ - cyg_uint32 tmp1, tmp2; \ - asm volatile ( \ - "mfmsr %0;" \ - "ori %1,%1,0x8000;" \ - "rlwimi %0,%1,0,16,16;" \ - "mtmsr %0;" \ - : "=r" (tmp1), "=r" (tmp2)); \ +#define HAL_ENABLE_INTERRUPTS() \ + CYG_MACRO_START \ + cyg_uint32 tmp1; \ + cyg_uint32 tmp2 = CYGARC_REG_MSR_INTBITS; \ + asm volatile ( \ + "mfmsr %0;" \ + "or %0,%0,%1;" \ + "mtmsr %0;" \ + : "=r" (tmp1), "+r" (tmp2)); \ CYG_MACRO_END -#define HAL_RESTORE_INTERRUPTS(_old_) \ - CYG_MACRO_START \ - cyg_uint32 tmp; \ - asm volatile ( \ - "mfmsr %0;" \ - "rlwimi %0,%1,0,16,16;" \ - "mtmsr %0;" \ - : "=&r" (tmp) \ - : "r" (_old_)); \ +#define HAL_RESTORE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + cyg_uint32 tmp1; \ + cyg_uint32 tmp2 = ~CYGARC_REG_MSR_INTBITS; \ + asm volatile ( \ + "mfmsr %0;" \ + "and %0,%0,%1;" \ + "not %1,%1;" \ + "and %1,%1,%2;" \ + "or %0,%0,%1;" \ + "mtmsr %0;" \ + : "=&r" (tmp1), "+r" (tmp2) \ + : "r" (_old_)); \ CYG_MACRO_END -#define HAL_QUERY_INTERRUPTS(_old_) \ - CYG_MACRO_START \ - cyg_uint32 tmp; \ - asm volatile ( \ - "mfmsr %0;" \ - "lis %1,0;" \ - "ori %1,%1,0x8000;" \ - "and %0,%0,%1;" \ - : "=&r"(_old_), "=r" (tmp)); \ +#define HAL_QUERY_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + cyg_uint32 tmp = CYGARC_REG_MSR_INTBITS; \ + asm volatile ( \ + "mfmsr %0;" \ + "and %0,%0,%1;" \ + : "=&r"(_old_) \ + : "r" (tmp)); \ CYG_MACRO_END //-------------------------------------------------------------------------- @@ -416,7 +483,7 @@ externC void cyg_hal_default_exception_v "mfdec %0;" \ : "=r"(result) \ ); \ - *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-result; \ + *(_pvalue_) = CYGNUM_HAL_RTC_PERIOD-result; \ CYG_MACRO_END #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
--- a/packages/hal/powerpc/arch/current/include/hal_io.h +++ b/packages/hal/powerpc/arch/current/include/hal_io.h @@ -11,7 +11,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2006 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -68,8 +68,17 @@ //----------------------------------------------------------------------------- // Enforce in-order IO for all HAL reads/writes using this macro. +#ifndef HAL_IO_BARRIER_DEFINED #define HAL_IO_BARRIER() \ asm volatile ( "eieio" : : : "memory" ) +#endif + +// Force memory writes to be flushed using this macro. This also +// invalidates the pipeline, in case those writes affect the pipeline +// (as with some flash drivers). +#ifndef HAL_MEMORY_BARRIER_DEFINED +#define HAL_MEMORY_BARRIER() __asm__ volatile ("sync ; isync " : : : "memory") +#endif //----------------------------------------------------------------------------- // IO Register address.
--- a/packages/hal/powerpc/arch/current/include/ppc_regs.h +++ b/packages/hal/powerpc/arch/current/include/ppc_regs.h @@ -11,7 +11,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -82,6 +82,7 @@ //-------------------------------------------------------------------------- // Some SPRs + #define CYGARC_REG_DSISR 18 #define CYGARC_REG_DAR 19 #define CYGARC_REG_DEC 22 @@ -108,6 +109,9 @@ //-------------------------------------------------------------------------- // MSR bits + +#if !defined(CYGHWR_HAL_POWERPC_BOOK_E) + #define CYGARC_REG_MSR_LE 0x00000001 // little-endian mode enable #define CYGARC_REG_MSR_RI 0x00000002 // recoverable exception #define CYGARC_REG_MSR_DR 0x00000010 // data address translation @@ -142,13 +146,69 @@ #define MSR_POW CYGARC_REG_MSR_POW #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#else + +// The MSR on BOOK E processors has some bits in common with the AIM +// architecture, but also has some differences. + +#define CYGARC_REG_MSR_PMM 0x00000004 // performance monitor mark +#define CYGARC_REG_MSR_DS 0x00000010 // data address space +#define CYGARC_REG_MSR_IS 0x00000020 // instruction address space +#define CYGARC_REG_MSR_FE1 0x00000100 // floating-point exception mode 1 +#define CYGARC_REG_MSR_DE 0x00000200 // debug interrupt enable +#define CYGARC_REG_MSR_UBLE 0x00000400 // User BTB lock enable (e +#define CYGARC_REG_MSR_FE0 0x00000800 // floating-point exception mode 0 +#define CYGARC_REG_MSR_ME 0x00001000 // machine check enable +#define CYGARC_REG_MSR_FP 0x00002000 // floating-point available +#define CYGARC_REG_MSR_PR 0x00004000 // privilege level +#define CYGARC_REG_MSR_EE 0x00008000 // external interrupt enable +#define CYGARC_REG_MSR_CE 0x00020000 // critical interrupt enable +#define CYGARC_REG_MSR_WE 0x00040000 // wait state enable +#define CYGARC_REG_MSR_SPE 0x02000000 // SPE enable +#define CYGARC_REG_MSR_UCLE 0x04000000 // user cache lock enable + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define MSR_PMM CYGARC_REG_MSR_PMM +#define MSR_DS CYGARC_REG_MSR_DS +#define MSR_IS CYGARC_REG_MSR_IS +#define MSR_FE1 CYGARC_REG_MSR_FE1 +#define MSR_DE CYGARC_REG_MSR_DE +#define MSR_UBLE CYGARC_REG_MSR_UBLE +#define MSR_FE0 CYGARC_REG_MSR_FE0 +#define MSR_ME CYGARC_REG_MSR_ME +#define MSR_FP CYGARC_REG_MSR_FP +#define MSR_PR CYGARC_REG_MSR_PR +#define MSR_EE CYGARC_REG_MSR_EE +#define MSR_CE CYGARC_REG_MSR_CE +#define MSR_WE CYGARC_REG_MSR_WE +#define MSR_SPE CYGARC_REG_MSR_SPE +#define MSR_UCLE CYGARC_REG_MSR_UCLE + +// The following bits are not defined by BOOK E processors. However +// they are referenced in the architecture HAL. By defining them as +// zero we neutralize their effect. +#define MSR_RI 0 +#define MSR_DR 0 +#define MSR_IR 0 + +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#endif + //-------------------------------------------------------------------------- // Time Base Registers -// READ and WRITE are different addresses! +// READ and WRITE are different addresses on some variants! + #define CYGARC_REG_TBL_W 284 #define CYGARC_REG_TBU_W 285 + +#if !defined(CYGHWR_HAL_POWERPC_BOOK_E) #define CYGARC_REG_TBL_R 268 #define CYGARC_REG_TBU_R 269 +#else +#define CYGARC_REG_TBL_R 284 +#define CYGARC_REG_TBU_R 285 +#endif #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS #define TBL_W CYGARC_REG_TBL_W @@ -157,6 +217,47 @@ #define TBU_R CYGARC_REG_TBU_R #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#if defined(CYGHWR_HAL_POWERPC_BOOK_E) + +#define CYGARC_REG_DECAR 54 +#define CYGARC_REG_TCR 340 +#define CYGARC_REG_TSR 336 + +#define CYGARC_REG_TCR_WP(__x) ((((__x)&3)<<30)|(((__x)&0x3C)<<15)) +#define CYGARC_REG_TCR_WRC_NONE (0<<28) +#define CYGARC_REG_TCR_WRC_CHECKSTOP (1<<28) +#define CYGARC_REG_TCR_WRC_RESET (2<<28) +#define CYGARC_REG_TCR_WIE (1<<27) +#define CYGARC_REG_TCR_DIE (1<<26) +#define CYGARC_REG_TCR_FP(__x) ((((__x)&3)<<24)|(((__x)&0x3C)<<11)) +#define CYGARC_REG_TCR_FIE (1<<23) +#define CYGARC_REG_TCR_ARE (1<<22) + + +#define CYGARC_REG_TSR_ENW (1<<31) +#define CYGARC_REG_TSR_WIS (1<<30) +#define CYGARC_REG_TSR_WRS_NONE (0<<28) +#define CYGARC_REG_TSR_WRS_CHECKSTOP (1<<28) +#define CYGARC_REG_TSR_WRS_RESET (2<<28) +#define CYGARC_REG_TSR_DIS (1<<27) +#define CYGARC_REG_TSR_FIS (1<<26) + +#endif + +//----------------------------------------------------------------------------- +// Exception Syndrome Register + +#if defined(CYGHWR_HAL_POWERPC_BOOK_E) + +#define CYGARC_REG_ESR 62 + +#define CYGARC_REG_ESR_PIL (1<<27) +#define CYGARC_REG_ESR_PPR (1<<26) +#define CYGARC_REG_ESR_PTR (1<<25) +#define CYGARC_REG_ESR_FP (1<<24) + +#endif + //----------------------------------------------------------------------------- #endif // ifdef CYGONCE_HAL_PPC_REGS_H // End of ppc_regs.h
--- a/packages/hal/powerpc/arch/current/include/ppc_stub.h +++ b/packages/hal/powerpc/arch/current/include/ppc_stub.h @@ -58,8 +58,29 @@ extern "C" { typedef unsigned long target_register_t; + +#ifndef CYGHWR_HAL_POWERPC_BOOK_E + +// Most PowerPCs use a standard register layout. + #define NUMREGS 71 - + +#define REGSIZE( _x_ ) (((_x_) >= F0 && (_x_) <= F31) ? 8 : 4) + +#else + +// BookE processors only have 70 registers, MQ is not supported. All +// registers are 32 bit and instead of FP registers there are the top +// 32 bits of the GPRs. The 64-bit registers are only used by SPE +// instructions, which we don't currently support. + +#define NUMREGS 70 + +#define REGSIZE( _x_ ) (4) + +#endif + + #ifdef CYGHWR_HAL_POWERPC_FPU // The PowerPC has floating point registers that are larger than what it // can hold in a target_register_t @@ -74,7 +95,6 @@ typedef unsigned long target_register_t; #define HAL_STUB_REGISTERS_SIZE ((sizeof(GDB_Registers) + sizeof(target_register_t) - 1)/sizeof(target_register_t)) #endif -#define REGSIZE( _x_ ) (((_x_) >= F0 && (_x_) <= F31) ? 8 : 4) enum regnames { R0, R1, R2, R3, R4, R5, R6, R7,
--- a/packages/hal/powerpc/arch/current/src/context.S +++ b/packages/hal/powerpc/arch/current/src/context.S @@ -197,7 +197,7 @@ FUNC_START(hal_thread_load_context) #endif lwz r3,CYGARC_PPCREG_MSR(sp) # merge interrupt state - hal_cpu_int_merge r3 + hal_cpu_int_merge r3,r2 lwz r0,CYGARC_PPCREG_REGS+0*4(sp) # R0 lwz r2,CYGARC_PPCREG_REGS+2*4(sp) # R2 = TOC
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -171,13 +171,14 @@ cyg_hal_exception_handler(HAL_SavedRegis #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ defined(CYGPKG_HAL_EXCEPTIONS) - int vector = regs->vector>>8; + int vector = regs->vector>>CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT; // We should decode the vector and pass a more appropriate // value as the second argument. For now we simply pass a // pointer to the saved registers. We should also divert // breakpoint and other debug vectors into the debug stubs. +#ifndef CYGHWR_HAL_POWERPC_BOOK_E if (vector==CYGNUM_HAL_VECTOR_PROGRAM) { int srr1; CYGARC_MFSPR(CYGARC_REG_SRR1, srr1); // get srr1 @@ -199,6 +200,8 @@ cyg_hal_exception_handler(HAL_SavedRegis CYG_FAIL("Unknown PROGRAM exception!!"); } } +#endif + cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs ); #else @@ -298,7 +301,9 @@ hal_MMU_init (void) externC void hal_enable_caches(void) { -#ifndef CYG_HAL_STARTUP_RAM +#ifndef HAL_UCACHE_ENABLE + +#if !(defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_JTAG)) // Invalidate caches HAL_DCACHE_INVALIDATE_ALL(); HAL_ICACHE_INVALIDATE_ALL(); @@ -324,6 +329,25 @@ hal_enable_caches(void) #endif #endif #endif + +#else // HAL_UCACHE_ENABLE + + +#if !(defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_JTAG)) + // Invalidate cache + HAL_UCACHE_INVALIDATE_ALL(); +#endif + + +#if defined(CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP) + + + HAL_UCACHE_ENABLE(); + +#endif + +#endif // HAL_UCACHE_ENABLE + } //---------------------------------------------------------------------------
--- a/packages/hal/powerpc/arch/current/src/hal_mk_defs.c +++ b/packages/hal/powerpc/arch/current/src/hal_mk_defs.c @@ -144,11 +144,17 @@ main(void) DEFINE(CYGARC_PPC_STACK_FRAME_SIZE, CYGARC_PPC_STACK_FRAME_SIZE); DEFINE(CYGARC_PPC_EXCEPTION_DECREMENT, sizeof(HAL_SavedRegisters)); - + // Some other exception related definitions DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT); DEFINE(CYGNUM_HAL_VECTOR_INTERRUPT, CYGNUM_HAL_VECTOR_INTERRUPT); DEFINE(CYGNUM_HAL_VECTOR_DECREMENTER, CYGNUM_HAL_VECTOR_DECREMENTER); +#ifdef CYGHWR_HAL_POWERPC_BOOK_E + DEFINE(CYGNUM_HAL_VECTOR_MACHINE_CHECK, CYGNUM_HAL_VECTOR_MACHINE_CHECK); + DEFINE(CYGNUM_HAL_VECTOR_FIT, CYGNUM_HAL_VECTOR_FIT); + DEFINE(CYGNUM_HAL_VECTOR_WATCHDOG, CYGNUM_HAL_VECTOR_WATCHDOG); + DEFINE(CYGNUM_HAL_VECTOR_CRITICAL_INPUT, CYGNUM_HAL_VECTOR_CRITICAL_INPUT); +#endif DEFINE(CYGNUM_HAL_VSR_MAX, CYGNUM_HAL_VSR_MAX); DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
--- a/packages/hal/powerpc/arch/current/src/ppc_stub.c +++ b/packages/hal/powerpc/arch/current/src/ppc_stub.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -106,6 +106,10 @@ int __computeSignal (unsigned int trap_n // The 40x is b0rken, returning 0 for these bits. Translate to // SIGTRAP to allow thread debugging. return SIGTRAP; +#elif defined(CYGHWR_HAL_POWERPC_BOOK_E) + // for Book E processor, we just translate all PROGRAM + // exceptions into SIGTRAP so that breakpoints work. + return SIGTRAP; #else // The register PS contains the value of SRR1 at the time of // exception entry. Bits 11-15 contain information about the @@ -190,7 +194,7 @@ int __get_trap_number (void) { // The vector is not not part of the GDB register set so get it // directly from the save context. - return _hal_registers->vector >> 8; + return _hal_registers->vector >> CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT; } /* Set the currently-saved pc register value to PC. This also updates NPC
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -8,7 +8,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -185,7 +185,7 @@ # Reset vector macro .macro reset_vector name - .p2align 8 + .p2align CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT .globl __exception_\name __exception_\name: #ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP @@ -201,7 +201,7 @@ # Generic vector macro .macro exception_vector name - .p2align 8 + .p2align CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT .globl __exception_\name __exception_\name: mtspr SPRG1,r3 # stash some work registers away @@ -209,7 +209,7 @@ mtspr SPRG3,r5 mfcr r4 # stash CR li r5,__exception_\name-rom_vectors # load low half of vector addr - srwi r5,r5,6 # shift right by 6 + srwi r5,r5,(CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT-2) # shift right by alignment-2 lwi r3,hal_vsr_table # table base lwzx r3,r3,r5 # address of vsr mflr r5 # save link register @@ -233,7 +233,7 @@ rom_vectors: # are always present. #ifdef CYG_HAL_RESERVED_VECTOR_00000 hal_reserved_vector_00000 -#else +#else exception_vector reserved_00000 #endif reset_vector reset @@ -252,6 +252,17 @@ rom_vectors: exception_vector floatingpoint_assist exception_vector reserved_00f00 +#if defined(CYGHWR_HAL_POWERPC_BOOK_E) + # Book E defines some extra vectors + exception_vector critical_input + exception_vector ap_unavailable + exception_vector interval_timer + exception_vector watchdog + exception_vector data_tlb_miss + exception_vector instruction_tlb_miss + exception_vector debug +#endif + # Variants may define extra vectors. hal_extra_vectors @@ -297,18 +308,8 @@ rom_vectors_end: .globl _hal_hardware_init_done _hal_hardware_init_done: -#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS - lwi r3,rom_vectors-4 - lwi r4,((CYGHWR_HAL_POWERPC_VECTOR_BASE)-4) - lwi r5,rom_vectors_end-4 - sub r5,r5,r3 # compute number of words to copy - srwi r5,r5,2 - mtctr r5 -0: lwzu r0,4(r3) - stwu r0,4(r4) - bdnz 0b -#endif - + hal_vectors_init + # set up stack lwi sp,__interrupt_stack mtspr SPRG0,sp # save in sprg0 for later use @@ -469,8 +470,16 @@ cyg_hal_default_exception_vsr: stw r4,CYGARC_PPCREG_CR(sp) # stash CR stw r5,CYGARC_PPCREG_LR(sp) # stash LR + # Save exception PC and MSR + mfsrr0 r3 + stw r3,CYGARC_PPCREG_PC(sp) + mfsrr1 r3 + stw r3,CYGARC_PPCREG_MSR(sp) + +cyg_hal_default_exception_vsr_common: + #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS - # Mark this fram as an Exception frame + # Mark this frame as an Exception frame lwi r3,0xDDDDDDE0 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) lwi r3,0xDDDDDDE1 @@ -511,13 +520,9 @@ cyg_hal_default_exception_vsr: # get remaining family CPU registers mfxer r3 mfctr r4 - mfsrr0 r5 - mfsrr1 r6 # and store them stw r3,CYGARC_PPCREG_XER(sp) stw r4,CYGARC_PPCREG_CTR(sp) - stw r5,CYGARC_PPCREG_PC(sp) - stw r6,CYGARC_PPCREG_MSR(sp) # Save variant registers hal_variant_save sp @@ -547,7 +552,48 @@ cyg_hal_default_exception_vsr: # When the call returns it will go to restore_state below. +#if defined(CYGHWR_HAL_POWERPC_BOOK_E) +##-------------------------------------------------------------------------- +## Critical exception handling code. +## +## Book E processors save the old PC and MSR in CSRR0/1 for certain +## exceptions. This VSR saves the values from these registers before +## branching to the common VSR code. + + .globl cyg_hal_default_critical_exception_vsr +cyg_hal_default_critical_exception_vsr: + + # We come here with all register containing their + # pre-exception values except: + # R3 = ls 16 bits of vector address + # R4 = saved CR + # R5 = saved LR + # LR = VSR address + # SPRG1 = old R3 + # SPRG2 = old R4 + # SPRG3 = old R5 + # CSRR0 = old PC + # CSRR1 = old MSR and the exception cause + subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT + # leave space for registers and + # a safety margin + + # First, save away some registers + stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector + stw r4,CYGARC_PPCREG_CR(sp) # stash CR + stw r5,CYGARC_PPCREG_LR(sp) # stash LR + + # Save exception PC and MSR + mfspr r3,58 + stw r3,CYGARC_PPCREG_PC(sp) + mfspr r3,59 + stw r3,CYGARC_PPCREG_MSR(sp) + + b cyg_hal_default_exception_vsr_common + +#endif + ##-------------------------------------------------------------------------- ## The following macros are defined depending on whether the Interrupt ## system is using isr tables or chaining, and depending on the interrupt @@ -616,8 +662,16 @@ cyg_hal_default_interrupt_vsr: stw r4,CYGARC_PPCREG_CR(sp) # stash CR stw r5,CYGARC_PPCREG_LR(sp) # stash LR + # Save exception PC and MSR + mfsrr0 r3 + stw r3,CYGARC_PPCREG_PC(sp) + mfsrr1 r3 + stw r3,CYGARC_PPCREG_MSR(sp) + +cyg_hal_default_interrupt_vsr_common: + #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS - # Mark this fram as an 1nterrupt frame + # Mark this frame as an interrupt frame lwi r3,0xDDDDDD10 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) lwi r3,0xDDDDDD11 @@ -658,14 +712,10 @@ cyg_hal_default_interrupt_vsr: # get remaining family CPU registers mfxer r3 mfctr r4 - mfsrr0 r5 - mfsrr1 r6 # and store them stw r3,CYGARC_PPCREG_XER(sp) stw r4,CYGARC_PPCREG_CTR(sp) - stw r5,CYGARC_PPCREG_PC(sp) - stw r6,CYGARC_PPCREG_MSR(sp) # Save variant registers hal_variant_save sp @@ -869,8 +919,48 @@ restore_state: isync rfi # and return +#if defined(CYGHWR_HAL_POWERPC_BOOK_E) +##--------------------------------------------------------------------------- +## Critical interrupt handling code. +## +## Book E processors save the old PC and MSR in CSRR0/1 for certain +## exceptions. This VSR saves the values from these registers before +## branching to the common VSR code. + + .globl cyg_hal_default_interrupt_vsr +cyg_hal_default_critical_interrupt_vsr: + + # We come here with all register containing their + # pre-exception values except: + # R3 = ls 16 bits of vector address + # R4 = saved CR + # R5 = saved LR + # LR = VSR address + # SPRG1 = old R3 + # SPRG2 = old R4 + # SPRG3 = old R5 + # CSRR0 = old PC + # CSRR1 = old MSR + subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT + # leave space for registers and + # a safety margin + + stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector + stw r4,CYGARC_PPCREG_CR(sp) # stash CR + stw r5,CYGARC_PPCREG_LR(sp) # stash LR + + # Save exception PC and MSR + mfspr r3,58 # Get CSSR0 + stw r3,CYGARC_PPCREG_PC(sp) + mfspr r3,59 # Get CSSR1 + stw r3,CYGARC_PPCREG_MSR(sp) + + b cyg_hal_default_interrupt_vsr_common + +#endif + ##----------------------------------------------------------------------------- ## Execute pending DSRs on the interrupt stack with interrupts enabled. ## Note: this can only be called from code running on a thread stack @@ -906,7 +996,7 @@ FUNC_START(hal_interrupt_stack_call_pend mtlr r3 lwz r5,12(sp) # get SP from saved state lwz r3,16(sp) # restore interrupt setting - hal_cpu_int_merge r3 + hal_cpu_int_merge r3,r4 mr sp,r5 # restore stack pointer blr # and return to caller