Mercurial > ecos
annotate packages/hal/powerpc/cogent/current/src/cogent.S @ 3292:7f8e529b4d82 default tip
Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
| author | vae |
|---|---|
| date | Wed, 29 Apr 2015 23:31:48 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
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| 0 | 1 ##============================================================================= |
| 2 ## | |
| 3 ## cogent.S | |
| 4 ## | |
| 5 ## Cogent board hardware setup | |
| 6 ## | |
| 7 ##============================================================================= | |
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8 ## ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 ## ------------------------------------------- |
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10 ## This file is part of eCos, the Embedded Configurable Operating System. |
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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12 ## |
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13 ## eCos is free software; you can redistribute it and/or modify it under |
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14 ## the terms of the GNU General Public License as published by the Free |
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15 ## Software Foundation; either version 2 or (at your option) any later |
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16 ## version. |
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17 ## |
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 ## for more details. |
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22 ## |
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23 ## You should have received a copy of the GNU General Public License |
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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26 ## |
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27 ## As a special exception, if other files instantiate templates or use |
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28 ## macros or inline functions from this file, or you compile this file |
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29 ## and link it with other works to produce a work based on this file, |
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30 ## this file does not by itself cause the resulting work to be covered by |
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31 ## the GNU General Public License. However the source code for this file |
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32 ## must still be made available in accordance with section (3) of the GNU |
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33 ## General Public License v2. |
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34 ## |
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35 ## This exception does not invalidate any other reasons why a work based |
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36 ## on this file might be covered by the GNU General Public License. |
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37 ## ------------------------------------------- |
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38 ## ####ECOSGPLCOPYRIGHTEND#### |
| 0 | 39 ##============================================================================= |
| 40 #######DESCRIPTIONBEGIN#### | |
| 41 ## | |
| 42 ## Author(s): nickg | |
| 43 ## Contributors: nickg | |
| 44 ## Date: 1997-11-11 | |
| 45 ## Purpose: Cogent board hardware setup | |
| 46 ## Description: This file contains any code needed to initialize the | |
| 47 ## hardware on a Cogent PowerPC board. | |
| 48 ## | |
| 49 ######DESCRIPTIONEND#### | |
| 50 ## | |
| 51 ##============================================================================= | |
| 52 | |
| 53 #include <pkgconf/hal.h> | |
| 54 | |
| 2 | 55 #include <cyg/hal/ppc_regs.h> |
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56 #include <cyg/hal/arch.inc> |
| 0 | 57 |
| 58 #------------------------------------------------------------------------------ | |
| 59 | |
| 60 .globl hal_hardware_init | |
| 61 hal_hardware_init: | |
| 62 | |
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63 #if defined(CYGPKG_HAL_POWERPC_COGENT) && defined(CYGPKG_HAL_POWERPC_MPC8xx) |
| 0 | 64 |
| 2 | 65 # Set up MPC8xx mapping registers for cogent |
| 66 | |
| 67 lwi r3,CYGARC_REG_IMM_BASE # base address of control registers | |
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68 mtspr CYGARC_REG_IMMR,r3 |
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69 |
| 2 | 70 # Set timebase divisor to busclock/16, pitrtc divisor to 512. |
| 71 lwz r4,(CYGARC_REG_IMM_SCCR - CYGARC_REG_IMM_BASE)(r3) | |
| 72 lwi r5,(CYGARC_REG_IMM_SCCR_RTDIV | CYGARC_REG_IMM_SCCR_RTSEL | CYGARC_REG_IMM_SCCR_TBS) | |
| 73 or r4,r4,r5 | |
| 74 stw r4,(CYGARC_REG_IMM_SCCR - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 75 |
| 2 | 76 # Enable TimeBase |
| 77 li r4,CYGARC_REG_IMM_TBSCR_TBE | |
| 78 sth r4,(CYGARC_REG_IMM_TBSCR - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 79 |
| 2 | 80 # Note: I do not know if the timeout is correct/optimal. |
| 81 # Works with the above memory mappings/wait states and | |
| 82 # the PromICE. | |
| 83 # Disable watchdog, enable bus monitor, timeout after 255*8 cycles | |
| 84 lwi r4,(CYGARC_REG_IMM_SYPCR_BMT_MASK | CYGARC_REG_IMM_SYPCR_BME) | |
| 85 stw r4,(CYGARC_REG_IMM_SYPCR - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 86 |
| 87 # Set CS0 to | |
| 88 # base addr 0xfff00000 | |
| 89 # wait states 4 | |
| 90 # size 1M | |
| 91 # Covers ROM | |
| 2 | 92 # Note: After a reset code is currently executing via the default |
| 93 # mapping defined in bank 0. This bank must remain valid while | |
| 94 # it is being configured. | |
| 95 lwi r4,(0xfff00000 | CYGARC_REG_IMM_BR_PS_16 | CYGARC_REG_IMM_BR_V) | |
| 96 stw r4,(CYGARC_REG_IMM_BR0 - CYGARC_REG_IMM_BASE)(r3) | |
| 97 lwi r4,(0xfff00000 | CYGARC_REG_IMM_OR_BI | 4 << CYGARC_REG_IMM_OR_SCY_SHIFT) | |
| 98 stw r4,(CYGARC_REG_IMM_OR0 - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 99 |
| 100 # Set CS1 to | |
| 101 # base addr 0x00000000 | |
| 102 # external ACK | |
| 103 # size 64M | |
| 104 # Covers DRAM and slot0 | |
| 2 | 105 lwi r4,(0xfc000000 | CYGARC_REG_IMM_OR_SETA) |
| 106 stw r4,(CYGARC_REG_IMM_OR1 - CYGARC_REG_IMM_BASE)(r3) | |
| 107 lwi r4,(0x00000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V) | |
| 108 stw r4,(CYGARC_REG_IMM_BR1 - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 109 |
| 110 # Set CS2 to | |
| 111 # base addr 0x04000000 | |
| 112 # external ACK | |
| 113 # size 64M | |
| 114 # slot1 and slot2 | |
| 2 | 115 lwi r4,(0xfc000000 | CYGARC_REG_IMM_OR_SETA) |
| 116 stw r4,(CYGARC_REG_IMM_OR2 - CYGARC_REG_IMM_BASE)(r3) | |
| 117 lwi r4,(0x04000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V) | |
| 118 stw r4,(CYGARC_REG_IMM_BR2 - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 119 |
| 120 # Set CS3 to | |
| 121 # base addr 0x0e000000 | |
| 122 # exernal ack | |
| 123 # size 32M | |
| 124 # covers IO registers | |
| 2 | 125 lwi r4,(0xfe000000 | CYGARC_REG_IMM_OR_BI | CYGARC_REG_IMM_OR_SETA) |
| 126 stw r4,(CYGARC_REG_IMM_OR3 - CYGARC_REG_IMM_BASE)(r3) | |
| 127 lwi r4,(0x0e000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V) | |
| 128 stw r4,(CYGARC_REG_IMM_BR3 - CYGARC_REG_IMM_BASE)(r3) | |
| 0 | 129 |
| 130 #endif | |
| 131 | |
| 2 | 132 sync |
| 0 | 133 blr |
| 134 | |
| 135 #------------------------------------------------------------------------------ | |
| 136 # end of cogent.S |
