Mercurial > ecos
changeset 68:f74b2666b30d ecos-sw-2000-02-04
Merge from eCos master repository on 2000-02-04-07:47:04-GMT
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--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * include/pkgconf/hal.h: CYG_HAL_POWERPC_x->CYGPKG_... + 1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/pkgconf/hal.h: Rename all CYG_HAL_USE_ROM_MONITOR_GDB_STUBS
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -499,23 +499,23 @@ * * NOTE: Currently the code also needs these #defines. */ -#ifdef CYG_HAL_POWERPC_COGENT -# define CYG_HAL_POWERPC_MPC8xx -# define CYG_HAL_POWERPC_MPC860 -# undef CYG_HAL_POWERPC_MPC850 -# undef CYG_HAL_POWERPC_MPC823 +#ifdef CYGPKG_HAL_POWERPC_COGENT +# define CYGPKG_HAL_POWERPC_MPC8xx +# define CYGPKG_HAL_POWERPC_MPC860 +# undef CYGPKG_HAL_POWERPC_MPC850 +# undef CYGPKG_HAL_POWERPC_MPC823 #endif -#ifdef CYG_HAL_POWERPC_FADS -# define CYG_HAL_POWERPC_MPC8xx -# define CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_FADS +# define CYGPKG_HAL_POWERPC_MPC8xx +# define CYGPKG_HAL_POWERPC_MPC860 #endif -#ifdef CYG_HAL_POWERPC_MBX -# define CYG_HAL_POWERPC_MPC8xx -# define CYG_HAL_POWERPC_MPC860 -# define CYG_HAL_POWERPC_COPY_VECTORS +#ifdef CYGPKG_HAL_POWERPC_MBX +# define CYGPKG_HAL_POWERPC_MPC8xx +# define CYGPKG_HAL_POWERPC_MPC860 +# define CYGSEM_HAL_POWERPC_COPY_VECTORS #endif -#ifdef CYG_HAL_POWERPC_SIM -# define CYG_HAL_POWERPC_MPC603 +#ifdef CYGPKG_HAL_POWERPC_SIM +# define CYGPKG_HAL_POWERPC_MPC603 #endif #include CYGBLD_HAL_TARGET_H
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,17 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * tests/intr0.c: + * tests/PKGconf.mak: + * include/hal_cache.h: + * include/hal_intr.h: + * include/ppc_regs.h: + * include/ppc.inc: + * src/hal_intr.c: + * src/hal_misc.c: + * src/ppc_stub.c: + * src/vectors.S: + CYG_HAL_POWERPC_x->CYGPKG_... + 2000-01-26 Jesper Skov <jskov@redhat.com> * include/hal_cache.h: Include plf_cache.h
--- a/packages/hal/powerpc/arch/current/include/hal_cache.h +++ b/packages/hal/powerpc/arch/current/include/hal_cache.h @@ -94,7 +94,7 @@ externC cyg_memdesc_t cyg_hal_mem_map[]; //============================================================================= // PowerPC simulator -#ifdef CYG_HAL_POWERPC_SIM +#ifdef CYGPKG_HAL_POWERPC_SIM //----------------------------------------------------------------------------- // Cache dimensions @@ -224,12 +224,12 @@ externC cyg_memdesc_t cyg_hal_mem_map[]; //============================================================================= // Motorola MPC8xx -#elif defined(CYG_HAL_POWERPC_MPC8xx) +#elif defined(CYGPKG_HAL_POWERPC_MPC8xx) //----------------------------------------------------------------------------- // Cache dimensions -#if defined(CYG_HAL_POWERPC_MPC860) +#if defined(CYGPKG_HAL_POWERPC_MPC860) // Data cache #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line @@ -239,9 +239,9 @@ externC cyg_memdesc_t cyg_hal_mem_map[]; #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line #define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYG_HAL_POWERPC_MPC860) +#endif // defined(CYGPKG_HAL_POWERPC_MPC860) -#if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) +#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) // Data cache #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line @@ -251,7 +251,7 @@ externC cyg_memdesc_t cyg_hal_mem_map[]; #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line #define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) +#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
--- a/packages/hal/powerpc/arch/current/include/hal_intr.h +++ b/packages/hal/powerpc/arch/current/include/hal_intr.h @@ -100,7 +100,7 @@ #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 // The MPC860 does not generate DSI and ISI: instead it goes to machine // check, so that a software VM system can then call into vectors 0x300 or // 0x400 if the address is truly invalid rather than merely not in the TLB @@ -115,7 +115,7 @@ #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI -#endif // !CYG_HAL_POWERPC_MPC860 : DSI and ISI exceptions generated +#endif // !CYGPKG_HAL_POWERPC_MPC860 : DSI and ISI exceptions generated #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ CYGNUM_HAL_VECTOR_ALIGNMENT @@ -138,7 +138,7 @@ ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // Additional exceptions on the MPC8xx #define CYGNUM_HAL_VECTOR_RESERVED_F 15 #define CYGNUM_HAL_VECTOR_SW_EMUL 16 @@ -421,7 +421,7 @@ externC void hal_interrupt_stack_call_pe //-------------------------------------------------------------------------- // Interrupt controller access -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 // FIXME: Should probably be put in a separate .inl file?!? @@ -893,7 +893,7 @@ cyg_hal_interrupt_set_level ( cyg_uint32 //-------------------------------------------------------------------------- // Interrupt arbiters -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data); @@ -904,7 +904,7 @@ externC cyg_uint32 hal_arbitration_isr_r externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, CYG_ADDRWORD data); -#endif // ifdef CYG_HAL_POWERPC_MPC860 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 //-------------------------------------------------------------------------- // Clock control
--- a/packages/hal/powerpc/arch/current/include/ppc.inc +++ b/packages/hal/powerpc/arch/current/include/ppc.inc @@ -93,7 +93,7 @@ ori \reg,\reg,\val@L .endm -#ifdef CYG_HAL_POWERPC_MPC603 +#ifdef CYGPKG_HAL_POWERPC_MPC603 # Move from HID0 hw control register .macro mfhid0 reg mfspr \reg,HID0
--- a/packages/hal/powerpc/arch/current/include/ppc_regs.h +++ b/packages/hal/powerpc/arch/current/include/ppc_regs.h @@ -134,7 +134,7 @@ //-------------------------------------------------------------------------- // MPC603 Specific Definitions //-------------------------------------------------------------------------- -#ifdef CYG_HAL_POWERPC_MPC603 +#ifdef CYGPKG_HAL_POWERPC_MPC603 //-------------------------------------------------------------------------- // Cache @@ -182,12 +182,12 @@ #define LBAT_PP_RW 0x00000002 // read/write #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#endif // ifdef CYG_HAL_POWERPC_MPC603 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC603 //-------------------------------------------------------------------------- // MPC8xx Generic Definitions //-------------------------------------------------------------------------- -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx //-------------------------------------------------------------------------- // Instruction cache control. @@ -475,6 +475,6 @@ #define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#endif // ifdef CYG_HAL_POWERPC_MPC8xx +#endif // ifdef CYGPKG_HAL_POWERPC_MPC8xx #endif // ifdef CYGONCE_HAL_PPC_REGS_H
--- a/packages/hal/powerpc/arch/current/src/hal_intr.c +++ b/packages/hal/powerpc/arch/current/src/hal_intr.c @@ -87,7 +87,7 @@ hal_call_isr (cyg_uint32 vector) } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 // Since the interrupt sources do not have fixed vectors on the 860 // SIU, some arbitration is required. @@ -236,7 +236,7 @@ hal_IRQ_init(void) HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM, 7); HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM); } -#else // ifdef CYG_HAL_POWERPC_MPC860 +#else // ifdef CYGPKG_HAL_POWERPC_MPC860 externC void hal_IRQ_init(void) @@ -244,7 +244,7 @@ hal_IRQ_init(void) // Nothing special } -#endif // ifdef CYG_HAL_POWERPC_MPC860 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 // ------------------------------------------------------------------------- // EOF hal_intr.c
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -229,7 +229,7 @@ void hal_idle_thread_action( cyg_uint32 count ) { #if 0 -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 register cyg_uint32 result; cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ; @@ -256,7 +256,7 @@ static int hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, cyg_int32 size, cyg_uint8 flags) { -#ifdef CYG_HAL_POWERPC_MPC603 +#ifdef CYGPKG_HAL_POWERPC_MPC603 { // Use BATs to map the memory. cyg_uint32 ubat, lbat; @@ -312,7 +312,7 @@ hal_map_memory (int id,CYG_ADDRESS virt, #endif -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx { // The MPC8xx CPUs do not have BATs. Fortunately we don't // currently use the MMU, so we can simulate BATs by using the @@ -321,11 +321,11 @@ hal_map_memory (int id,CYG_ADDRESS virt, cyg_uint32 epn, rpn, ctr, twc; int max_tlbs; -#if defined(CYG_HAL_POWERPC_MPC860) +#if defined(CYGPKG_HAL_POWERPC_MPC860) // There are 32 TLBs. max_tlbs = 32; #endif -#if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) +#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) // There are 8 TLBs. max_tlbs = 8; #endif @@ -381,7 +381,7 @@ hal_map_memory (int id,CYG_ADDRESS virt, static void hal_clear_MMU (void) { -#ifdef CYG_HAL_POWERPC_MPC603 +#ifdef CYGPKG_HAL_POWERPC_MPC603 { cyg_uint32 ubat, lbat; @@ -408,7 +408,7 @@ hal_clear_MMU (void) } #endif -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx { // Initialize TLBs with 0, Valid bits unset. @@ -416,11 +416,11 @@ hal_clear_MMU (void) int id; int max_tlbs; -#if defined(CYG_HAL_POWERPC_MPC860) +#if defined(CYGPKG_HAL_POWERPC_MPC860) // There are 32 TLBs. max_tlbs = 32; #endif -#if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) +#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) // There are 8 TLBs. max_tlbs = 8; #endif @@ -488,7 +488,7 @@ hal_enable_caches(void) #endif #endif -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // Disable serialization { cyg_uint32 ictrl;
--- a/packages/hal/powerpc/arch/current/src/ppc_stub.c +++ b/packages/hal/powerpc/arch/current/src/ppc_stub.c @@ -119,7 +119,7 @@ int __computeSignal (unsigned int trap_n /* System call */ return SIGSYS; -#if defined(CYG_HAL_POWERPC_MPC8xx) +#if defined(CYGPKG_HAL_POWERPC_MPC8xx) case CYGNUM_HAL_VECTOR_SW_EMUL: /* A SW_EMUL is generated instead of PROGRAM for illegal instructions. */ @@ -144,7 +144,7 @@ int __computeSignal (unsigned int trap_n case CYGNUM_HAL_VECTOR_DTLB_ERROR: /* Invalid data access. */ return SIGSEGV; -#endif // defined(CYG_HAL_POWERPC_MPC8xx) +#endif // defined(CYGPKG_HAL_POWERPC_MPC8xx) default: return SIGTERM;
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -78,7 +78,7 @@ #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) -# ifdef CYG_HAL_POWERPC_COPY_VECTORS +# ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS # define CYG_MSR CYG_MSR_COMMON # else # define CYG_MSR (CYG_MSR_COMMON | MSR_IP) @@ -87,7 +87,7 @@ #ifdef CYG_HAL_STARTUP_RAM #define CYG_MSR CYG_MSR_COMMON #endif -#ifdef CYG_HAL_POWERPC_SIM +#ifdef CYGPKG_HAL_POWERPC_SIM # When building for SIM, don~t enable MMU -- it~s not needed since caches # are disabled, and there is a runtime simulation overhead. #undef CYG_MSR @@ -207,7 +207,7 @@ reset_vector: # There are some additional vectors defined # on various implementations. -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx # MPC8xx vectors exception_vector software_emu @@ -241,7 +241,7 @@ rom_vectors_end: # Initialize CPU bl _init_CPU -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx # Disable special MPC8xx "development support" which # suppresses trace exceptions. The CPU seems to hang, not # executing from offset 0x1e00(?) as expected. @@ -292,9 +292,9 @@ 2: #endif -#ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup +#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup -#ifdef CYG_HAL_POWERPC_MBX +#ifdef CYGPKG_HAL_POWERPC_MBX # define CYGPRI_STUBROM_HAS_RAM_VECTORS #endif @@ -520,7 +520,7 @@ 9: ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx ## First level decoding of MPC8xx SIU interrupt controller. @@ -689,7 +689,7 @@ 1: #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx # The CPM controller allows nested interrupts. However, # it sits on the back of the SIU controller which has no # HW support for this. In effect, SW masking of lower @@ -894,7 +894,7 @@ FUNC_START(hal_interrupt_stack_call_pend #--------------------------------------------------------------------------- # Code for putting the CPU in a post-reset state; disabling MMU and caches. _init_CPU: -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx lwi r3,CYGARC_REG_DC_CMD_CD sync mtspr CYGARC_REG_DC_CST,r3 @@ -943,7 +943,7 @@ hal_vsr_table: .long __default_exception_vsr # floating point assist .long __default_exception_vsr # reserved 0x0f00 -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx # Implementation defined vectors .long __default_exception_vsr # software emulation
--- a/packages/hal/powerpc/arch/current/tests/intr0.c +++ b/packages/hal/powerpc/arch/current/tests/intr0.c @@ -53,7 +53,7 @@ extern diag_printf( char *format, ... ); #include <cyg/infra/testcase.h> -#if defined(CYG_HAL_POWERPC_MPC860) +#if defined(CYGPKG_HAL_POWERPC_MPC860) #undef CHECK(b) #define CHECK(b) CYG_TEST_CHECK(b,#b) @@ -66,7 +66,7 @@ extern diag_printf( char *format, ... ); // interrupt handlers. #define PIT_PERIOD 5000 -#ifdef CYG_HAL_POWERPC_MBX +#ifdef CYGPKG_HAL_POWERPC_MBX #define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS #else #define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors @@ -284,7 +284,7 @@ cyg_start( void ) intr0_main(); } -#else // ifdef CYG_HAL_POWERPC_MPC860 +#else // ifdef CYGPKG_HAL_POWERPC_MPC860 externC void cyg_start( void ) @@ -293,6 +293,6 @@ cyg_start( void ) CYG_TEST_PASS_FINISH("N/A: Not a MPC860"); } -#endif // ifdef CYG_HAL_POWERPC_MPC860 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 // EOF intr0.c
--- a/packages/hal/powerpc/cogent/current/ChangeLog +++ b/packages/hal/powerpc/cogent/current/ChangeLog @@ -1,3 +1,9 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + * src/cma_ser.inl: + * src/cogent.S: + * src/hal_diag.c: + CYG_HAL_POWERPC_x->CYGPKG_... + 2000-01-26 Jesper Skov <jskov@redhat.com> * include/plf_cache.h: Added.
--- a/packages/hal/powerpc/cogent/current/src/cma_ser.inl +++ b/packages/hal/powerpc/cogent/current/src/cma_ser.inl @@ -212,7 +212,7 @@ CYG_CMA_PUBLIC void NC(init_serial)( voi cyg_uint8 lcr; // Disable interrupts. -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ1); #else #error "Not supported on CPU" @@ -297,7 +297,7 @@ CYG_CMA_PUBLIC void NC(put_char)( int c int NC(interruptible)( int state ) { int vector; -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // Serial interrupts are feed to IRQ1 on the 8xx CPUs. vector = CYGNUM_HAL_INTERRUPT_SIU_IRQ1; #else @@ -332,7 +332,7 @@ int cyg_hal_gdb_isr( target_register_t p cyg_uint8 vec; int break_irq = 0; -#ifdef CYG_HAL_POWERPC_MPC8xx +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // Serial interrupts are feed to IRQ1 (vector 0x08) on the Cogent // board. HAL_READ_UINT8(CYGARC_REG_IMM_SIVEC, vec);
--- a/packages/hal/powerpc/cogent/current/src/cogent.S +++ b/packages/hal/powerpc/cogent/current/src/cogent.S @@ -52,7 +52,7 @@ .globl hal_hardware_init hal_hardware_init: -#if defined(CYG_HAL_POWERPC_COGENT) && defined(CYG_HAL_POWERPC_MPC8xx) +#if defined(CYGPKG_HAL_POWERPC_COGENT) && defined(CYGPKG_HAL_POWERPC_MPC8xx) # Set up MPC8xx mapping registers for cogent
--- a/packages/hal/powerpc/cogent/current/src/hal_diag.c +++ b/packages/hal/powerpc/cogent/current/src/hal_diag.c @@ -388,7 +388,7 @@ void hal_diag_read_char(char* c) {} #if defined(CYG_KERNEL_DIAG_ROMART) -#ifdef CYG_HAL_POWERPC_COGENT +#ifdef CYGPKG_HAL_POWERPC_COGENT #define PROMICE_AILOC 0xfff00020 #endif
--- a/packages/hal/powerpc/fads/current/ChangeLog +++ b/packages/hal/powerpc/fads/current/ChangeLog @@ -1,3 +1,8 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/fads.S: + CYG_HAL_POWERPC_x->CYGPKG_... + 2000-01-26 Jesper Skov <jskov@redhat.com> * include/plf_cache.h: Added.
--- a/packages/hal/powerpc/fads/current/src/fads.S +++ b/packages/hal/powerpc/fads/current/src/fads.S @@ -73,7 +73,7 @@ .globl hal_hardware_init hal_hardware_init: -#if defined(CYGPKG_HAL_POWERPC_FADS) && defined(CYG_HAL_POWERPC_MP860) +#if defined(CYGPKG_HAL_POWERPC_FADS) && defined(CYGPKG_HAL_POWERPC_MP860) # kevinh disabled - we use the values which have already been setup # by the mpc8bug
--- a/packages/hal/powerpc/quicc/current/ChangeLog +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/quicc_smc1.c: CYG_HAL_POWERPC_x->CYGPKG_... + 1999-09-02 Gary Thomas <gthomas@cygnus.co.uk> * src/quicc_smc1.c (init_smc1_uart): Generalize baud rate computation.
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c +++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c @@ -48,7 +48,7 @@ #include <cyg/infra/cyg_type.h> #include <cyg/hal/hal_cache.h> -#ifdef CYG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC860 // eCos headers decribing PowerQUICC: #include <cyg/hal/quicc/ppc8xx.h> @@ -365,5 +365,5 @@ int cyg_hal_gdb_isr( target_register_t p } #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT -#endif // CYG_HAL_POWERPC_MPC860 +#endif // CYGPKG_HAL_POWERPC_MPC860 // EOF quicc_smc1.c
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + 2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper
--- a/packages/io/serial/current/src/powerpc/quicc_smc_serial.c +++ b/packages/io/serial/current/src/powerpc/quicc_smc_serial.c @@ -408,7 +408,7 @@ quicc_smc_serial_init(struct cyg_devtab_ ); TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8; #else -#ifdef CYG_HAL_POWERPC_MBX +#ifdef CYGPKG_HAL_POWERPC_MBX // Ensure the SMC1 side is initialized first and use shared mem // above where it plays: diag_init(); // (pull in constructor that inits diag channel)
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,7 @@ +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/sched/lottery.cxx (schedule): CYG_HAL_POWERPC_x->CYGPKG_... + 2000-02-01 Jonathan Larmour <jlarmour@redhat.co.uk> * tests/tm_basic.cxx (NTEST_THREADS): Reduce further to fit on small
--- a/packages/kernel/current/src/sched/lottery.cxx +++ b/packages/kernel/current/src/sched/lottery.cxx @@ -94,7 +94,7 @@ Cyg_Thread *Cyg_Scheduler_Implementation { CYG_REPORT_FUNCTION(); -#ifdef CYG_HAL_POWERPC +#ifdef CYGPKG_HAL_POWERPC // PowerPc specific version of random number generator. register cyg_int32 r1 asm("r4");