ecos: packages/hal/powerpc/ppc60x/current/include/var

annotate packages/hal/powerpc/ppc60x/current/include/var_cache.h @ 3292:7f8e529b4d82 default tip

Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.

author	vae
date	Wed, 29 Apr 2015 23:31:48 +0000
parents	74dbf4c3f2e1
children

rev	line source
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	1 #ifndef CYGONCE_VAR_CACHE_H
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	2 #define CYGONCE_VAR_CACHE_H
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	3 //=============================================================================
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	4 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	5 // var_cache.h
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	6 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	7 // Variant HAL cache control API
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	8 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	9 //=============================================================================
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	10 // ####ECOSGPLCOPYRIGHTBEGIN####
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	11 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	12 // This file is part of eCos, the Embedded Configurable Operating System.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	13 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 70 diff changeset	14 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	15 // eCos is free software; you can redistribute it and/or modify it under
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	16 // the terms of the GNU General Public License as published by the Free
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	17 // Software Foundation; either version 2 or (at your option) any later
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	18 // version.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 70 diff changeset	19 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	20 // eCos is distributed in the hope that it will be useful, but WITHOUT
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	23 // for more details.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 70 diff changeset	24 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	25 // You should have received a copy of the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	26 // along with eCos; if not, write to the Free Software Foundation, Inc.,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 70 diff changeset	28 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	29 // As a special exception, if other files instantiate templates or use
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	30 // macros or inline functions from this file, or you compile this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	31 // and link it with other works to produce a work based on this file,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	32 // this file does not by itself cause the resulting work to be covered by
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	33 // the GNU General Public License. However the source code for this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	34 // must still be made available in accordance with section (3) of the GNU
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	35 // General Public License v2.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 70 diff changeset	36 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	37 // This exception does not invalidate any other reasons why a work based
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	38 // on this file might be covered by the GNU General Public License.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	39 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 901 diff changeset	40 // ####ECOSGPLCOPYRIGHTEND####
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	41 //=============================================================================
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	42 //#####DESCRIPTIONBEGIN####
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	43 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	44 // Author(s): nickg
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	45 // Contributors:nickg, jskov, gthomas
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	46 // Date: 2000-04-02
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	47 // Purpose: Variant cache control API
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	48 // Description: The macros defined here provide the HAL APIs for handling
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	49 // cache control operations on the PPC60x variant CPUs.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	50 // Usage: Is included via the architecture cache header:
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	51 // #include <cyg/hal/hal_cache.h>
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	52 // ...
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	53 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	54 //####DESCRIPTIONEND####
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	55 //
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	56 //=============================================================================
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	57
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	58 #include <pkgconf/hal.h>
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	59 #include <cyg/infra/cyg_type.h>
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	60
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	61 #include <cyg/hal/ppc_regs.h>
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	62 #include <cyg/hal/plf_cache.h>
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	63
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	64
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	65 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	66 // Cache dimensions
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	67
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	68 // Data cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	69 #ifndef HAL_DCACHE_SIZE
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	70 #define HAL_DCACHE_SIZE 16384 // Size of data cache in bytes
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	71 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	72 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	73 #endif
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	74
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	75 // Instruction cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	76 #ifndef HAL_ICACHE_SIZE
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	77 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	78 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	79 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	80 #endif
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	81
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	82 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	83 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	84
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	85 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	86 // Global control of data cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	87
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	88 // Enable the data cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	89 #define HAL_DCACHE_ENABLE() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	90 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	91 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	92 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	93 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	94 "or %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	95 "mtspr %1,%0" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	96 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	97 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	98 "r" (_HID0_DCE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	99 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	100 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	101
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	102 // Disable the data cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	103 #define HAL_DCACHE_DISABLE() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	104 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	105 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	106 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	107 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	108 "andc %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	109 "mtspr %1,%0" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	110 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	111 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	112 "r" (_HID0_DCE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	113 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	114 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	115
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	116 // Invalidate the entire cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	117 #define HAL_DCACHE_INVALIDATE_ALL() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	118 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	119 cyg_int32 _scr1, _scr2; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	120 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	121 "mfspr %0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	122 "mr %1,%0;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	123 "or %0,%0,%3;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	124 "mtspr %2,%0;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	125 "mtspr %2,%1" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	126 : "=&r" (_scr1), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	127 "=&r" (_scr2) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	128 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	129 "r" (_HID0_DCFI) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	130 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	131 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	132
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	133 // Synchronize the contents of the cache with memory.
901 b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	134 // Modifications to this macro should mirror modifications to the
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	135 // identically named one in the mpc8260 variant.
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	136 // We step through twice the number of lines in the cache in order
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	137 // to ensure that all dirty lines are flushed to main memory.
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	138 // (Consider the case where one of the dirty lines is in the
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	139 // first 16Kbytes of RAM -- it won't get flushed by loading
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	140 // in words from the first 16Kbytes of RAM).
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	141 #define HAL_DCACHE_SYNC() \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	142 CYG_MACRO_START \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	143 cyg_int32 i; \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	144 cyg_uint32 __base = (cyg_uint32 ) (0); \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	145 for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	146 asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \
b7a9c0130fa1 * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the jlarmour parents: 482 diff changeset	147 } \
482 3bdcf83ee58f Define data cache sync. gthomas parents: 473 diff changeset	148 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	149
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	150 // Query the state of the data cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	151 #define HAL_DCACHE_IS_ENABLED(_state_) \
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	152 CYG_MACRO_START \
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	153 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	154 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	155 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	156 "and %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	157 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	158 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	159 "r" (_HID0_DCE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	160 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	161 (_state_) = _scratch != 0; \
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	162 CYG_MACRO_END
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	163
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	164 // Set the data cache refill burst size
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	165 //#define HAL_DCACHE_BURST_SIZE(_size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	166
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	167 // Set the data cache write mode
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	168 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	169
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	170 //#define HAL_DCACHE_WRITETHRU_MODE 0
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	171 //#define HAL_DCACHE_WRITEBACK_MODE 1
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	172
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	173 // Load the contents of the given address range into the data cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	174 // and then lock the cache so that it stays there.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	175 //#define HAL_DCACHE_LOCK(_base_, _size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	176
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	177 // Undo a previous lock operation
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	178 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	179
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	180 // Unlock entire cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	181 //#define HAL_DCACHE_UNLOCK_ALL()
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	182
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	183 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	184 // Data cache line control
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	185
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	186 // Allocate cache lines for the given address range without reading its
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	187 // contents from memory.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	188 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	189
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	190 // Write dirty cache lines to memory and invalidate the cache entries
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	191 // for the given address range.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	192 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	193 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	194 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	195 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	196 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	197 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	198 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	199 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	200 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	201 CYG_MACRO_END
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	202
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	203 // Invalidate cache lines in the given range without writing to memory.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	204 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	205 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	206 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	207 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	208 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	209 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	210 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	211 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	212 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	213 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	214
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	215 // Write dirty cache lines to memory for the given address range.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	216 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	217 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	218 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	219 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	220 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	221 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	222 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	223 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	224 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	225 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	226
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	227 // Preread the given range into the cache with the intention of reading
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	228 // from it later.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	229 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	230 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	231 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	232 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	233 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	234 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	235 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	236 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	237 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	238 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	239
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	240 // Preread the given range into the cache with the intention of writing
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	241 // to it later.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	242 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	243 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	244 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	245 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	246 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	247 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	248 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	249 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	250 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	251 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	252
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	253 // Allocate and zero the cache lines associated with the given range.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	254 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	255 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	256 cyg_uint32 __base = (cyg_uint32) (_base_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	257 cyg_int32 __size = (cyg_int32) (_size_); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	258 while (__size > 0) { \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	259 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	260 __base += HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	261 __size -= HAL_DCACHE_LINE_SIZE; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	262 } \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	263 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	264
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	265 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	266 // Global control of Instruction cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	267
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	268 // Enable the instruction cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	269 #define HAL_ICACHE_ENABLE() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	270 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	271 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	272 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	273 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	274 "or %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	275 "mtspr %1,%0" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	276 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	277 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	278 "r" (_HID0_ICE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	279 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	280 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	281
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	282 // Disable the instruction cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	283 #define HAL_ICACHE_DISABLE() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	284 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	285 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	286 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	287 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	288 "andc %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	289 "mtspr %1,%0" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	290 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	291 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	292 "r" (_HID0_ICE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	293 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	294 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	295
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	296 // Invalidate the entire cache
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	297 #define HAL_ICACHE_INVALIDATE_ALL() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	298 CYG_MACRO_START \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	299 cyg_int32 _scr1, _scr2; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	300 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	301 "mfspr %0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	302 "mr %1,%0;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	303 "or %0,%0,%3;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	304 "mtspr %2,%0;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	305 "mtspr %2,%1" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	306 : "=&r" (_scr1), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	307 "=&r" (_scr2) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	308 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	309 "r" (_HID0_ICFI) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	310 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	311 CYG_MACRO_END
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	312
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	313 // Synchronize the contents of the cache with memory.
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	314 #define HAL_ICACHE_SYNC() \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	315 HAL_ICACHE_INVALIDATE_ALL()
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	316
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	317 // Query the state of the instruction cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	318 #define HAL_ICACHE_IS_ENABLED(_state_) \
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	319 CYG_MACRO_START \
473 87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	320 cyg_int32 _scratch; \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	321 asm volatile ("isync;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	322 "mfspr %0,%1;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	323 "and %0,%0,%2;" \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	324 : "=&r" (_scratch) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	325 : "I" (CYGARC_REG_HID0), \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	326 "r" (_HID0_ICE) \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	327 ); \
87f3e026b015 PPC60x improvements gthomas parents: 210 diff changeset	328 (_state_) = _scratch != 0; \
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	329 CYG_MACRO_END
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	330
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	331 // Set the instruction cache refill burst size
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	332 //#define HAL_ICACHE_BURST_SIZE(_size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	333
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	334 // Load the contents of the given address range into the instruction cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	335 // and then lock the cache so that it stays there.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	336 //#define HAL_ICACHE_LOCK(_base_, _size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	337
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	338 // Undo a previous lock operation
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	339 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	340
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	341 // Unlock entire cache
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	342 //#define HAL_ICACHE_UNLOCK_ALL()
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	343
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	344 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	345 // Instruction cache line control
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	346
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	347 // Invalidate cache lines in the given range without writing to memory.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	348 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	349
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	350 //-----------------------------------------------------------------------------
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	351 #endif // ifndef CYGONCE_VAR_CACHE_H
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: diff changeset	352 // End of var_cache.h

Mercurial > ecos

annotate packages/hal/powerpc/ppc60x/current/include/var_cache.h @ 3292:7f8e529b4d82 default tip