Mercurial > ecos
changeset 901:b7a9c0130fa1
* include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the
number of lines in order to ensure that dirty lines in the first
16Kbytes of memory are flushed.
| author | jlarmour |
|---|---|
| date | Thu, 03 Apr 2003 15:56:43 +0000 |
| parents | 370be9d42783 |
| children | 5ede1532afc0 |
| files | packages/hal/powerpc/mpc8260/current/ChangeLog packages/hal/powerpc/mpc8260/current/include/var_cache.h packages/hal/powerpc/ppc60x/current/ChangeLog packages/hal/powerpc/ppc60x/current/include/var_cache.h |
| diffstat | 4 files changed, 34 insertions(+), 9 deletions(-) [+] |
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--- a/packages/hal/powerpc/mpc8260/current/ChangeLog +++ b/packages/hal/powerpc/mpc8260/current/ChangeLog @@ -1,3 +1,9 @@ +2003-04-03 Patrick Doyle <wpd@delcomsys.com> + + * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the + number of lines in order to ensure that dirty lines in the first + 16Kbytes of memory are flushed. + 2003-03-04 Paul Fine <pfine@delcomsys.com> * include/var_cache.h: Modify the HAL_DCACHE_SYNC macro to look
--- a/packages/hal/powerpc/mpc8260/current/include/var_cache.h +++ b/packages/hal/powerpc/mpc8260/current/include/var_cache.h @@ -137,12 +137,18 @@ // Synchronize the contents of the cache with memory. -// Use the macro defined in the PPC60x HAL as of January 2003. +// Modifications to this macro should mirror modifications to the +// identically named one in the ppc60x variant. +// We step through twice the number of lines in the cache in order +// to ensure that all dirty lines are flushed to main memory. +// (Consider the case where one of the dirty lines is in the +// first 16Kbytes of RAM -- it won't get flushed by loading +// in words from the first 16Kbytes of RAM). #define HAL_DCACHE_SYNC() \ CYG_MACRO_START \ cyg_int32 i; \ cyg_uint32 *__base = (cyg_uint32 *) (0); \ - for(i=0;i< (HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \ + for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \ asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \ } \ CYG_MACRO_END
--- a/packages/hal/powerpc/ppc60x/current/ChangeLog +++ b/packages/hal/powerpc/ppc60x/current/ChangeLog @@ -1,3 +1,9 @@ +2003-04-03 Patrick Doyle <wpd@delcomsys.com> + + * include/var_cache.h (HAL_DCACHE_SYNC): Step through twice the + number of lines in order to ensure that dirty lines in the first + 16Kbytes of memory are flushed. + 2003-02-26 Gary Thomas <gary@mlbassoc.com> * include/variant.inc: Get proper initialization for ROMRAM startup.
--- a/packages/hal/powerpc/ppc60x/current/include/var_cache.h +++ b/packages/hal/powerpc/ppc60x/current/include/var_cache.h @@ -133,13 +133,20 @@ CYG_MACRO_END // Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() \ - CYG_MACRO_START \ - cyg_int32 i; \ - cyg_uint32 *__base = (cyg_uint32 *) (0); \ - for (i = 0; i < (HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); i++, __base += HAL_DCACHE_LINE_SIZE/4){ \ - asm volatile ("lwz %%r0,0(%0)" : : "r" (__base) : "r0"); \ - } \ +// Modifications to this macro should mirror modifications to the +// identically named one in the mpc8260 variant. +// We step through twice the number of lines in the cache in order +// to ensure that all dirty lines are flushed to main memory. +// (Consider the case where one of the dirty lines is in the +// first 16Kbytes of RAM -- it won't get flushed by loading +// in words from the first 16Kbytes of RAM). +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + cyg_int32 i; \ + cyg_uint32 *__base = (cyg_uint32 *) (0); \ + for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \ + asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \ + } \ CYG_MACRO_END // Query the state of the data cache