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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_HAL_PLATFORM_INC
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2 #define CYGONCE_HAL_PLATFORM_INC
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3 ##=============================================================================
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4 ##
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5 ## platform.inc
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6 ##
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7 ## SH/EDK7708 board assembler header file
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8 ##
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9 ##=============================================================================
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10 ## ####ECOSGPLCOPYRIGHTBEGIN####
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11 ## -------------------------------------------
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12 ## This file is part of eCos, the Embedded Configurable Operating System.
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13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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14 ##
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15 ## eCos is free software; you can redistribute it and/or modify it under
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16 ## the terms of the GNU General Public License as published by the Free
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17 ## Software Foundation; either version 2 or (at your option) any later
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18 ## version.
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19 ##
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20 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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21 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 ## for more details.
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24 ##
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25 ## You should have received a copy of the GNU General Public License
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26 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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27 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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28 ##
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29 ## As a special exception, if other files instantiate templates or use
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30 ## macros or inline functions from this file, or you compile this file
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31 ## and link it with other works to produce a work based on this file,
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32 ## this file does not by itself cause the resulting work to be covered by
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33 ## the GNU General Public License. However the source code for this file
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34 ## must still be made available in accordance with section (3) of the GNU
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35 ## General Public License v2.
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36 ##
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37 ## This exception does not invalidate any other reasons why a work based
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38 ## on this file might be covered by the GNU General Public License.
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39 ## -------------------------------------------
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40 ## ####ECOSGPLCOPYRIGHTEND####
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41 ##=============================================================================
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42 #######DESCRIPTIONBEGIN####
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43 ##
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44 ## Author(s): jskov
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45 ## Contributors:jskov
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46 ## Date: 2000-02-02
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47 ## Purpose: SH/EDK7708 board definitions.
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48 ## Description: This file contains various definitions and macros that are
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49 ## useful for writing assembly code for the SH/EDK7708 board.
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50 ## Usage:
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51 ## #include <cyg/hal/platform.inc>
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52 ## ...
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53 ##
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54 ##
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55 ######DESCRIPTIONEND####
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56 ##
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57 ##=============================================================================
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58
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59 #include <pkgconf/hal.h>
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60
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61 #include <cyg/hal/sh_regs.h>
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62 #include <cyg/hal/sh_offsets.inc>
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63
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64 #------------------------------------------------------------------------------
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65 # Hardware initialization.
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66
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67 .macro hal_hardware_init
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68 // Set up the Bus State Controller
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69 mova BSC_settings_table,r0
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70 mov r0,r3
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71 1: mov.w @r3+,r0 // Address (or zero)
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72 cmp/eq #0,r0
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73 bt 2f
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74 mov.w @r3+,r1 // data
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75 bra 1b
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76 mov.w r1,@r0 // delay slot
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77
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78 .align 2
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79 BSC_settings_table:
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80 # These are the settings set by the Hitachi ROM Monitor.
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81
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82 .word (CYGARC_REG_FRQCR & 0x0000FFFF)
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83 .word CYGARC_REG_FRQCR_INIT
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84
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85 # BCR2: Bus size of areas 1-6 to 32 bits
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86 .word (CYGARC_REG_BCR2 & 0x0000FFFF)
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87 .word 0x3ffc
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88 # BCR1: Areas 2 and 3 are SDRAM
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89 .word (CYGARC_REG_BCR1 & 0x0000FFFF)
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90 .word 0x080c
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91 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
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92 .word (CYGARC_REG_BCR2 & 0x0000FFFF)
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93 .word 0x3ffc
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94 # WCR1: 3 wait-state cycles inserted for all areas
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95 .word (CYGARC_REG_WCR1 & 0x0000FFFF)
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96 .word 0x3fff
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97 # WCR2: extra wait states and full pitch for burst
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98 .word (CYGARC_REG_WCR2 & 0x0000FFFF)
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99 .word 0xffd7
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100 # MCR: RAS/CAS & burst timing area 2/3
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101 .word (CYGARC_REG_MCR & 0x0000FFFF)
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102 .word 0x963c
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103 # RTCNT: refresh counter (needs a5 in top byte to accept write)
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104 .word (CYGARC_REG_RTCNT & 0x0000FFFF)
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105 .word (0xa500 | 0x0000)
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106 # RTCOR: refresh time constant (needs a5 in top byte to accept write)
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107 .word (CYGARC_REG_RTCOR & 0x0000FFFF)
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108 .word (0xa500 | 0x003b)
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109 # RFCR: refresh count register (needs a4 in top byte to accept write)
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110 .word (CYGARC_REG_RFCR & 0x0000FFFF)
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111 .word (0xa400 | 0x0000)
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112 # RTCSR: refresh timer control (needs a5 in top byte to accept write)
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113 .word (CYGARC_REG_RTCSR & 0x0000FFFF)
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114 .word (0xa500 | 0x0008)
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115
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116 # Set SDMR to 0x220
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117 .word 0xd880
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118 .word 0
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119
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120 # Table end
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121 .word 0
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122
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123 .align 2
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124 2:
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125 .endm
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126
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127 #------------------------------------------------------------------------------
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128 # Monitor initialization.
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129
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130 #ifndef CYGPKG_HAL_SH_MON_DEFINED
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131
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132 #if !defined(CYG_HAL_STARTUP_RAM) || \
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133 ( defined(CYG_HAL_STARTUP_RAM) && \
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134 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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135
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136 # If we are not starting up from RAM, or we are starting in
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137 # RAM and NOT using a ROM monitor, initialize the VSR table.
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138
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139 .macro hal_mon_init
138
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140 mov.l $hal_vsr_table,r3
134
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141 # Write exception vectors
138
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142 mov.l $cyg_hal_default_exception_vsr,r4
134
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143 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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144 1: mov.l r4,@r3
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145 add #4,r3
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146 dt r5
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147 bf 1b
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148 # Write interrupt vector
138
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149 mov.l $cyg_hal_default_interrupt_vsr,r4
156
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150 mov.l $hal_vsr_table,r3
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151 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
134
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152 mov.l r4,@r3
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153 bra 2f
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154 nop
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155 .align 2
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156
138
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157 SYM_PTR_REF(cyg_hal_default_exception_vsr)
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158 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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159 SYM_PTR_REF(hal_vsr_table)
134
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160 2:
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161 .endm
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162
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163 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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164
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165 # Initialize the VSR table entries
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166 # We only take control of the interrupt vector,
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167 # the rest are left to the ROM for now...
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168
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169 .macro hal_mon_init
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170 # Write interrupt vector
138
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171 mov.l $hal_vsr_table,r3
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172 mov.l $cyg_hal_default_interrupt_vsr,r4
150
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173 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
134
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174 mov.l r4,@r3
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175 bra 2f
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176 nop
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177 .align 2
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178
138
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179 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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180 SYM_PTR_REF(hal_vsr_table)
134
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181 2:
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182 .endm
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183
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184 #else
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185
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186 .macro hal_mon_init
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187 .endm
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188
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189 #endif
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190
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191
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192 #define CYGPKG_HAL_SH_MON_DEFINED
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193
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194 #endif // CYGPKG_HAL_SH_MON_DEFINED
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195
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196 #endif // CYGONCE_HAL_PLATFORM_INC