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annotate packages/hal/sh/sh3/current/include/var_cache.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL variant cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): jskov
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46 // Contributors:jskov
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47 // Date: 1999-04-23
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/hal_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/system.h>
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61 #include <pkgconf/hal.h>
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62 #include <cyg/infra/cyg_type.h>
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63 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
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64
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65 #include <cyg/hal/plf_cache.h> // Platform cache definitions
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66
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67 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs
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68
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69 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
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70
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71 //-----------------------------------------------------------------------------
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72 // Cache dimensions - one unified cache
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73
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74 #define HAL_CACHE_UNIFIED
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75
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76 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
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77 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
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78 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
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79
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80 // Cache addressing information
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81 #define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE
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82 #define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP
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83 #define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP
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84
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85 // Writing this to a cache address entry forces a flush of the line if
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86 // it is dirty.
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87 #define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH
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88
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89 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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90
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91 //-----------------------------------------------------------------------------
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92 // Global control of cache
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93
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94 // This is all handled in assembly (see variant.S) due to a requirement about
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95 // not fiddling the cache from cachable memory.
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96
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97 externC void cyg_hal_cache_enable(void);
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98 externC void cyg_hal_cache_disable(void);
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99 externC void cyg_hal_cache_invalidate_all(void);
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100 externC void cyg_hal_cache_sync(void);
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101 externC void cyg_hal_cache_sync_region(cyg_haladdress base,
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102 cyg_haladdrword len);
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103 externC void cyg_hal_cache_write_mode(int mode);
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104
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105 // Enable the cache
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106 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
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107
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108 // Disable the cache
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109 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
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110
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111 // Invalidate the entire cache
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112 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
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113
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114 // Synchronize the contents of the cache with memory.
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115 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
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116
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117 // Query the state of the cache (does not affect the caching)
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118 #define HAL_UCACHE_IS_ENABLED(_state_) \
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119 CYG_MACRO_START \
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120 cyg_uint32 _tmp; \
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121 HAL_READ_UINT32(CYGARC_REG_CCR, _tmp); \
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122 (_state_) = (_tmp & CYGARC_REG_CCR_CE) ? 1 : 0; \
134
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123 CYG_MACRO_END
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124
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125 // Set the cache refill burst size
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126 //#define HAL_UCACHE_BURST_SIZE(_size_)
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127
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128 // Set the cache write mode
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129 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \
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130 CYG_MACRO_START \
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131 cyg_uint32 _m_; \
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132 if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \
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133 _m_ = CYGARC_REG_CCR_WT; \
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134 else \
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135 _m_ = CYGARC_REG_CCR_CB; \
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136 cyg_hal_cache_write_mode(_m_); \
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137 CYG_MACRO_END
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138
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139 #define HAL_UCACHE_WRITETHRU_MODE 0
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140 #define HAL_UCACHE_WRITEBACK_MODE 1
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141
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142 // This macro allows the client to specify separate modes for the two
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143 // regions.
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144 #define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_)
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145
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146 // Load the contents of the given address range into the cache
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147 // and then lock the cache so that it stays there.
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148 //#define HAL_UCACHE_LOCK(_base_, _size_)
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149
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150 // Undo a previous lock operation
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151 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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152
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153 // Unlock entire cache
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154 //#define HAL_UCACHE_UNLOCK_ALL()
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155
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156 //-----------------------------------------------------------------------------
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157 // Cache line control
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158
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159 // Allocate cache lines for the given address range without reading its
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160 // contents from memory.
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161 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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162
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163 // Write dirty cache lines to memory and invalidate the cache entries
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164 // for the given address range.
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165 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) \
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166 cyg_hal_cache_sync_region((cyg_haladdress) _base_, (cyg_haladdrword)_size_)
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167
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168 // Invalidate cache lines in the given range without writing to memory.
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169 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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170
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171 // Write dirty cache lines to memory for the given address range.
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172 //#define HAL_UCACHE_STORE( _base_ , _size_ )
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173
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174
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175 // Preread the given range into the cache with the intention of reading
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176 // from it later.
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177 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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178
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179 // Preread the given range into the cache with the intention of writing
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180 // to it later.
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181 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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182
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183 // Allocate and zero the cache lines associated with the given range.
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184 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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185
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186
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187 //-----------------------------------------------------------------------------
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188 // Data and instruction cache macros map onto the both-cache macros
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189
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190 //-----------------------------------------------------------------------------
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191 // Global control of data cache
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192
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193 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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194 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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195 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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196 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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197
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198 // Enable the data cache
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199 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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200
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201 // Disable the data cache
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202 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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203
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204 // Invalidate the entire cache
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205 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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206
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207 // Synchronize the contents of the cache with memory.
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208 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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209
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210 // Query the state of the data cache
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211 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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212
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213 // Set the data cache refill burst size
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214 //#define HAL_DCACHE_BURST_SIZE(_size_)
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215
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216 // Set the data cache write mode
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217 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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218
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219 //#define HAL_DCACHE_WRITETHRU_MODE 0
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220 //#define HAL_DCACHE_WRITEBACK_MODE 1
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221
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222 // Load the contents of the given address range into the data cache
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223 // and then lock the cache so that it stays there.
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224 //#define HAL_DCACHE_LOCK(_base_, _size_)
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225
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226 // Undo a previous lock operation
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227 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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228
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229 // Unlock entire cache
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230 //#define HAL_DCACHE_UNLOCK_ALL()
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231
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232 //-----------------------------------------------------------------------------
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233 // Data cache line control
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234
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235 // Allocate cache lines for the given address range without reading its
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236 // contents from memory.
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237 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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238
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239 // Write dirty cache lines to memory and invalidate the cache entries
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240 // for the given address range.
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241 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ )
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242
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243 // Invalidate cache lines in the given range without writing to memory.
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244 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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245
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246 // Write dirty cache lines to memory for the given address range.
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247 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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248
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249 // Preread the given range into the cache with the intention of reading
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250 // from it later.
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251 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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252
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253 // Preread the given range into the cache with the intention of writing
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254 // to it later.
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255 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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256
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257 // Allocate and zero the cache lines associated with the given range.
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258 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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259
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260 //-----------------------------------------------------------------------------
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261 // Global control of Instruction cache
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262
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263 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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264 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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265 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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266 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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267
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268 // Enable the instruction cache
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269 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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270
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271 // Disable the instruction cache
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272 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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273
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274 // Invalidate the entire cache
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275 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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276
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277
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278 // Synchronize the contents of the cache with memory.
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279 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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280
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281 // Query the state of the instruction cache
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282 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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283
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284 // Set the instruction cache refill burst size
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285 //#define HAL_ICACHE_BURST_SIZE(_size_)
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286
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287 // Load the contents of the given address range into the instruction cache
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288 // and then lock the cache so that it stays there.
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289
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290 //#define HAL_ICACHE_LOCK(_base_, _size_)
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291
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292 // Undo a previous lock operation
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293 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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294
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295 // Unlock entire cache
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296 //#define HAL_ICACHE_UNLOCK_ALL()
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297
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298 //-----------------------------------------------------------------------------
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299 // Instruction cache line control
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300
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301 // Invalidate cache lines in the given range without writing to memory.
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302 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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303
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304 //-----------------------------------------------------------------------------
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305 #endif // ifndef CYGONCE_VAR_CACHE_H
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306 // End of var_cache.h