Mercurial > ecos
annotate packages/hal/sh/sh3/current/include/variant.inc @ 3292:7f8e529b4d82 default tip
Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
| author | vae |
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| date | Wed, 29 Apr 2015 23:31:48 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
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1 #ifndef CYGONCE_HAL_VARIANT_INC |
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2 #define CYGONCE_HAL_VARIANT_INC |
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3 ##============================================================================= |
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4 ## |
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5 ## variant.inc |
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6 ## |
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7 ## SH3 variant assembler header file |
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8 ## |
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9 ##============================================================================= |
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10 ## ####ECOSGPLCOPYRIGHTBEGIN#### |
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11 ## ------------------------------------------- |
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12 ## This file is part of eCos, the Embedded Configurable Operating System. |
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13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
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14 ## |
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15 ## eCos is free software; you can redistribute it and/or modify it under |
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16 ## the terms of the GNU General Public License as published by the Free |
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17 ## Software Foundation; either version 2 or (at your option) any later |
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18 ## version. |
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19 ## |
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20 ## eCos is distributed in the hope that it will be useful, but WITHOUT |
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21 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 ## for more details. |
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24 ## |
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25 ## You should have received a copy of the GNU General Public License |
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26 ## along with eCos; if not, write to the Free Software Foundation, Inc., |
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27 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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28 ## |
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29 ## As a special exception, if other files instantiate templates or use |
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30 ## macros or inline functions from this file, or you compile this file |
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31 ## and link it with other works to produce a work based on this file, |
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32 ## this file does not by itself cause the resulting work to be covered by |
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33 ## the GNU General Public License. However the source code for this file |
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34 ## must still be made available in accordance with section (3) of the GNU |
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35 ## General Public License v2. |
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36 ## |
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37 ## This exception does not invalidate any other reasons why a work based |
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38 ## on this file might be covered by the GNU General Public License. |
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39 ## ------------------------------------------- |
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40 ## ####ECOSGPLCOPYRIGHTEND#### |
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41 ##============================================================================= |
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42 #######DESCRIPTIONBEGIN#### |
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43 ## |
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44 ## Author(s): jskov |
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45 ## Contributors:jskov |
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46 ## Date: 2000-10-30 |
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47 ## Purpose: SH3 variant definitions and init code |
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48 ## Description: This file contains various definitions and macros that are |
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49 ## useful for writing assembly code for the SH3 CPU family. |
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50 ## Usage: |
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51 ## #include <cyg/hal/variant.inc> |
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52 ## ... |
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53 ## |
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54 ## |
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55 ######DESCRIPTIONEND#### |
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56 ## |
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57 ##============================================================================= |
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58 |
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59 #include <pkgconf/hal.h> |
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60 #include <cyg/hal/sh_regs.h> |
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61 |
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62 #=========================================================================== |
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63 ## SR initialization value |
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64 ## zero all bits except: |
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65 ## MD = Processor operation mode field (privileged mode) |
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66 ## I0-3 = Mask out all interrupts but NMI. |
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67 ## |
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68 ## When saving or restoring the state of an exception or interrupt, the bit |
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69 ## CYGARC_REG_SR_RB is also set, switching the register bank. When this bit |
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70 ## is set, interrupts must be disabled. |
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71 ## |
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72 ## Note: We could also use the BL bit to prevent interrupts, but that would |
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73 ## also prevent the use of breakpoints. |
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74 |
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75 #define CYG_SR (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK) |
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76 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) |
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77 |
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78 ##----------------------------------------------------------------------------- |
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79 ## Hardware init macros |
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80 #ifndef CYGPKG_HAL_SH_POST_RESET_INIT |
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81 .macro hal_post_reset_init |
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82 # Initialize CPU |
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83 mov.l $nCYG_SR,r1 ! Put CPU in a well-known state |
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84 ldc r1,sr |
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85 mov #0,r0 |
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86 mov #CYGARC_REG_CCR & 0x0FF,r1 ! Disable cache |
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87 mov.l r0,@r1 |
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88 mov #CYGARC_REG_MMUCR & 0x0FF,r1 ! Disable MMU |
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89 mov.l r0,@r1 |
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90 mov #CYGARC_REG_BBRA & 0x0FF,r1 ! Disable UBC Channel A |
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91 mov.w r0,@r1 |
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92 mov #CYGARC_REG_BBRB & 0x0FF,r1 ! Disable UBC Channel B |
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93 mov.w r0,@r1 |
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94 mov #CYGARC_REG_BRCR & 0x0FF,r1 ! Reset UBC common register |
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95 mov.w r0,@r1 |
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96 mov.l $CYGARC_REG_TSTR,r1 ! Disable timers |
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97 mov.b r0,@r1 |
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98 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources |
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99 mov.w r0,@r1 |
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100 mov.l $CYGARC_REG_IPRB,r1 |
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101 mov.w r0,@r1 |
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102 #if (CYGARC_SH_MOD_INTC >= 2) |
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103 mov.l $CYGARC_REG_IPRC,r1 |
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104 mov.w r0,@r1 |
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105 mov.l $CYGARC_REG_IPRD,r1 |
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106 mov.w r0,@r1 |
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107 mov.l $CYGARC_REG_IPRE,r1 |
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108 mov.w r0,@r1 |
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109 #if (CYGARC_SH_MOD_INTC >= 3) |
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110 mov.l $CYGARC_REG_IPRF,r1 |
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111 mov.w r0,@r1 |
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112 #endif |
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113 mov.w $nCYG_ICR1_INIT,r0 |
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114 mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode |
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115 mov.w r0,@r1 |
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116 #endif |
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117 mov.w $nCYG_WTCSR,r0 ! Clear watchdog |
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118 mov #CYGARC_REG_WTCSR & 0x0FF,r1 |
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119 mov.w r0,@r1 |
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120 |
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121 # Initialize VBR if necessary |
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122 #if !defined(CYG_HAL_STARTUP_RAM) || \ |
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123 ( defined(CYG_HAL_STARTUP_RAM) && \ |
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124 !defined(CYGSEM_HAL_USE_ROM_MONITOR)) |
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125 mov.l $_reset,r1 ! Set VBR |
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126 ldc r1,vbr |
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127 #endif |
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128 bra 1f |
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129 nop |
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130 |
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131 $nCYG_WTCSR: |
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132 .word 0xa500 ! clear all CSR bits |
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133 |
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134 .align 2 |
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135 $nCYG_SR: |
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136 .long CYG_SR |
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137 $CYGARC_REG_TSTR: |
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138 .long CYGARC_REG_TSTR |
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139 $CYGARC_REG_IPRA: |
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140 .long CYGARC_REG_IPRA |
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141 $CYGARC_REG_IPRB: |
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142 .long CYGARC_REG_IPRB |
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143 #if (CYGARC_SH_MOD_INTC >= 2) |
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144 $CYGARC_REG_IPRC: |
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145 .long CYGARC_REG_IPRC |
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146 $CYGARC_REG_IPRD: |
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147 .long CYGARC_REG_IPRD |
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148 $CYGARC_REG_IPRE: |
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149 .long CYGARC_REG_IPRE |
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150 $CYGARC_REG_ICR1: |
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151 .long CYGARC_REG_ICR1 |
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152 $nCYG_ICR1_INIT: |
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153 .word CYGARC_REG_ICR1_INIT |
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154 .align 2 |
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155 #endif |
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156 #if (CYGARC_SH_MOD_INTC >= 3) |
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157 $CYGARC_REG_IPRF: |
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158 .long CYGARC_REG_IPRF |
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159 #endif |
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160 SYM_PTR_REF(_reset) |
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161 |
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162 1: |
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163 .endm |
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164 #define CYGPKG_HAL_SH_POST_RESET_INIT |
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165 #endif |
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166 |
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167 ##----------------------------------------------------------------------------- |
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168 ## Interrupt decode macros |
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169 .macro hal_intc_decode tmp,inum |
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170 mov.l 1f,\tmp |
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171 mov.l @\tmp,\inum |
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172 mov #-5,\tmp ! divide cause by 0x20 |
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173 shld \tmp,\inum |
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174 bra 2f |
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175 add #-14,\inum ! adjust so NMI becomes 0 |
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176 .align 2 |
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177 1: |
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178 #if (CYGARC_SH_MOD_INTC >= 2) |
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179 .long CYGARC_REG_INTEVT2 |
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180 #else |
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181 .long CYGARC_REG_INTEVT |
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182 #endif |
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183 2: |
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184 .endm |
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185 |
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186 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN |
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187 .macro hal_intc_translate inum,vnum |
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188 mov #0,\vnum ! Just vector zero is supported |
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189 .endm |
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190 #else |
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191 .macro hal_intc_translate inum,vnum |
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192 mov \inum,\vnum ! Vector == interrupt number |
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193 shll2 \vnum ! get from vector number to ISR index |
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194 .endm |
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195 #endif |
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196 |
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197 #------------------------------------------------------------------------------ |
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198 #endif // CYGONCE_HAL_VARIANT_INC |
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199 # end of variant.inc |