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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents f1c9d35ca75a
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 # ====================================================================
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2 #
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3 # hal_sh_sh4.cdl
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4 #
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5 # SH4 architectural HAL package configuration data
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6 #
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7 # ====================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 # ====================================================================
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40 ######DESCRIPTIONBEGIN####
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41 #
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42 # Author(s): jskov, nickg
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43 # Original data: jskov
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44 # Contributors:
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45 # Date: 1999-10-29
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46 #
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47 #####DESCRIPTIONEND####
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48 #
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49 # ====================================================================
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50
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51 cdl_package CYGPKG_HAL_SH_SH4 {
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52 display "SH4 architecture"
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53 parent CYGPKG_HAL_SH
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54
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55 hardware
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56 include_dir cyg/hal
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57 define_header hal_sh_sh4.h
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58 description "
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59 The SH4 (SuperH 4) architecture HAL package provides generic
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60 support for this processor architecture. It is also
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61 necessary to select a specific target platform HAL
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62 package."
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63
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64 compile sh4_scif.c var_misc.c variant.S
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65
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66 define_proc {
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67 puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_sh_sh4.h>"
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68 puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_H <cyg/hal/hal_var_bank.h>"
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69 puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_INC <cyg/hal/hal_var_bank.inc>"
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70 puts $::cdl_header "#define CYGBLD_HAL_VAR_INTR_MODEL_H <cyg/hal/hal_intr_excevt.h>"
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71 }
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72
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73 # The "-o file" is a workaround for CR100958 - without it the
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74 # output file would end up in the source directory under CygWin.
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75 # n.b. grep does not behave itself under win32
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76 make -priority 1 {
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77 <PREFIX>/include/cyg/hal/sh4_offsets.inc : <PACKAGE>/src/var_mk_defs.c
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78 $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $<
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79 fgrep .equ var_mk_defs.tmp | sed s/#// > $@
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80 @echo $@ ": \\" > $(notdir $@).deps
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81 @tail -n +2 sh4_offsets.tmp >> $(notdir $@).deps
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82 @echo >> $(notdir $@).deps
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83 @rm sh4_offsets.tmp var_mk_defs.tmp
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84 }
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85
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86 # CPU variant supported
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87 cdl_component CYGPKG_HAL_SH_7750 {
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88 display "SH 7750 microprocessor"
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89 parent CYGPKG_HAL_SH_CPU
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90 implements CYGINT_HAL_SH_VARIANT
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91 implements CYGINT_HAL_SH_CPG_T1
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92 requires ! CYGHWR_HAL_SH_CACHE_ENABLE
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93 default_value 0
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94 no_define
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95 define -file=system.h CYGPKG_HAL_SH_7750
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96 description "
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97 The SH4 7750 microprocessor. This is an embedded part that in
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98 addition to the SH4 processor core has built in peripherals
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99 such as memory controllers, DMA controllers, serial ports and
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100 timers/counters."
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101 define_proc {
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102 puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7750.h>"
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103 }
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104 }
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105
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106 cdl_component CYGPKG_HAL_SH_7751 {
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107 display "SH 7751 microprocessor"
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108 parent CYGPKG_HAL_SH_CPU
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109 implements CYGINT_HAL_SH_VARIANT
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110 implements CYGINT_HAL_SH_CPG_T1
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111 default_value 0
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112 no_define
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113 define -file=system.h CYGPKG_HAL_SH_7751
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114 compile pcic.c
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115 description "
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116 The SH4 7751 microprocessor. This is an embedded part that in
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117 addition to the SH4 processor core has built in peripherals
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118 such as memory controllers, DMA controllers, serial ports and
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119 timers/counters."
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120 define_proc {
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121 puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7751.h>"
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122 }
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123 }
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124
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125 cdl_component CYGPKG_HAL_SH_202 {
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126 display "SH 202 microprocessor"
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127 parent CYGPKG_HAL_SH_CPU
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128 implements CYGINT_HAL_SH_VARIANT
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129 implements CYGINT_HAL_SH_CPG_T1
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130 requires CYGHWR_HAL_SH_FPU
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131 requires { CYGHWR_HAL_SH_FPU_REGS == 16 }
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132 default_value 0
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133 no_define
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134 define -file=system.h CYGPKG_HAL_SH_202
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135 description "
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136 The SH4-202 microprocessor. This is an embedded part that in
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137 addition to the SH4 processor core has built in peripherals
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138 such as memory controllers, DMA controllers, serial ports and
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139 timers/counters."
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140 define_proc {
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141 puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_202.h>"
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142 }
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143 }
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144
134
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145 cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {
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146 display "SH on-chip generic clock controls"
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147 description "
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148 The various clocks used by the system are controlled by
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149 these options, some of which are derived from platform
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150 settings."
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151 flavor none
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152 no_define
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153
171
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154 cdl_interface CYGINT_HAL_SH_CPG_T1 {
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155 display "Clock pulse generator type 1"
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156 }
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157
134
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158 cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {
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159 display "TMU counter 0 prescaling"
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160 description "
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161 The peripheral clock is driving the counter used for
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162 the real-time clock, prescaled by this factor."
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163 flavor data
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164 legal_values { 4 16 64 256 }
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165 default_value 4
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166 }
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167
208
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168 cdl_option CYGHWR_HAL_SH_RTC_PRESCALE {
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169 display "eCos RTC prescaling"
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170 flavor data
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171 calculated CYGHWR_HAL_SH_TMU_PRESCALE_0
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172 }
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173
171
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174 cdl_option CYGHWR_HAL_SH_CLOCK_CKIO {
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175 display "CKIO clock"
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176 no_define
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177 flavor data
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178 calculated { CYGHWR_HAL_SH_PLL2_OUTPUT }
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179 }
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180
134
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181 cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {
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182 display "The clock output from PLL1"
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183 no_define
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184 flavor data
171
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185 calculated { CYGHWR_HAL_SH_DIVIDER1_OUTPUT * CYGHWR_HAL_SH_OOC_PLL_1 }
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186 }
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187
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188 cdl_option CYGHWR_HAL_SH_DIVIDER1_OUTPUT {
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189 display "The clock output from divider 1"
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190 no_define
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191 flavor data
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192 # DIV1 output is either 1 or 1/2 XTAL
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193 calculated { (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1)
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194 ? CYGHWR_HAL_SH_OOC_XTAL
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195 : CYGHWR_HAL_SH_OOC_XTAL / 2 }
134
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196 }
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197
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198 cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {
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199 display "Processor clock speed (MHz)"
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200 flavor data
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201 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_IFC }
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202 description "
171
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203 The peripheral speed is computed from the PLL2 output clock
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204 speed and the IFC divider settings."
134
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205 }
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206
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207 cdl_option CYGHWR_HAL_SH_BOARD_SPEED {
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208 display "Platform bus clock speed (MHz)"
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209 flavor data
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210 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_BFC }
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211 description "
171
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212 The peripheral speed is computed from the PLL2 output clock
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213 speed and the BFC divider settings."
134
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214 }
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215
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216 cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {
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217 display "Processor on-chip peripheral clock speed (MHz)"
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218 flavor data
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219 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_PFC }
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220 description "
171
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221 The peripheral speed is computed from the PLL2 output clock
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222 speed and the PFC divider settings."
134
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223 }
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224 }
151
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225
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226 cdl_option CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE {
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227 display "SCIF serial ports default baud rate"
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228 flavor data
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229 legal_values { 4800 9600 14400 19200 38400 57600 115200 }
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230 default_value { CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE_DEFAULT ? \
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231 CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE_DEFAULT : 38400 }
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232 description "
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233 This controls the default baud rate used for communicating
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234 with GDB / displaying diagnostic output."
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235 }
171
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236
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237 cdl_component CYGPKG_HAL_SH_INTERRUPT {
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238 display "Interrupt controls"
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239 flavor none
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240 no_define
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241 description "
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242 Initial interrupt settings can be specified using these option."
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243
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244 cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL {
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245 display "Use IRL0-3 pins as IRL input"
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246 default_value 0
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247 description "
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248 It is possible for the IRL0-3 pins to be used as IRL
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249 inputs by enabling this option."
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250 }
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251 }
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252
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253 # Cache settings
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254 cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 {
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255 display "Select cache mode set for P0/U0/P3 at startup"
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256 parent CYGPKG_HAL_SH_CACHE
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257 default_value { "WRITE_BACK" }
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258 legal_values { "WRITE_BACK" "WRITE_THROUGH" }
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259 flavor data
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260 description "
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261 Controls what cache mode the cache should be put in at
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262 startup for areas P0, U0 and P3. Write-back mode improves
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263 performance by letting dirty data to be kept in the
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264 cache for a period of time, allowing mutiple writes to
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265 the same cache line to be written back to memory in
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266 one memory transaction. In Write-through mode, each
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267 individual write will cause a memory transaction."
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268 }
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269
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270 cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 {
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271 display "Select cache mode set for P1 at startup"
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272 parent CYGPKG_HAL_SH_CACHE
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273 default_value { "WRITE_BACK" }
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274 legal_values { "WRITE_BACK" "WRITE_THROUGH" }
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275 flavor data
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276 description "
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277 Controls what cache mode the cache should be put in at
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278 startup for area P1. Write-back mode improves
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279 performance by letting dirty data to be kept in the
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280 cache for a period of time, allowing mutiple writes to
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281 the same cache line to be written back to memory in
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282 one memory transaction. In Write-through mode, each
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283 individual write will cause a memory transaction."
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284 }
134
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285 }