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annotate packages/hal/sh/sh4/current/include/mod_regs_cpg.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
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1 //=============================================================================
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2 //
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3 // mod_regs_cpg.h
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4 //
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5 // CPG (clock pulse generator) Module register definitions
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6 //
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7 //=============================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //=============================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): jskov
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43 // Contributors:jskov, nickg
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44 // Date: 2000-10-30
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 //--------------------------------------------------------------------------
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51 // Oscillator control registers
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52 #define CYGARC_REG_FRQCR 0xFFC00000
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53 #define CYGARC_REG_STBCR 0xFFC00004
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54 #define CYGARC_REG_WTCNT 0xFFC00008 // read 8bit, write 16bit
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55 #define CYGARC_REG_WTCSR 0xFFC0000C // read 8bit, write 16bit
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56 #define CYGARC_REG_STBCR2 0xFFC00010
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57
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58 #ifdef CYGPKG_HAL_SH_202
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59 #define CYGARC_REG_FRQCR3 0xFE0A0018
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60 #endif
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61
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62 #define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write
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63
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64 #define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write
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65 #define CYGARC_REG_WTCSR_TME 0x80 // timer enable
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66 #define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0)
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67 #define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0)
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68 #define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow
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69 #define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow
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70 #define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2
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71 #define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1
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72 #define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0
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73 #define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask
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74 // This is the period (in us) between watchdog reset and overflow.
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75 // Note: We use max timeout delay for now.
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76 #define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay
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77
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78 #define CYGARC_REG_WTCSR_PERIOD ((1000000000/(CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/4096))*256)
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79
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80 // Translate various CDL clock configurations to register equivalents
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81 // for the various CPG versions
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82 #if (CYGARC_SH_MOD_CPG == 1) // ---------------------------- V1
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83
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84 // PLL1
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85 #if (CYGHWR_HAL_SH_OOC_PLL_1 == 0)
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86 # define CYGARC_REG_FRQCR_INIT_PLL1 0x0000
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87 #elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4)
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88 # define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
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89 #elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6)
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90 # define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
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91 #elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8)
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92 # define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
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93 #elif (CYGHWR_HAL_SH_OOC_PLL_1 == 12)
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94 # define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
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95 #else
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96 # error "Unsupported PLL1 setting"
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97 #endif
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98
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99 // PLL2
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100 #if (CYGHWR_HAL_SH_OOC_PLL_2 == 0)
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101 # define CYGARC_REG_FRQCR_INIT_PLL2 0x0000
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102 #elif (CYGHWR_HAL_SH_OOC_PLL_2 == 1)
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103 # define CYGARC_REG_FRQCR_INIT_PLL2 0x0200
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104 #else
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105 # error "Unsupported PLL2 setting"
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106 #endif
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107
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108 // Divider IFC
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109 #if (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 1)
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110 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0000
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111 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 2)
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112 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0040
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113 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 3)
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114 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0080
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115 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 4)
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116 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x00c0
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117 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 6)
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118 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0100
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119 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_IFC == 8)
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120 # define CYGARC_REG_FRQCR_INIT_DIVIDER_IFC 0x0140
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121 #else
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122 # error "Unsupported Divider IFC setting"
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123 #endif
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124
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125 // Divider BFC
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126 #if (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 1)
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127 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0000
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128 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 2)
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129 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0008
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130 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 3)
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131 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0010
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132 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 4)
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133 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0018
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134 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 6)
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135 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0020
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136 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_BFC == 8)
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137 # define CYGARC_REG_FRQCR_INIT_DIVIDER_BFC 0x0028
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138 #else
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139 # error "Unsupported Divider BFC setting"
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140 #endif
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141
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142 // Divider PFC
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143 #if (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 2)
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144 # define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0000
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145 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 3)
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146 # define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0001
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147 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 4)
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148 # define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0002
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149 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 6)
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150 # define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0003
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151 #elif (CYGHWR_HAL_SH_OOC_DIVIDER_PFC == 8)
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152 # define CYGARC_REG_FRQCR_INIT_DIVIDER_PFC 0x0004
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153 #else
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154 # error "Unsupported Divider PFC setting"
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155 #endif
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156
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157
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158 // CKOEN
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159 #ifdef CYGHWR_HAL_SH_OOC_CKIO
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160 # define CYGARC_REG_FRQCR_INIT_CKOEN 0x0800
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161 #else
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162 # define CYGARC_REG_FRQCR_INIT_CKOEN 0x0000
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163 #endif
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164
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165 #else
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166
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167 # error "Unsupported CPG version"
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168
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169 #endif
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170
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171 // Init value
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172 #define CYGARC_REG_FRQCR_INIT (CYGARC_REG_FRQCR_INIT_PLL1|CYGARC_REG_FRQCR_INIT_PLL2|CYGARC_REG_FRQCR_INIT_DIVIDER_IFC|CYGARC_REG_FRQCR_INIT_DIVIDER_BFC|CYGARC_REG_FRQCR_INIT_DIVIDER_PFC|CYGARC_REG_FRQCR_INIT_CKOEN)