Mercurial > ecos
annotate packages/hal/sparclite/sleb/current/include/hal_cache.h @ 3292:7f8e529b4d82 default tip
Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
| author | vae |
|---|---|
| date | Wed, 29 Apr 2015 23:31:48 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL Cache control support (such as it is in the simulator) | |
| 9 // | |
| 10 //============================================================================= | |
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11 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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208
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later |
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19 // version. |
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208
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20 // |
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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24 // for more details. |
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25 // |
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26 // You should have received a copy of the GNU General Public License |
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27 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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29 // |
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30 // As a special exception, if other files instantiate templates or use |
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31 // macros or inline functions from this file, or you compile this file |
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32 // and link it with other works to produce a work based on this file, |
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33 // this file does not by itself cause the resulting work to be covered by |
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34 // the GNU General Public License. However the source code for this file |
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35 // must still be made available in accordance with section (3) of the GNU |
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36 // General Public License v2. |
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37 // |
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38 // This exception does not invalidate any other reasons why a work based |
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39 // on this file might be covered by the GNU General Public License. |
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40 // ------------------------------------------- |
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41 // ####ECOSGPLCOPYRIGHTEND#### |
| 2 | 42 //============================================================================= |
| 43 //#####DESCRIPTIONBEGIN#### | |
| 44 // | |
| 45 // Author(s): nickg, gthomas, hmt | |
| 46 // Contributors: nickg, gthomas, hmt | |
| 47 // Date: 1999-01-28 | |
| 48 // Purpose: Define Interrupt support | |
| 49 // Description: The macros defined here provide the HAL APIs for handling | |
| 50 // the caches. | |
| 51 // | |
| 52 // Usage: | |
| 53 // #include <cyg/hal/hal_cache.h> | |
| 54 // ... | |
| 55 // | |
| 56 // | |
| 57 //####DESCRIPTIONEND#### | |
| 58 // | |
| 59 //============================================================================= | |
| 60 | |
| 61 #include <pkgconf/hal.h> | |
| 62 #include <pkgconf/hal_sparclite.h> | |
| 63 | |
| 64 #include <cyg/infra/cyg_type.h> | |
| 65 | |
| 66 //----------------------------------------------------------------------------- | |
| 67 // SPARClite cache macros | |
| 68 | |
| 69 // The MB6863x Control Registers are in Address Space 1: | |
| 70 #define HAL_SPARC_ASI_1_READ( addr, res ) \ | |
| 71 asm volatile( \ | |
| 72 "lda [ %1 ] 1, %0" \ | |
| 73 : "=r"(res) \ | |
| 74 : "r"(addr) \ | |
| 75 ); | |
| 76 | |
| 77 #define HAL_SPARC_ASI_1_WRITE( addr, val ) \ | |
| 78 asm volatile( \ | |
| 79 "sta %0, [ %1 ] 1" \ | |
| 80 : \ | |
| 81 : "r"(val),"r"(addr) \ | |
| 82 ); | |
| 83 | |
| 84 #define HAL_SPARC_MMCR_CBIR 0x00 // Cache/BusInterfaceUnit Control | |
| 85 #define HAL_SPARC_MMCR_LCR 0x04 // Lock Control Register | |
| 86 #define HAL_SPARC_MMCR_LCSR 0x08 // Lock Control Save Reg | |
| 87 #define HAL_SPARC_MMCR_CSR 0x0c // Cache Status Reg | |
| 88 #define HAL_SPARC_MMCR_RLCR 0x10 // Restore Lock Control Register | |
| 89 | |
| 90 #define HAL_SPARC_MMCR_CBIR_ICE 0x01 // Instruction Cache Enable | |
| 91 #define HAL_SPARC_MMCR_CBIR_GICL 0x02 // Global IC Lock | |
| 92 #define HAL_SPARC_MMCR_CBIR_DCE 0x04 // Data CE | |
| 93 #define HAL_SPARC_MMCR_CBIR_GDCL 0x08 // G Data CE | |
| 94 #define HAL_SPARC_MMCR_CBIR_PBE 0x10 // Prefetch Buffer Enable | |
| 95 #define HAL_SPARC_MMCR_CBIR_WBE 0x20 // Write BE | |
| 96 | |
| 97 | |
| 98 //----------------------------------------------------------------------------- | |
| 99 // Cache dimensions | |
| 100 | |
| 101 // These definitions are suitable for any MB8683x processor: | |
| 102 // The largest possible cachesize and "ways", | |
| 103 // the smallest possible line size. | |
| 104 // This gives values that can correctly manipulate the cache by | |
| 105 // jumping on memory. | |
| 106 | |
| 107 // Data cache | |
| 108 #define HAL_DCACHE_SIZE 0x2000 // Size of data cache in bytes | |
| 109 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 110 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 111 | |
| 112 // Instruction cache | |
| 113 #define HAL_ICACHE_SIZE 0x2000 // Size of cache in bytes | |
| 114 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 115 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 116 | |
| 117 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 118 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 119 | |
| 120 //----------------------------------------------------------------------------- | |
| 121 // Global control of data cache | |
| 122 | |
| 123 // Enable the data cache | |
| 124 #define HAL_DCACHE_ENABLE() CYG_MACRO_START \ | |
| 125 int _v_; \ | |
| 126 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 127 _v_ |= HAL_SPARC_MMCR_CBIR_DCE; \ | |
| 128 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 129 asm volatile ( "nop; nop; nop; nop;" ); \ | |
| 130 CYG_MACRO_END | |
| 131 | |
| 132 // Disable the data cache | |
| 133 #define HAL_DCACHE_DISABLE() CYG_MACRO_START \ | |
| 134 int _v_; \ | |
| 135 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 136 _v_ &=~ HAL_SPARC_MMCR_CBIR_DCE; \ | |
| 137 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 138 asm volatile ( "nop; nop; nop; nop;" ); \ | |
| 139 CYG_MACRO_END | |
| 140 | |
| 141 // Invalidate the entire cache | |
| 142 #define HAL_DCACHE_INVALIDATE_ALL() CYG_MACRO_START \ | |
| 143 asm volatile ( \ | |
| 144 "set 3, %%l0;" \ | |
| 145 "set 0x00001000, %%l1;" \ | |
| 146 "set 0x80001000, %%l2;" \ | |
| 147 "sta %%l0, [ %%l1 ] 0x0e;" \ | |
| 148 "sta %%l0, [ %%l2 ] 0x0e;" \ | |
| 149 "nop;" \ | |
| 150 "nop;" \ | |
| 151 "nop;" \ | |
| 152 "nop" : : : "l0","l1","l2" ); \ | |
| 153 CYG_MACRO_END | |
| 154 | |
| 155 // Synchronize the contents of the cache with memory. | |
| 156 #define HAL_DCACHE_SYNC() CYG_MACRO_START \ | |
| 157 /* read 8k from the ROM; that should do it... */ \ | |
| 158 volatile cyg_uint32 *_p_ = (cyg_uint32 *)0; \ | |
| 159 volatile cyg_uint32 *_q_ = (cyg_uint32 *)HAL_DCACHE_SIZE; \ | |
| 160 volatile cyg_uint32 _tmp_; \ | |
| 161 for ( ; _p_ < _q_; _p_ ++ ) _tmp_ = *_q_; \ | |
| 162 CYG_MACRO_END | |
| 163 | |
| 164 // Query the state of the data cache | |
| 165 #define HAL_DCACHE_IS_ENABLED(_state_) CYG_MACRO_START \ | |
| 166 int _v_; \ | |
| 167 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 168 (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_DCE)); \ | |
| 169 CYG_MACRO_END | |
| 170 | |
| 171 | |
| 172 // Set the data cache refill burst size | |
| 173 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 174 | |
| 175 // Set the data cache write mode | |
| 176 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 177 | |
| 178 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 179 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 180 | |
| 181 // Load the contents of the given address range into the data cache | |
| 182 // and then lock the cache so that it stays there. | |
| 183 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 184 | |
| 185 // Undo a previous lock operation | |
| 186 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 187 | |
| 188 // Unlock entire cache | |
| 189 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 190 | |
| 191 //----------------------------------------------------------------------------- | |
| 192 // Data cache line control | |
| 193 | |
| 194 // Allocate cache lines for the given address range without reading its | |
| 195 // contents from memory. | |
| 196 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 197 | |
| 198 // Write dirty cache lines to memory and invalidate the cache entries | |
| 199 // for the given address range. | |
| 200 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 201 | |
| 202 // Invalidate cache lines in the given range without writing to memory. | |
| 203 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 204 | |
| 205 // Write dirty cache lines to memory for the given address range. | |
| 206 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 207 | |
| 208 // Preread the given range into the cache with the intention of reading | |
| 209 // from it later. | |
| 210 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 211 | |
| 212 // Preread the given range into the cache with the intention of writing | |
| 213 // to it later. | |
| 214 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 215 | |
| 216 // Allocate and zero the cache lines associated with the given range. | |
| 217 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 218 | |
| 219 //----------------------------------------------------------------------------- | |
| 220 // Global control of Instruction cache - use Data cache controls since they | |
| 221 // are not separatable. | |
| 222 | |
| 223 // Enable the data cache | |
| 224 #define HAL_ICACHE_ENABLE() CYG_MACRO_START \ | |
| 225 int _v_; \ | |
| 226 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 227 _v_ |= HAL_SPARC_MMCR_CBIR_ICE; \ | |
| 228 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 229 asm volatile ( "nop; nop; nop; nop;" ); \ | |
| 230 CYG_MACRO_END | |
| 231 | |
| 232 // Disable the data cache | |
| 233 #define HAL_ICACHE_DISABLE() CYG_MACRO_START \ | |
| 234 int _v_; \ | |
| 235 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 236 _v_ &=~ HAL_SPARC_MMCR_CBIR_ICE; \ | |
| 237 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 238 asm volatile ( "nop; nop; nop; nop;" ); \ | |
| 239 CYG_MACRO_END | |
| 240 | |
| 241 // Invalidate the entire cache | |
| 242 #define HAL_ICACHE_INVALIDATE_ALL() CYG_MACRO_START \ | |
| 243 asm volatile ( \ | |
| 244 "set 3, %%l0;" \ | |
| 245 "set 0x00001000, %%l1;" \ | |
| 246 "set 0x80001000, %%l2;" \ | |
| 247 "sta %%l0, [ %%l1 ] 0x0c;" \ | |
| 248 "sta %%l0, [ %%l2 ] 0x0c;" \ | |
| 249 "nop;" \ | |
| 250 "nop;" \ | |
| 251 "nop;" \ | |
| 252 "nop" : : : "l0","l1","l2" ); \ | |
| 253 CYG_MACRO_END | |
| 254 | |
| 255 // Synchronize the contents of the cache with memory. | |
| 256 #define HAL_ICACHE_SYNC() CYG_MACRO_START \ | |
| 257 HAL_DCACHE_SYNC(); /* Ensure data is in memory */ \ | |
| 258 HAL_ICACHE_INVALIDATE_ALL(); /* Pick up new memory contents */ \ | |
| 259 CYG_MACRO_END | |
| 260 | |
| 261 // Query the state of the instruction cache | |
| 262 #define HAL_ICACHE_IS_ENABLED(_state_) CYG_MACRO_START \ | |
| 263 int _v_; \ | |
| 264 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ | |
| 265 (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_ICE)); \ | |
| 266 CYG_MACRO_END | |
| 267 | |
| 268 // Set the instruction cache refill burst size | |
| 269 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 270 | |
| 271 // Load the contents of the given address range into the instruction cache | |
| 272 // and then lock the cache so that it stays there. | |
| 273 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 274 | |
| 275 // Undo a previous lock operation | |
| 276 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 277 | |
| 278 // Unlock entire cache | |
| 279 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 280 | |
| 281 //----------------------------------------------------------------------------- | |
| 282 // Instruction cache line control | |
| 283 | |
| 284 // Invalidate cache lines in the given range without writing to memory. | |
| 285 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 286 | |
| 287 //----------------------------------------------------------------------------- | |
| 288 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 289 // End of hal_cache.h |