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comparison packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @ 2981:3022189df937

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* src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to CP Command Register
author sergeig
date Sun, 12 Dec 2010 11:11:23 +0000
parents 74dbf4c3f2e1
children
comparison
equal deleted inserted replaced
2980:8d5bed76c596 2981:3022189df937
337 cyg_uint32 _lcr; 337 cyg_uint32 _lcr;
338 EPPC *eppc = eppc_base(); 338 EPPC *eppc = eppc_base();
339 volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl; 339 volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl;
340 340
341 if (baud_divisor == 0) return false; 341 if (baud_divisor == 0) return false;
342 // Stop transmitter while changing baud rate
343 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
344 while (eppc->cp_cr & QUICC_SMC_CMD_Go )
345 continue;
346 HAL_IO_BARRIER(); // Inforce I/O ordering
342 // Disable channel during setup 347 // Disable channel during setup
343 ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode 348 ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
344 HAL_IO_BARRIER(); // Inforce I/O ordering 349 HAL_IO_BARRIER(); // Inforce I/O ordering
345 // Disable port interrupts while changing hardware 350 // Disable port interrupts while changing hardware
346 _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) | 351 _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
347 smc_select_stop_bits[new_config->stop] | 352 smc_select_stop_bits[new_config->stop] |
348 smc_select_parity[new_config->parity]; 353 smc_select_parity[new_config->parity];
349 // Stop transmitter while changing baud rate
350 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
351 HAL_IO_BARRIER(); // Inforce I/O ordering 354 HAL_IO_BARRIER(); // Inforce I/O ordering
352 // Set baud rate generator 355 // Set baud rate generator
353 *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); 356 *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
354 357
355 // Enable channel with new configuration 358 // Enable channel with new configuration
356 ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr; 359 ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
357 HAL_IO_BARRIER(); // Inforce I/O ordering 360 HAL_IO_BARRIER(); // Inforce I/O ordering
358 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx; 361 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
362 while (eppc->cp_cr & QUICC_SMC_CMD_Go )
363 continue;
359 if (new_config != &chan->config) { 364 if (new_config != &chan->config) {
360 chan->config = *new_config; 365 chan->config = *new_config;
361 } 366 }
362 return true; 367 return true;
363 } 368 }
451 /* 456 /*
452 * Reset Rx & Tx params 457 * Reset Rx & Tx params
453 */ 458 */
454 HAL_IO_BARRIER(); // Inforce I/O ordering 459 HAL_IO_BARRIER(); // Inforce I/O ordering
455 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; 460 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
461 while (eppc->cp_cr & QUICC_SMC_CMD_Go )
462 continue;
456 HAL_IO_BARRIER(); // Inforce I/O ordering 463 HAL_IO_BARRIER(); // Inforce I/O ordering
457 /* 464 /*
458 * Clear any previous events. Enable interrupts. 465 * Clear any previous events. Enable interrupts.
459 * (Section 16.15.7.14 and 16.15.7.15) 466 * (Section 16.15.7.14 and 16.15.7.15)
460 */ 467 */
489 /* 496 /*
490 * Init Rx & Tx params for SCCX 497 * Init Rx & Tx params for SCCX
491 */ 498 */
492 HAL_IO_BARRIER(); // Inforce I/O ordering 499 HAL_IO_BARRIER(); // Inforce I/O ordering
493 eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY; 500 eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
494 501 while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
502 continue;
495 HAL_IO_BARRIER(); // Inforce I/O ordering 503 HAL_IO_BARRIER(); // Inforce I/O ordering
496 regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx 504 regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx
497 if (new_config != &chan->config) { 505 if (new_config != &chan->config) {
498 chan->config = *new_config; 506 chan->config = *new_config;
499 } 507 }
601 /* 609 /*
602 * Reset Rx & Tx params 610 * Reset Rx & Tx params
603 */ 611 */
604 HAL_IO_BARRIER(); // Inforce I/O ordering 612 HAL_IO_BARRIER(); // Inforce I/O ordering
605 eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; 613 eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
614 while (eppc->cp_cr & QUICC_SMC_CMD_Go )
615 continue;
606 /* 616 /*
607 * Clear any previous events. Enable interrupts. 617 * Clear any previous events. Enable interrupts.
608 * (Section 16.15.7.14 and 16.15.7.15) 618 * (Section 16.15.7.14 and 16.15.7.15)
609 */ 619 */
610 HAL_IO_BARRIER(); // Inforce I/O ordering 620 HAL_IO_BARRIER(); // Inforce I/O ordering