Mercurial > ecos
changeset 2981:3022189df937
* src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to
CP Command Register
| author | sergeig |
|---|---|
| date | Sun, 12 Dec 2010 11:11:23 +0000 |
| parents | 8d5bed76c596 |
| children | 2155db306734 |
| files | packages/devs/serial/powerpc/quicc/current/ChangeLog packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c |
| diffstat | 2 files changed, 18 insertions(+), 3 deletions(-) [+] |
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--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog +++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog @@ -1,3 +1,8 @@ +2010-12-06 Mark Retallack <mark.retallack@siemens.com> + + * src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to + CP Command Register + 2006-01-27 Will Wagner <willw@carallon.com> * src/quicc_smc_serial.h: Removed unused structure
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c +++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @@ -339,6 +339,11 @@ quicc_smc_serial_config_port(serial_chan volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl; if (baud_divisor == 0) return false; + // Stop transmitter while changing baud rate + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; + HAL_IO_BARRIER(); // Inforce I/O ordering // Disable channel during setup ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode HAL_IO_BARRIER(); // Inforce I/O ordering @@ -346,8 +351,6 @@ quicc_smc_serial_config_port(serial_chan _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) | smc_select_stop_bits[new_config->stop] | smc_select_parity[new_config->parity]; - // Stop transmitter while changing baud rate - eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx; HAL_IO_BARRIER(); // Inforce I/O ordering // Set baud rate generator *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); @@ -356,6 +359,8 @@ quicc_smc_serial_config_port(serial_chan ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr; HAL_IO_BARRIER(); // Inforce I/O ordering eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; if (new_config != &chan->config) { chan->config = *new_config; } @@ -453,6 +458,8 @@ quicc_smc_serial_init_info(quicc_sxx_ser */ HAL_IO_BARRIER(); // Inforce I/O ordering eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; HAL_IO_BARRIER(); // Inforce I/O ordering /* * Clear any previous events. Enable interrupts. @@ -491,7 +498,8 @@ quicc_scc_serial_config_port(serial_chan */ HAL_IO_BARRIER(); // Inforce I/O ordering eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY; - + while (eppc->cp_cr & QUICC_CPM_CR_BUSY ) + continue; HAL_IO_BARRIER(); // Inforce I/O ordering regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx if (new_config != &chan->config) { @@ -603,6 +611,8 @@ quicc_scc_serial_init_info(quicc_sxx_ser */ HAL_IO_BARRIER(); // Inforce I/O ordering eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; + while (eppc->cp_cr & QUICC_SMC_CMD_Go ) + continue; /* * Clear any previous events. Enable interrupts. * (Section 16.15.7.14 and 16.15.7.15)