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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 24:306eee292492 ecos-sw-1999-07-16

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Merge from eCos master repository on 1999-07-16-05:47:06-BST
author jlarmour
date Fri, 16 Jul 1999 21:54:32 +0000
parents 7253dcc42a09
children c38311975d4f
comparison
equal deleted inserted replaced
23:8883a9947b66 24:306eee292492
50 #include <pkgconf/hal.h> 50 #include <pkgconf/hal.h>
51 #include <cyg/infra/cyg_type.h> 51 #include <cyg/infra/cyg_type.h>
52 52
53 #include <cyg/hal/var_cache.h> 53 #include <cyg/hal/var_cache.h>
54 54
55 // Use this macro to allow the assembler to accept "cache" instructions,
56 // which are MIPS ISA 3. This is useful if someone is compiling
57 // with -mips2, but the architecture is really MIPS ISA 3.
58
59 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( ".set mips" ## #_isal_ )
60
61
55 //============================================================================= 62 //=============================================================================
56 // Default Implementation. This uses the standard MIPS CP0 registers and 63 // Default Implementation. This uses the standard MIPS CP0 registers and
57 // cache instructions. Note that not all variants will have all of the 64 // cache instructions. Note that not all variants will have all of the
58 // functionality defined here. 65 // functionality defined here.
59 66
111 #define HAL_DCACHE_SYNC() \ 118 #define HAL_DCACHE_SYNC() \
112 { \ 119 { \
113 register CYG_ADDRESS _baddr_ = 0x80000000; \ 120 register CYG_ADDRESS _baddr_ = 0x80000000; \
114 register CYG_ADDRESS _addr_ = 0x80000000; \ 121 register CYG_ADDRESS _addr_ = 0x80000000; \
115 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ 122 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
116 register CYG_WORD _state_; \ 123 _HAL_ASM_SET_MIPS_ISA(3); \
117 HAL_DCACHE_IS_ENABLED( _state_ ); \ 124 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
118 if( _state_ ) \ 125 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \
119 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 126 _HAL_ASM_SET_MIPS_ISA(0); \
120 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \
121 } 127 }
122 #endif 128 #endif
123 129
124 // Set the data cache refill burst size 130 // Set the data cache refill burst size
125 //#define HAL_DCACHE_BURST_SIZE(_size_) 131 //#define HAL_DCACHE_BURST_SIZE(_size_)
139 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 145 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
140 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 146 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
141 register CYG_WORD _size_ = (_asize_); \ 147 register CYG_WORD _size_ = (_asize_); \
142 register CYG_WORD _state_; \ 148 register CYG_WORD _state_; \
143 HAL_DCACHE_IS_ENABLED( _state_ ); \ 149 HAL_DCACHE_IS_ENABLED( _state_ ); \
144 if( _state_ ) \ 150 if( _state_ ) { \
151 _HAL_ASM_SET_MIPS_ISA(3); \
145 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 152 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
146 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \ 153 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \
154 _HAL_ASM_SET_MIPS_ISA(0); \
155 } \
147 CYG_MACRO_END 156 CYG_MACRO_END
148 #endif 157 #endif
149 158
150 // Undo a previous lock operation. 159 // Undo a previous lock operation.
151 // Do this by flushing the cache, which is defined to clear the lock bit. 160 // Do this by flushing the cache, which is defined to clear the lock bit.
170 // Write dirty cache lines to memory and invalidate the cache entries 179 // Write dirty cache lines to memory and invalidate the cache entries
171 // for the given address range. 180 // for the given address range.
172 // This uses the hit-writeback-invalidate cache operation. 181 // This uses the hit-writeback-invalidate cache operation.
173 #ifndef HAL_DCACHE_FLUSH_DEFINED 182 #ifndef HAL_DCACHE_FLUSH_DEFINED
174 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ 183 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
175 { \ 184 CYG_MACRO_START \
176 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 185 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
177 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 186 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
178 register CYG_WORD _size_ = (_asize_); \ 187 register CYG_WORD _size_ = (_asize_); \
179 register CYG_WORD _state_; \ 188 register CYG_WORD _state_; \
180 HAL_DCACHE_IS_ENABLED( _state_ ); \ 189 HAL_DCACHE_IS_ENABLED( _state_ ); \
181 if( _state_ ) \ 190 if( _state_ ) { \
191 _HAL_ASM_SET_MIPS_ISA(3); \
182 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 192 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
183 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \ 193 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \
184 } 194 _HAL_ASM_SET_MIPS_ISA(0); \
195 } \
196 CYG_MACRO_END
185 #endif 197 #endif
186 198
187 // Invalidate cache lines in the given range without writing to memory. 199 // Invalidate cache lines in the given range without writing to memory.
188 // This uses the hit-invalidate cache operation. 200 // This uses the hit-invalidate cache operation.
189 #ifndef HAL_DCACHE_INVALIDATE_DEFINED 201 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
190 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ 202 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
191 { \ 203 { \
192 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 204 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
193 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 205 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
194 register CYG_WORD _size_ = (_asize_); \ 206 register CYG_WORD _size_ = (_asize_); \
195 register CYG_WORD _state_; \ 207 _HAL_ASM_SET_MIPS_ISA(3); \
196 HAL_DCACHE_IS_ENABLED( _state_ ); \ 208 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
197 if( _state_ ) \ 209 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \
198 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 210 _HAL_ASM_SET_MIPS_ISA(0); \
199 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \
200 } 211 }
201 #endif 212 #endif
202 213
203 // Write dirty cache lines to memory for the given address range. 214 // Write dirty cache lines to memory for the given address range.
204 // This uses the hit-writeback cache operation. 215 // This uses the hit-writeback cache operation.
205 #ifndef HAL_DCACHE_STORE_DEFINED 216 #ifndef HAL_DCACHE_STORE_DEFINED
206 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \ 217 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
207 { \ 218 CYG_MACRO_START \
208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 219 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 220 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
210 register CYG_WORD _size_ = (_asize_); \ 221 register CYG_WORD _size_ = (_asize_); \
211 register CYG_WORD _state_; \ 222 register CYG_WORD _state_; \
212 HAL_DCACHE_IS_ENABLED( _state_ ); \ 223 HAL_DCACHE_IS_ENABLED( _state_ ); \
213 if( _state_ ) \ 224 if( _state_ ) { \
225 _HAL_ASM_SET_MIPS_ISA(3); \
214 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 226 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
215 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \ 227 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \
216 } 228 _HAL_ASM_SET_MIPS_ISA(0); \
229 } \
230 CYG_MACRO_END
217 #endif 231 #endif
218 232
219 // Preread the given range into the cache with the intention of reading 233 // Preread the given range into the cache with the intention of reading
220 // from it later. 234 // from it later.
221 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) 235 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
246 #endif 260 #endif
247 261
248 // Invalidate the entire cache 262 // Invalidate the entire cache
249 // This uses the index-invalidate cache operation. 263 // This uses the index-invalidate cache operation.
250 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED 264 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
251 #define HAL_ICACHE_INVALIDATE_ALL() \ 265 #define HAL_ICACHE_INVALIDATE_ALL() \
252 { \ 266 { \
253 register CYG_ADDRESS _baddr_ = 0x80000000; \ 267 register CYG_ADDRESS _baddr_ = 0x80000000; \
254 register CYG_ADDRESS _addr_ = 0x80000000; \ 268 register CYG_ADDRESS _addr_ = 0x80000000; \
255 register CYG_WORD _state_; \ 269 _HAL_ASM_SET_MIPS_ISA(3); \
256 HAL_ICACHE_IS_ENABLED( _state_ ); \ 270 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
257 if( _state_ ) \ 271 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \
258 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 272 _HAL_ASM_SET_MIPS_ISA(0); \
259 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \
260 } 273 }
261 #endif 274 #endif
262 275
263 // Synchronize the contents of the cache with memory. 276 // Synchronize the contents of the cache with memory.
264 // Simply force the cache to reload. 277 // Simply force the cache to reload.
278 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 291 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
279 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 292 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
280 register CYG_WORD _size_ = (_asize_); \ 293 register CYG_WORD _size_ = (_asize_); \
281 register CYG_WORD _state_; \ 294 register CYG_WORD _state_; \
282 HAL_ICACHE_IS_ENABLED( _state_ ); \ 295 HAL_ICACHE_IS_ENABLED( _state_ ); \
283 if( _state_ ) \ 296 if( _state_ ) { \
297 _HAL_ASM_SET_MIPS_ISA(3); \
284 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 298 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
285 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \ 299 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \
300 _HAL_ASM_SET_MIPS_ISA(0); \
301 } \
286 CYG_MACRO_END 302 CYG_MACRO_END
287 #endif 303 #endif
288 304
289 // Undo a previous lock operation. 305 // Undo a previous lock operation.
290 // Do this by invalidating the cache, which is defined to clear the lock bit. 306 // Do this by invalidating the cache, which is defined to clear the lock bit.
305 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ 321 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
306 { \ 322 { \
307 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 323 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
308 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 324 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
309 register CYG_WORD _size_ = (_asize_); \ 325 register CYG_WORD _size_ = (_asize_); \
310 register CYG_WORD _state_; \ 326 _HAL_ASM_SET_MIPS_ISA(3); \
311 HAL_ICACHE_IS_ENABLED( _state_ ); \ 327 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
312 if( _state_ ) \ 328 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \
313 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 329 _HAL_ASM_SET_MIPS_ISA(0); \
314 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \
315 } 330 }
316 #endif 331 #endif
317 332
318 //----------------------------------------------------------------------------- 333 //-----------------------------------------------------------------------------
319 // Check that a supported configuration has actually defined some macros. 334 // Check that a supported configuration has actually defined some macros.