ecos: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 24:306eee292492 ecos-sw-1999-07-16

Merge from eCos master repository on 1999-07-16-05:47:06-BST

author	jlarmour
date	Fri, 16 Jul 1999 21:54:32 +0000
parents	7253dcc42a09
children	c38311975d4f

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 //####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	12 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	13 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	14 // The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	15 // Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	16 // compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	17 // http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	18 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	19 // Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	21 // License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	22 // the License.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	23 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	24 // The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	25 // September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	26 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	27 // The Initial Developer of the Original Code is Cygnus. Portions created
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	29 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	30 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	31 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	32 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	33 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	34 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	35 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	36 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	42 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	46 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	53 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	54
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	55 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	56 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	57 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	58
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	59 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( ".set mips" ## #_isal_ )
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	60
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	61
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	63 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	64 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	65 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	67 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	68 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	69 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	70 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	71
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	72 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	73
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	74 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	81 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	87 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	88
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	93 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	94 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	96 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	99 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	101 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	102
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	103 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	104 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	105 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	106
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	107 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	108 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	109 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	110 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	111 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	112 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	113 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	114
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	116 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	117 #ifndef HAL_DCACHE_SYNC_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	118 #define HAL_DCACHE_SYNC() \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	119 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	120 register CYG_ADDRESS _baddr_ = 0x80000000; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	121 register CYG_ADDRESS _addr_ = 0x80000000; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	122 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	123 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	124 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	125 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	126 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	127 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	128 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	132
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	133 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	140 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	141 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	142 #ifndef HAL_DCACHE_LOCK_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	143 #define HAL_DCACHE_LOCK(_base_, _asize_) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	144 CYG_MACRO_START \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	145 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	146 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	147 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	148 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	149 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	150 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	151 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	152 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	153 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	154 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	155 } \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	156 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	157 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	158
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	159 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	160 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	161 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	162 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	163 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	164 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	165
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	166 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	167 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	168 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	169 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	170 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	171
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	172 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	173 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	175 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	178
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	179 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	180 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	181 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	182 #ifndef HAL_DCACHE_FLUSH_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	183 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	184 CYG_MACRO_START \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	185 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	186 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	187 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	188 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	189 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	190 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	191 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	192 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	193 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	194 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	195 } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	196 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	197 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	198
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	199 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	200 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	201 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	202 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	203 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	204 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	205 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	206 register CYG_WORD _size_ = (_asize_); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	207 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	208 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	209 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	210 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	211 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	212 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	213
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	214 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	215 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	216 #ifndef HAL_DCACHE_STORE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	217 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	218 CYG_MACRO_START \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	219 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	220 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	221 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	222 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	223 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	224 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	225 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	226 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	227 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	228 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	229 } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	230 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	231 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	232
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	233 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	234 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	237 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	238 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	239 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	240
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	241 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	242 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	243
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	244 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	245 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	246
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	247 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	248 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	249 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	250 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	251 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	252
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	253 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	254 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	255 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	256 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	258 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	259 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	260 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	261
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	262 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	263 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	264 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	265 #define HAL_ICACHE_INVALIDATE_ALL() \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	266 { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	267 register CYG_ADDRESS _baddr_ = 0x80000000; \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	268 register CYG_ADDRESS _addr_ = 0x80000000; \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	269 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	270 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	271 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	272 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	273 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	274 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	275
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	276 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	277 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	278 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	279 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	280 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	287 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	288 #ifndef HAL_ICACHE_LOCK_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	289 #define HAL_ICACHE_LOCK(_base_, _asize_) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	290 CYG_MACRO_START \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	291 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	292 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	293 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	294 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	295 HAL_ICACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	296 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	297 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	298 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	299 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	300 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	301 } \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	302 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	303 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	305 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	306 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	307 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	308 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	309 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	310 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	311
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	312 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	313 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	314
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	319 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	320 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	321 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	322 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	323 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	324 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	325 register CYG_WORD _size_ = (_asize_); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	326 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	327 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	328 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	329 _HAL_ASM_SET_MIPS_ISA(0); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	331 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	332
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	333 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	334 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	335
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	336 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	337
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	338 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	339
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	340 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	341
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	342 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	343 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	344 // End of hal_cache.h

Mercurial > ecos

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 24:306eee292492 ecos-sw-1999-07-16