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comparison packages/hal/sh/arch/current/include/hal_intr.h @ 126:518f42066aba ecos-sw-2000-09-19

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Merge from eCos master repository on 2000-09-19-06:25:26-BST
author jlarmour
date Tue, 19 Sep 2000 05:53:51 +0000
parents 0ec04793409a
children 0c2b7be0d798
comparison
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125:b4407dc7f59d 126:518f42066aba
414 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \ 414 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
415 CYG_MACRO_END 415 CYG_MACRO_END
416 416
417 417
418 //-------------------------------------------------------------------------- 418 //--------------------------------------------------------------------------
419 // Interrupt controller access 419 // Interrupt controller(s) access
420 // 420 //
421 // Note: These macros work only on a unit basis ; if one source in a 421
422 // unit (such as SCI) is unmasked, all sources of that unit get 422 externC void hal_interrupt_set_level(int, int);
423 // unmasked. Finer control must be done in the driver/apps. 423 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
424 424 hal_interrupt_set_level(_vector_, _level_);
425 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING 425
426 externC cyg_uint8 cyg_hal_ILVL_table[]; 426 externC void hal_interrupt_mask(int);
427 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \ 427 #define HAL_INTERRUPT_MASK( _vector_ ) \
428 /* Update the ILVL table, so it is easy for the interrupt entry */ \ 428 hal_interrupt_mask(_vector_);
429 /* code to find out the level of a given interrupt source. */ \ 429
430 cyg_hal_ILVL_table[(_vector_)] = (_level_) 430 externC void hal_interrupt_unmask(int);
431 #else 431 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
432 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) 432 hal_interrupt_unmask(_vector_);
433 #endif 433
434 434 externC void hal_interrupt_acknowledge(int);
435 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ 435 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
436 CYG_MACRO_START \ 436 hal_interrupt_acknowledge(_vector_);
437 cyg_uint16 iprX; \ 437
438 \ 438 externC void hal_interrupt_configure(int, int, int);
439 CYG_ASSERT((0 <= (_level_) && 15 >= (_level_)), "Illegal level"); \ 439 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
440 CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (_vector_) \ 440 hal_interrupt_configure(_vector_, _level_, _up_);
441 && CYGNUM_HAL_ISR_MAX >= (_vector_)), "Illegal vector"); \
442 \
443 HAL_UPDATE_ILVL_TABLE(_vector_, _level_); \
444 \
445 switch( (_vector_) ) { \
446 case CYGNUM_HAL_INTERRUPT_NMI: \
447 /* fall through */ \
448 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
449 /* Cannot change levels */ \
450 break; \
451 \
452 /* IPRA */ \
453 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0: \
454 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
455 iprX &= ~CYGARC_REG_IPRA_TMU0_MASK; \
456 iprX |= (_level_)*CYGARC_REG_IPRA_TMU0_PRI1; \
457 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
458 break; \
459 case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1: \
460 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
461 iprX &= ~CYGARC_REG_IPRA_TMU1_MASK; \
462 iprX |= (_level_)*CYGARC_REG_IPRA_TMU1_PRI1; \
463 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
464 break; \
465 case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2: \
466 case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2: \
467 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
468 iprX &= ~CYGARC_REG_IPRA_TMU2_MASK; \
469 iprX |= (_level_)*CYGARC_REG_IPRA_TMU2_PRI1; \
470 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
471 break; \
472 case CYGNUM_HAL_INTERRUPT_RTC_ATI: \
473 case CYGNUM_HAL_INTERRUPT_RTC_PRI: \
474 case CYGNUM_HAL_INTERRUPT_RTC_CUI: \
475 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
476 iprX &= ~CYGARC_REG_IPRA_RTC_MASK; \
477 iprX |= (_level_)*CYGARC_REG_IPRA_RTC_PRI1; \
478 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
479 break; \
480 \
481 /* IPRB */ \
482 case CYGNUM_HAL_INTERRUPT_SCI_ERI: \
483 case CYGNUM_HAL_INTERRUPT_SCI_RXI: \
484 case CYGNUM_HAL_INTERRUPT_SCI_TXI: \
485 case CYGNUM_HAL_INTERRUPT_SCI_TEI: \
486 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
487 iprX &= ~CYGARC_REG_IPRB_SCI_MASK; \
488 iprX |= (_level_)*CYGARC_REG_IPRB_SCI_PRI1; \
489 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
490 break; \
491 case CYGNUM_HAL_INTERRUPT_WDT_ITI: \
492 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
493 iprX &= ~CYGARC_REG_IPRB_WDT_MASK; \
494 iprX |= (_level_)*CYGARC_REG_IPRB_WDT_PRI1; \
495 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
496 break; \
497 case CYGNUM_HAL_INTERRUPT_REF_RCMI: \
498 case CYGNUM_HAL_INTERRUPT_REF_ROVI: \
499 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
500 iprX &= ~CYGARC_REG_IPRB_REF_MASK; \
501 iprX |= (_level_)*CYGARC_REG_IPRB_REF_PRI1; \
502 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
503 break; \
504 \
505 /* IPRC */ \
506 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \
507 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \
508 iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK; \
509 iprX |= (_level_)*CYGARC_REG_IPRC_IRQ0_PRI1; \
510 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \
511 break; \
512 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \
513 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \
514 iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK; \
515 iprX |= (_level_)*CYGARC_REG_IPRC_IRQ1_PRI1; \
516 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \
517 break; \
518 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \
519 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \
520 iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK; \
521 iprX |= (_level_)*CYGARC_REG_IPRC_IRQ2_PRI1; \
522 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \
523 break; \
524 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \
525 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \
526 iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK; \
527 iprX |= (_level_)*CYGARC_REG_IPRC_IRQ3_PRI1; \
528 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \
529 break; \
530 \
531 /* IPRD */ \
532 case CYGNUM_HAL_INTERRUPT_PINT_PINT07: \
533 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \
534 iprX &= ~CYGARC_REG_IPRD_PINT07_MASK; \
535 iprX |= (_level_)*CYGARC_REG_IPRD_PINT07_PRI1; \
536 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \
537 break; \
538 case CYGNUM_HAL_INTERRUPT_PINT_PINT8F: \
539 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \
540 iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK; \
541 iprX |= (_level_)*CYGARC_REG_IPRD_PINT8F_PRI1; \
542 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \
543 break; \
544 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \
545 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \
546 iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK; \
547 iprX |= (_level_)*CYGARC_REG_IPRD_IRQ5_PRI1; \
548 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \
549 break; \
550 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \
551 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \
552 iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK; \
553 iprX |= (_level_)*CYGARC_REG_IPRD_IRQ4_PRI1; \
554 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \
555 break; \
556 \
557 /* IPRE */ \
558 case CYGNUM_HAL_INTERRUPT_DMAC_DEI0: \
559 case CYGNUM_HAL_INTERRUPT_DMAC_DEI1: \
560 case CYGNUM_HAL_INTERRUPT_DMAC_DEI2: \
561 case CYGNUM_HAL_INTERRUPT_DMAC_DEI3: \
562 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \
563 iprX &= ~CYGARC_REG_IPRE_DMAC_MASK; \
564 iprX |= (_level_)*CYGARC_REG_IPRE_DMAC_PRI1; \
565 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \
566 break; \
567 case CYGNUM_HAL_INTERRUPT_IRDA_ERI1: \
568 case CYGNUM_HAL_INTERRUPT_IRDA_RXI1: \
569 case CYGNUM_HAL_INTERRUPT_IRDA_BRI1: \
570 case CYGNUM_HAL_INTERRUPT_IRDA_TXI1: \
571 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \
572 iprX &= ~CYGARC_REG_IPRE_IRDA_MASK; \
573 iprX |= (_level_)*CYGARC_REG_IPRE_IRDA_PRI1; \
574 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \
575 break; \
576 case CYGNUM_HAL_INTERRUPT_SCIF_ERI2: \
577 case CYGNUM_HAL_INTERRUPT_SCIF_RXI2: \
578 case CYGNUM_HAL_INTERRUPT_SCIF_BRI2: \
579 case CYGNUM_HAL_INTERRUPT_SCIF_TXI2: \
580 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \
581 iprX &= ~CYGARC_REG_IPRE_SCIF_MASK; \
582 iprX |= (_level_)*CYGARC_REG_IPRE_SCIF_PRI1; \
583 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \
584 break; \
585 case CYGNUM_HAL_INTERRUPT_ADC_ADI: \
586 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \
587 iprX &= ~CYGARC_REG_IPRE_ADC_MASK; \
588 iprX |= (_level_)*CYGARC_REG_IPRE_ADC_PRI1; \
589 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \
590 break; \
591 \
592 /* IPRF */ \
593 case CYGNUM_HAL_INTERRUPT_LCDC_LCDI: \
594 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); \
595 iprX &= ~CYGARC_REG_IPRF_LCDI_MASK; \
596 iprX |= (_level_)*CYGARC_REG_IPRF_LCDI_PRI1; \
597 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); \
598 break; \
599 case CYGNUM_HAL_INTERRUPT_PCC_PCC0: \
600 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); \
601 iprX &= ~CYGARC_REG_IPRF_PCC0_MASK; \
602 iprX |= (_level_)*CYGARC_REG_IPRF_PCC0_PRI1; \
603 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); \
604 break; \
605 case CYGNUM_HAL_INTERRUPT_PCC_PCC1: \
606 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX); \
607 iprX &= ~CYGARC_REG_IPRF_PCC1_MASK; \
608 iprX |= (_level_)*CYGARC_REG_IPRF_PCC1_PRI1; \
609 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX); \
610 break; \
611 \
612 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
613 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
614 /* Do nothing for these reserved vectors. */ \
615 break; \
616 } \
617 CYG_MACRO_END
618
619 #define HAL_INTERRUPT_MASK( _vector_ ) \
620 CYG_MACRO_START \
621 switch( (_vector_) ) { \
622 case CYGNUM_HAL_INTERRUPT_NMI: \
623 /* fall through */ \
624 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
625 /* Can only be masked by fiddling Imask in SR. */ \
626 break; \
627 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: \
628 HAL_INTERRUPT_SET_LEVEL((_vector_), 0); \
629 break; \
630 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
631 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
632 /* Do nothing for these reserved vectors. */ \
633 break; \
634 default: \
635 CYG_FAIL("Unknown interrupt vector"); \
636 break; \
637 } \
638 CYG_MACRO_END
639
640 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
641 CYG_MACRO_START \
642 switch( (_vector_) ) { \
643 case CYGNUM_HAL_INTERRUPT_NMI: \
644 /* fall through */ \
645 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
646 /* Can only be unmasked by fiddling Imask in SR. */ \
647 break; \
648 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: \
649 HAL_INTERRUPT_SET_LEVEL((_vector_), 1); \
650 break; \
651 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
652 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
653 /* Do nothing for these reserved vectors. */ \
654 break; \
655 default: \
656 CYG_FAIL("Unknown interrupt vector"); \
657 break; \
658 } \
659 CYG_MACRO_END
660
661 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
662 CYG_MACRO_START \
663 if ( (_vector_) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 \
664 && (_vector_) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { \
665 \
666 cyg_uint8 irr0; \
667 \
668 HAL_READ_UINT8(CYGARC_REG_IRR0, irr0); \
669 switch ( _vector_ ) { \
670 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \
671 irr0 &= ~CYGARC_REG_IRR0_IRQ0; \
672 break; \
673 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \
674 irr0 &= ~CYGARC_REG_IRR0_IRQ1; \
675 break; \
676 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \
677 irr0 &= ~CYGARC_REG_IRR0_IRQ2; \
678 break; \
679 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \
680 irr0 &= ~CYGARC_REG_IRR0_IRQ3; \
681 break; \
682 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \
683 irr0 &= ~CYGARC_REG_IRR0_IRQ4; \
684 break; \
685 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \
686 irr0 &= ~CYGARC_REG_IRR0_IRQ5; \
687 break; \
688 } \
689 HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0); \
690 } \
691 CYG_MACRO_END
692
693 // Note: The PINTs can be masked and configured individually, even
694 // though there are only two vectors. Maybe add some fake vectors just
695 // for masking/configuring?
696 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
697 CYG_MACRO_START \
698 if ( (_vector_) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 \
699 && (_vector_) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { \
700 \
701 cyg_uint16 icr1, ss, mask; \
702 ss = 0; \
703 mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL; \
704 if (_up_) ss |= CYGARC_REG_ICR1_SENSE_UP; \
705 if (_level_) ss |= CYGARC_REG_ICR1_SENSE_LEVEL; \
706 CYG_ASSERT(!(_up_ && _level_), "Cannot trigger on high level!"); \
707 \
708 switch( (_vector_) ) { \
709 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \
710 ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; \
711 mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; \
712 break; \
713 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \
714 ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; \
715 mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; \
716 break; \
717 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \
718 ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; \
719 mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; \
720 break; \
721 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \
722 ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; \
723 mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; \
724 break; \
725 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \
726 ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; \
727 mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; \
728 break; \
729 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \
730 ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; \
731 mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; \
732 break; \
733 } \
734 \
735 HAL_READ_UINT16(CYGARC_REG_ICR1, icr1); \
736 icr1 &= ~mask; \
737 icr1 |= ss; \
738 HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1); \
739 } \
740 CYG_MACRO_END
741 441
742 //-------------------------------------------------------------------------- 442 //--------------------------------------------------------------------------
743 // Clock control 443 // Clock control
744 444
745 // Using TMU counter 0, clocked at p/4, with peripheral clock 445 // Using TMU counter 0, clocked at p/4, with peripheral clock