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annotate packages/hal/sh/arch/current/include/hal_intr.h @ 126:518f42066aba ecos-sw-2000-09-19

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Merge from eCos master repository on 2000-09-19-06:25:26-BST
author jlarmour
date Tue, 19 Sep 2000 05:53:51 +0000
parents 0ec04793409a
children 0c2b7be0d798
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors: jskov,
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39 // Date: 1999-04-24
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40 // Purpose: Define Interrupt support
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // interrupts and the clock.
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43 //
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44 // Usage:
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45 // #include <cyg/hal/hal_intr.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #include <pkgconf/hal.h>
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54 #include CYGBLD_HAL_CPU_MODULES_H // INTC module selection
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56 // More include statements below. First part of this file must be
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57 // usable for both assembly and C files, so only use defines here.
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58
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59 //--------------------------------------------------------------------------
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60 // SH3 exception vectors. These correspond to VSRs and are the values
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61 // to use for HAL_VSR_GET/SET
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62 //
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63 // Note that exceptions are decoded - there is a VSR slot for each exception
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64 // source, while interrupts are handled via the same VSR.
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66 #define CYGNUM_HAL_VECTOR_POWERON 0 // power-on
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67 #define CYGNUM_HAL_VECTOR_RESET 1 // reset
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68 #define CYGNUM_HAL_VECTOR_TLBMISS_ACCESS 2 // TLB-miss/invalid load
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69 #define CYGNUM_HAL_VECTOR_TLBMISS_WRITE 3 // TLB-miss/invalid store
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70 #define CYGNUM_HAL_VECTOR_INITIAL_WRITE 4 // initial page write
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71 #define CYGNUM_HAL_VECTOR_TLBERROR_ACCESS 5 // TLB prot violation l
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72 #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE 6 // TLB prot violation s
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73 #define CYGNUM_HAL_VECTOR_DATA_ACCESS 7 // address error (load)
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74 #define CYGNUM_HAL_VECTOR_DATA_WRITE 8 // address error (store)
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75 // define CYGNUM_HAL_VECTOR_RESERVED_9 9
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76 // define CYGNUM_HAL_VECTOR_RESERVED_10 10
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77 #define CYGNUM_HAL_VECTOR_TRAP 11 // unconditional trap
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78 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 12 // reserved instruction
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79 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 13
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80 // illegal instruction in delay slot
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81 // define CYGNUM_HAL_VECTOR_RESERVED_14 14
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82 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 15 // user breakpoint
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83
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84 #define CYG_VECTOR_IS_INTERRUPT(v) \
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85 (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v))
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87 #define CYGNUM_HAL_VECTOR_INTERRUPT 16 // all interrupts
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88
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89 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON
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90 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT
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91 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
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92
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93 #define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1)
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96
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97 // The decoded interrupts.
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98 #define CYGNUM_HAL_INTERRUPT_NMI 0
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99 #define CYGNUM_HAL_INTERRUPT_RESERVED_1E0 1
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100 #define CYGNUM_HAL_INTERRUPT_LVL0 2
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101 #define CYGNUM_HAL_INTERRUPT_LVL1 3
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102 #define CYGNUM_HAL_INTERRUPT_LVL2 4
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103 #define CYGNUM_HAL_INTERRUPT_LVL3 5
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104 #define CYGNUM_HAL_INTERRUPT_LVL4 6
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105 #define CYGNUM_HAL_INTERRUPT_LVL5 7
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106 #define CYGNUM_HAL_INTERRUPT_LVL6 8
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107 #define CYGNUM_HAL_INTERRUPT_LVL7 9
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108 #define CYGNUM_HAL_INTERRUPT_LVL8 10
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109 #define CYGNUM_HAL_INTERRUPT_LVL9 11
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110 #define CYGNUM_HAL_INTERRUPT_LVL10 12
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111 #define CYGNUM_HAL_INTERRUPT_LVL11 13
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112 #define CYGNUM_HAL_INTERRUPT_LVL12 14
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113 #define CYGNUM_HAL_INTERRUPT_LVL13 15
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114 #define CYGNUM_HAL_INTERRUPT_LVL14 16
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115 #define CYGNUM_HAL_INTERRUPT_RESERVED_3E0 17
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116 #define CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 18
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117 #define CYGNUM_HAL_INTERRUPT_TMU1_TUNI1 19
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118 #define CYGNUM_HAL_INTERRUPT_TMU2_TUNI2 20
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119 #define CYGNUM_HAL_INTERRUPT_TMU2_TICPI2 21
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120 #define CYGNUM_HAL_INTERRUPT_RTC_ATI 22
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121 #define CYGNUM_HAL_INTERRUPT_RTC_PRI 23
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122 #define CYGNUM_HAL_INTERRUPT_RTC_CUI 24
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123 #define CYGNUM_HAL_INTERRUPT_SCI_ERI 25
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124 #define CYGNUM_HAL_INTERRUPT_SCI_RXI 26
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125 #define CYGNUM_HAL_INTERRUPT_SCI_TXI 27
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126 #define CYGNUM_HAL_INTERRUPT_SCI_TEI 28
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127 #define CYGNUM_HAL_INTERRUPT_WDT_ITI 29
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128 #define CYGNUM_HAL_INTERRUPT_REF_RCMI 30
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129 #define CYGNUM_HAL_INTERRUPT_REF_ROVI 31
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130
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131 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI
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132
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133 //----------------------------------------------------------------------------
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134 // Additional vectors provided by INTC V2
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135
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136 //#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME
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137 #define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32
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138 #define CYGNUM_HAL_INTERRUPT_HUDI_HUDI 33
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139 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 34
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140 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 35
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141 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 36
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142 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 37
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143 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 38
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144 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 39
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145 #define CYGNUM_HAL_INTERRUPT_RESERVED_6C0 40
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146 #define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41
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147 #define CYGNUM_HAL_INTERRUPT_PINT_PINT07 42
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148 #define CYGNUM_HAL_INTERRUPT_PINT_PINT8F 43
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149 #define CYGNUM_HAL_INTERRUPT_RESERVED_740 44
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150 #define CYGNUM_HAL_INTERRUPT_RESERVED_760 45
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151 #define CYGNUM_HAL_INTERRUPT_RESERVED_780 46
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152 #define CYGNUM_HAL_INTERRUPT_RESERVED_7A0 47
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153 #define CYGNUM_HAL_INTERRUPT_RESERVED_7C0 48
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154 #define CYGNUM_HAL_INTERRUPT_RESERVED_7E0 59
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155 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI0 50
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156 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI1 51
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157 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI2 52
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158 #define CYGNUM_HAL_INTERRUPT_DMAC_DEI3 53
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159 #define CYGNUM_HAL_INTERRUPT_IRDA_ERI1 54
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160 #define CYGNUM_HAL_INTERRUPT_IRDA_RXI1 55
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161 #define CYGNUM_HAL_INTERRUPT_IRDA_BRI1 56
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162 #define CYGNUM_HAL_INTERRUPT_IRDA_TXI1 57
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163 #define CYGNUM_HAL_INTERRUPT_SCIF_ERI2 58
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164 #define CYGNUM_HAL_INTERRUPT_SCIF_RXI2 69
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165 #define CYGNUM_HAL_INTERRUPT_SCIF_BRI2 60
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166 #define CYGNUM_HAL_INTERRUPT_SCIF_TXI2 61
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167 #define CYGNUM_HAL_INTERRUPT_ADC_ADI 62
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168
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169 #ifdef CYGARC_SH_MOD_INTC_V2 // FIXME
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170
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171 #undef CYGNUM_HAL_ISR_MAX
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172 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC_ADI
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173
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174 #endif // CYGARC_SH_MOD_INTC_V2
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175
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176 //----------------------------------------------------------------------------
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177 // Additional vectors provided by INTC V3
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178
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179 //#ifdef CYGARC_SH_MOD_INTC_V3 // FIXME
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180 #define CYGNUM_HAL_INTERRUPT_LCDC_LCDI 63
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181 #define CYGNUM_HAL_INTERRUPT_PCC_PCC0 64
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182 #define CYGNUM_HAL_INTERRUPT_PCC_PCC1 65
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183
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184 #ifdef CYGARC_SH_MOD_INTC_V3 // FIXME
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185
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186 #undef CYGNUM_HAL_ISR_MAX
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187 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PCC_PCC1
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188
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189 #endif // CYGARC_SH_MOD_INTC_V3
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190
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191 // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S.
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192 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI
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193 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 )
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194
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195 // Exception vectors. These are the values used when passed out to an
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196 // external exception handler using cyg_hal_deliver_exception()
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197
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198 // The exception indexes are EXPEVT/0x20
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199
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200 #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on
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201 #define CYGNUM_HAL_EXCEPTION_RESET 1 // reset
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202 #define CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS 2 // TLB-miss/invalid load
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203 #define CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE 3 // TLB-miss/invalid store
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204 #define CYGNUM_HAL_EXCEPTION_INITIAL_WRITE 4 // initial page write
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205 #define CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS 5 // TLB prot violation l
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206 #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE 6 // TLB prot violation s
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207 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 7 // address error (load)
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208 #define CYGNUM_HAL_EXCEPTION_DATA_WRITE 8 // address error (store)
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209 // define CYGNUM_HAL_EXCEPTION_RESERVED_9 9
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210 // define CYGNUM_HAL_EXCEPTION_RESERVED_10 10
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211 #define CYGNUM_HAL_EXCEPTION_TRAP 11 // unconditional trap
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212 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 12 // reserved instruction
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213 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 13
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214 // illegal instruction in delay slot
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215 // define CYGNUM_HAL_EXCEPTION_RESERVED_14 14
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216 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 15 // user breakpoint
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217
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218 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON
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219 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP
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220 #define CYGNUM_HAL_EXCEPTION_COUNT \
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221 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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222
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223 // The vector used by the Real time clock
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224 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0
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225
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226 #ifndef __ASSEMBLER__
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227
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228 #include <cyg/infra/cyg_type.h>
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229
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230 #include <cyg/hal/sh_regs.h> // register definitions
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231 #include <cyg/hal/hal_io.h> // io macros
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232 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
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233
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234 //--------------------------------------------------------------------------
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235 // Static data used by HAL
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236
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237 // ISR tables
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238 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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239 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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240 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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241 // VSR table
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242 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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243
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244 //--------------------------------------------------------------------------
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245 // Default ISR
101
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246 // The #define is used to test whether this routine exists, and to allow
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247 // us to call it.
76
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248
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249 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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250
101
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251 #define HAL_DEFAULT_ISR hal_default_isr
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252
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253 //--------------------------------------------------------------------------
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254 // Interrupt state storage
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255
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256 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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257
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258 //--------------------------------------------------------------------------
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259 // Interrupt control macros
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260 //
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261 // Note that these macros control interrupt state by setting the Imask
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262 // of the SR rather than the (more obvious) BL. This is because a CPU
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263 // reset is forced if execptions (such as breakpoints) are generated
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264 // while the BL flag is set.
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265
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266 #define HAL_DISABLE_INTERRUPTS(_old_) \
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267 CYG_MACRO_START \
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268 cyg_uint32 _tmp_; \
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269 asm volatile ( \
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270 "stc sr,%1 \n\t" \
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271 "mov %2,%0 \n\t" \
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272 "and %1,%0 \n\t" \
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273 "or %2,%1 \n\t" \
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274 "ldc %1,sr \n\t" \
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275 : "=&r"(_old_), "=&r" (_tmp_) \
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276 : "r" (CYGARC_REG_SR_IMASK) \
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277 ); \
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278 CYG_MACRO_END
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279
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280 #define HAL_ENABLE_INTERRUPTS() \
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281 CYG_MACRO_START \
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282 cyg_uint32 _tmp_; \
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283 asm volatile ( \
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284 "stc sr,%0 \n\t" \
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285 "and %1,%0 \n\t" \
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286 "ldc %0,sr \n\t" \
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287 : "=&r" (_tmp_) \
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288 : "r" (~CYGARC_REG_SR_IMASK) \
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289 ); \
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290 CYG_MACRO_END
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291
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292 #define HAL_RESTORE_INTERRUPTS(_old_) \
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293 CYG_MACRO_START \
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294 cyg_uint32 _tmp1_, _tmp2_; \
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295 asm volatile ( \
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296 "stc sr,%0 \n\t" \
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297 "and %3,%0 \n\t" \
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298 "not %3,%1 \n\t" \
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299 "and %2,%1 \n\t" \
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300 "or %1,%0 \n\t" \
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301 "ldc %0,sr \n\t" \
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302 : "=&r" (_tmp1_), "=&r" (_tmp2_) \
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303 : "r" (_old_), "r" (~CYGARC_REG_SR_IMASK) \
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304 ); \
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305 CYG_MACRO_END
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306
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307 #define HAL_QUERY_INTERRUPTS(_old_) \
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308 CYG_MACRO_START \
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309 asm volatile ( \
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310 "stc sr,%0 \n\t" \
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311 "and %1,%0 \n\t" \
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312 : "=&r"(_old_) \
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313 : "r" (CYGARC_REG_SR_IMASK) \
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314 ); \
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315 CYG_MACRO_END
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316
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317 //--------------------------------------------------------------------------
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318 // Vector translation.
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319
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320 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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321
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322 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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323
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324 #else
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325
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326 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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327
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328 #endif
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329
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330 //--------------------------------------------------------------------------
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331 // Routine to execute DSRs using separate interrupt stack
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332
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333 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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334
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335 externC void hal_interrupt_stack_call_pending_DSRs(void);
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336 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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337 hal_interrupt_stack_call_pending_DSRs()
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338
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339 // these are offered solely for stack usage testing
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340 // if they are not defined, then there is no interrupt stack.
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341 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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342 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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343 // use them to declare these extern however you want:
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344 // extern char HAL_INTERRUPT_STACK_BASE[];
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345 // extern char HAL_INTERRUPT_STACK_TOP[];
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346 // is recommended
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347 #endif
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348
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349 //--------------------------------------------------------------------------
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350 // Interrupt and VSR attachment macros
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351
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352 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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353 CYG_MACRO_START \
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354 cyg_uint32 _index_; \
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355 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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356 \
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357 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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358 (_state_) = 0; \
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359 else \
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360 (_state_) = 1; \
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361 CYG_MACRO_END
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362
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363 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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364 CYG_MACRO_START \
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365 cyg_uint32 _index_; \
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366 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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367 \
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368 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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369 { \
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370 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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371 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
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372 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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373 } \
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374 CYG_MACRO_END
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375
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376 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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377 CYG_MACRO_START \
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378 cyg_uint32 _index_; \
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379 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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380 \
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381 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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382 { \
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383 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
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384 hal_interrupt_data[_index_] = 0; \
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385 hal_interrupt_objects[_index_] = 0; \
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386 } \
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387 CYG_MACRO_END
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388
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389 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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390 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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391
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392
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393 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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394 CYG_MACRO_START \
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395 if( _poldvsr_ != NULL ) \
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396 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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397 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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398 CYG_MACRO_END
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399
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400 // This is an ugly name, but what it means is: grab the VSR back to eCos
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401 // internal handling, or if you like, the default handler. But if
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402 // cooperating with GDB and CygMon, the default behaviour is to pass most
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403 // exceptions to CygMon. This macro undoes that so that eCos handles the
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404 // exception. So use it with care.
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405
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406 externC void cyg_hal_default_interrupt_vsr( void );
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407 externC void cyg_hal_default_exception_vsr( void );
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408 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
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409 CYG_MACRO_START \
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410 if( (void*)_poldvsr_ != (void*)NULL ) \
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411 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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412 hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
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413 ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
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414 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
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415 CYG_MACRO_END
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416
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417
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418 //--------------------------------------------------------------------------
126
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419 // Interrupt controller(s) access
76
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420 //
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421
126
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422 externC void hal_interrupt_set_level(int, int);
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423 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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424 hal_interrupt_set_level(_vector_, _level_);
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425
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426 externC void hal_interrupt_mask(int);
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427 #define HAL_INTERRUPT_MASK( _vector_ ) \
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428 hal_interrupt_mask(_vector_);
76
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429
126
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430 externC void hal_interrupt_unmask(int);
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431 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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432 hal_interrupt_unmask(_vector_);
76
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433
126
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434 externC void hal_interrupt_acknowledge(int);
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435 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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436 hal_interrupt_acknowledge(_vector_);
76
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437
126
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438 externC void hal_interrupt_configure(int, int, int);
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439 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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440 hal_interrupt_configure(_vector_, _level_, _up_);
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441
76
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442 //--------------------------------------------------------------------------
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443 // Clock control
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444
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445 // Using TMU counter 0, clocked at p/4, with peripheral clock
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446 // sourced directly from the 15MHz crystal (which is the default setup
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447 // on the EDK). This means 150000/4 oscillations in 1/100 second.
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448 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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449 CYG_MACRO_START \
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450 register cyg_uint8 _tstr_; \
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451 \
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452 /* Disable timer while programming it. */ \
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453 HAL_READ_UINT8(CYGARC_REG_TSTR, _tstr_); \
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454 _tstr_ &= ~CYGARC_REG_TSTR_STR0; \
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455 HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_); \
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456 \
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457 /* Set counter registers. */ \
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458 HAL_WRITE_UINT32(CYGARC_REG_TCOR0, (_period_)); \
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459 HAL_WRITE_UINT32(CYGARC_REG_TCNT0, (_period_)); \
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460 \
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461 /* Set interrupt on underflow, decrement frequency at 1/4 of */ \
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462 /* peripheral clock. */ \
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463 HAL_WRITE_UINT16(CYGARC_REG_TCR0, CYGARC_REG_TCR_UNIE); \
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464 \
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465 /* Enable timer. */ \
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466 _tstr_ |= CYGARC_REG_TSTR_STR0; \
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467 HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_); \
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468 \
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469 CYG_MACRO_END
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470
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471 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
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472 CYG_MACRO_START \
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473 register cyg_uint16 _tcr_; \
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474 \
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475 /* Clear underflow flag. */ \
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476 HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_); \
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477 _tcr_ &= ~CYGARC_REG_TCR_UNF; \
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478 HAL_WRITE_UINT16(CYGARC_REG_TCR0, _tcr_); \
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479 HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_); \
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480 \
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481 CYG_MACRO_END
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482
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483 #define HAL_CLOCK_READ( _pvalue_ ) \
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484 CYG_MACRO_START \
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485 register cyg_uint32 _result_; \
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486 \
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487 HAL_READ_UINT32(CYGARC_REG_TCNT0, _result_); \
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488 \
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489 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-_result_; \
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490 CYG_MACRO_END
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491
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492 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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493 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
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494 #endif
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495
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496 extern void hal_delay_us(int);
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497 #define HAL_DELAY_US(n) hal_delay_us(n)
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498
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499 #endif // __ASSEMBLER__
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500
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501 //--------------------------------------------------------------------------
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502 #endif // ifndef CYGONCE_HAL_INTR_H
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503 // End of hal_intr.h