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comparison packages/hal/powerpc/ppc40x/current/include/var_cache.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children a9ac27ec7abc
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133:98d71f4d8243 134:d2f49caf9e38
1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
3 //=============================================================================
4 //
5 // var_cache.h
6 //
7 // Variant HAL cache control API
8 //
9 //=============================================================================
10 //####COPYRIGHTBEGIN####
11 //
12 // -------------------------------------------
13 // The contents of this file are subject to the Red Hat eCos Public License
14 // Version 1.1 (the "License"); you may not use this file except in
15 // compliance with the License. You may obtain a copy of the License at
16 // http://www.redhat.com/
17 //
18 // Software distributed under the License is distributed on an "AS IS"
19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 // License for the specific language governing rights and limitations under
21 // the License.
22 //
23 // The Original Code is eCos - Embedded Configurable Operating System,
24 // released September 30, 1998.
25 //
26 // The Initial Developer of the Original Code is Red Hat.
27 // Portions created by Red Hat are
28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 // All Rights Reserved.
30 // -------------------------------------------
31 //
32 //####COPYRIGHTEND####
33 //=============================================================================
34 //#####DESCRIPTIONBEGIN####
35 //
36 // Author(s): nickg
37 // Contributors:nickg, jskov
38 // Date: 2000-04-02
39 // Purpose: Variant cache control API
40 // Description: The macros defined here provide the HAL APIs for handling
41 // cache control operations on the PPC60x variant CPUs.
42 // Usage: Is included via the architecture cache header:
43 // #include <cyg/hal/hal_cache.h>
44 // ...
45 //
46 //####DESCRIPTIONEND####
47 //
48 //=============================================================================
49
50 #include <pkgconf/hal.h>
51 #include <cyg/infra/cyg_type.h>
52
53 #include <cyg/hal/ppc_regs.h>
54
55 #include <cyg/hal/plf_cache.h>
56
57
58 //-----------------------------------------------------------------------------
59 // Cache dimensions
60
61 // Data cache
62 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
63 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
64 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
65
66 // Instruction cache
67 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
68 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
69 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
70
71 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
72 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
73
74 //-----------------------------------------------------------------------------
75 // Global control of data cache
76
77 // Enable the data cache - this is implicit whenever the MMU is turned on
78 #define HAL_DCACHE_ENABLE()
79
80 // Disable the data cache
81 #define HAL_DCACHE_DISABLE()
82
83 // Invalidate the entire cache
84 #define HAL_DCACHE_INVALIDATE_ALL() \
85 CYG_MACRO_START \
86 int _i_, _indx_; \
87 _indx_ = 0; \
88 for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
89 asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
90 _indx_ += HAL_DCACHE_LINE_SIZE; \
91 } \
92 CYG_MACRO_END
93
94 // Synchronize the contents of the cache with memory.
95 #define HAL_DCACHE_SYNC()
96
97 // Query the state of the data cache
98 #define HAL_DCACHE_IS_ENABLED(_state_) \
99 CYG_MACRO_START \
100 (_state_) = 0; \
101 CYG_MACRO_END
102
103 // Set the data cache refill burst size
104 //#define HAL_DCACHE_BURST_SIZE(_size_)
105
106 // Set the data cache write mode
107 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
108
109 //#define HAL_DCACHE_WRITETHRU_MODE 0
110 //#define HAL_DCACHE_WRITEBACK_MODE 1
111
112 // Load the contents of the given address range into the data cache
113 // and then lock the cache so that it stays there.
114 //#define HAL_DCACHE_LOCK(_base_, _size_)
115
116 // Undo a previous lock operation
117 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
118
119 // Unlock entire cache
120 #define HAL_DCACHE_UNLOCK_ALL()
121
122 //-----------------------------------------------------------------------------
123 // Data cache line control
124
125 // Allocate cache lines for the given address range without reading its
126 // contents from memory.
127 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
128
129 // Write dirty cache lines to memory and invalidate the cache entries
130 // for the given address range.
131 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
132
133 // Invalidate cache lines in the given range without writing to memory.
134 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
135
136 // Write dirty cache lines to memory for the given address range.
137 //#define HAL_DCACHE_STORE( _base_ , _size_ )
138
139 // Preread the given range into the cache with the intention of reading
140 // from it later.
141 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
142
143 // Preread the given range into the cache with the intention of writing
144 // to it later.
145 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
146
147 // Allocate and zero the cache lines associated with the given range.
148 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
149
150 //-----------------------------------------------------------------------------
151 // Global control of Instruction cache
152
153 // Enable the instruction cache
154 #define HAL_ICACHE_ENABLE()
155
156 // Disable the instruction cache
157 #define HAL_ICACHE_DISABLE()
158
159 // Invalidate the entire cache
160 #define HAL_ICACHE_INVALIDATE_ALL()
161
162 // Synchronize the contents of the cache with memory.
163 #define HAL_ICACHE_SYNC()
164
165 // Query the state of the instruction cache
166 #define HAL_ICACHE_IS_ENABLED(_state_) \
167 CYG_MACRO_START \
168 (_state_) = 0; \
169 CYG_MACRO_END
170
171 // Set the instruction cache refill burst size
172 //#define HAL_ICACHE_BURST_SIZE(_size_)
173
174 // Load the contents of the given address range into the instruction cache
175 // and then lock the cache so that it stays there.
176 //#define HAL_ICACHE_LOCK(_base_, _size_)
177
178 // Undo a previous lock operation
179 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
180
181 // Unlock entire cache
182 #define HAL_ICACHE_UNLOCK_ALL()
183
184 //-----------------------------------------------------------------------------
185 // Instruction cache line control
186
187 // Invalidate cache lines in the given range without writing to memory.
188 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
189
190 //-----------------------------------------------------------------------------
191 #endif // ifndef CYGONCE_VAR_CACHE_H
192 // End of var_cache.h