Mercurial > ecos

comparison packages/hal/sh/edk7708/current/src/edk.S @ 134:d2f49caf9e38 ecos-sw-2000-11-03

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents
children e0c0827131d1
comparison
equal deleted inserted replaced
133:98d71f4d8243 134:d2f49caf9e38
1 ##=============================================================================
2 ##
3 ## edk.S
4 ##
5 ## EDK board hardware setup
6 ##
7 ##=============================================================================
8 #####COPYRIGHTBEGIN####
9 #
10 # -------------------------------------------
11 # The contents of this file are subject to the Red Hat eCos Public License
12 # Version 1.1 (the "License"); you may not use this file except in
13 # compliance with the License. You may obtain a copy of the License at
14 # http://www.redhat.com/
15 #
16 # Software distributed under the License is distributed on an "AS IS"
17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 # License for the specific language governing rights and limitations under
19 # the License.
20 #
21 # The Original Code is eCos - Embedded Configurable Operating System,
22 # released September 30, 1998.
23 #
24 # The Initial Developer of the Original Code is Red Hat.
25 # Portions created by Red Hat are
26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 # All Rights Reserved.
28 # -------------------------------------------
29 #
30 #####COPYRIGHTEND####
31 ##=============================================================================
32 #######DESCRIPTIONBEGIN####
33 ##
34 ## Author(s): jskov
35 ## Contributors:jskov
36 ## Date: 1999-05-03
37 ## Purpose: EDK7708 board hardware setup
38 ## Description: This file contains any code needed to initialize the
39 ## hardware on a Hitachi SH3 EDK7708 board.
40 ##
41 ######DESCRIPTIONEND####
42 ##
43 ##=============================================================================
44
45 #include <pkgconf/hal.h>
46 #include <cyg/hal/sh_regs.h>
47
48 .globl _hal_hardware_init
49 _hal_hardware_init:
50
51 // Set up the Bus State Controller
52 mov.l $BSC_settings_table,r3
53 1: mov.w @r3+,r0 // Address (or zero)
54 cmp/eq #0,r0
55 bt 2f
56 mov.w @r3+,r1 // data
57 bra 1b
58 mov.w r1,@r0 // delay slot
59
60 2:
61 rts
62 nop
63
64 .align 2
65 $BSC_settings_table:
66 .long BSC_settings_table
67 BSC_settings_table:
68 # These are the settings set by the Hitachi ROM Monitor.
69
70 # BCR2: Bus size of areas 1-6 to 32 bits
71 .word CYGARC_REG_BCR2
72 .word 0x3ffc
73 # BCR1: Areas 2 and 3 are SDRAM
74 .word CYGARC_REG_BCR1
75 .word 0x080c
76 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
77 .word CYGARC_REG_BCR2
78 .word 0x3ffc
79 # WCR1: 3 wait-state cycles inserted for all areas
80 .word CYGARC_REG_WCR1
81 .word 0x3fff
82 # WCR2: extra wait states and full pitch for burst
83 .word CYGARC_REG_WCR2
84 .word 0xffd7
85 # MCR: RAS/CAS & burst timing area 2/3
86 .word CYGARC_REG_MCR
87 .word 0x963c
88 #if 0
89 # DCR: RAS/CAS & burst timing area 2
90 .word CYGARC_REG_DCR
91 .word 0x0000
92 # PCR: PCMCIA disabled
93 .word CYGARC_REG_PCR
94 .word 0x0000
95 #endif
96 # RTCNT: refresh counter (needs a5 in top byte to accept write)
97 .word CYGARC_REG_RTCNT
98 .word (0xa500 | 0x0000)
99 # RTCOR: refresh time constant (needs a5 in top byte to accept write)
100 .word CYGARC_REG_RTCOR
101 .word (0xa500 | 0x003b)
102 # RFCR: refresh count register (needs a4 in top byte to accept write)
103 .word CYGARC_REG_RFCR
104 .word (0xa400 | 0x0000)
105 # RTCSR: refresh timer control (needs a5 in top byte to accept write)
106 .word CYGARC_REG_RTCSR
107 .word (0xa500 | 0x0008)
108
109 # Set SDMR to 0x220
110 .word 0xd880
111 .word 0
112
113 # Table end
114 .word 0
115
116 #------------------------------------------------------------------------------
117 # end of edk.S