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comparison packages/hal/sh/sh4/current/include/mod_regs_ser.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 289bf90c6a9b
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133:98d71f4d8243 134:d2f49caf9e38
1 //=============================================================================
2 //
3 // mod_regs_ser.h
4 //
5 // SCI, SCIF, and IRDA (serial) Module register definitions
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //=============================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 2000-10-30
37 // Note: All three serial module definitions kept in the same file
38 // since they share some of the information.
39 //####DESCRIPTIONEND####
40 //
41 //=============================================================================
42
43 //++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44
45 //--------------------------------------------------------------------------
46 // Serial registers. All 8 bit registers.
47 #define CYGARC_REG_SCSMR1 0xFFE00000 // serial mode register
48 #define CYGARC_REG_SCBRR1 0xFFE00004 // bit rate register
49 #define CYGARC_REG_SCSCR1 0xFFE00008 // serial control register
50 #define CYGARC_REG_SCTDR1 0xFFE0000C // transmit data register
51 #define CYGARC_REG_SCSSR1 0xFFE00010 // serial status register
52 #define CYGARC_REG_SCRDR1 0xFFE00014 // receive data register
53 #define CYGARC_REG_SCRCMR1 0xFFE00018
54 #define CYGARC_REG_SCSPTR1 0xFFE0001C // serial port register
55
56 // Serial Mode Register
57 #define CYGARC_REG_SCSMR1_CA 0x80 // communication mode
58 #define CYGARC_REG_SCSMR1_CHR 0x40 // character length (7 if set)
59 #define CYGARC_REG_SCSMR1_PE 0x20 // parity enable
60 #define CYGARC_REG_SCSMR1_OE 0x10 // parity mode
61 #define CYGARC_REG_SCSMR1_STOP 0x08 // stop bit length
62 #define CYGARC_REG_SCSMR1_MP 0x04 // multiprocessor mode
63 #define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1
64 #define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0
65 #define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask
66
67 // Serial Control Register
68 #define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable
69 #define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable
70 #define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable
71 #define CYGARC_REG_SCSCR1_RE 0x10 // receive enable
72 #define CYGARC_REG_SCSCR1_MPIE 0x08 // multiprocessor interrupt enable
73 #define CYGARC_REG_SCSCR1_TEIE 0x04 // transmit-end interrupt enable
74 #define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1
75 #define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0
76
77 // Serial Status Register
78 #define CYGARC_REG_SCSSR1_TDRE 0x80 // transmit data register empty
79 #define CYGARC_REG_SCSSR1_RDRF 0x40 // receive data register full
80 #define CYGARC_REG_SCSSR1_ORER 0x20 // overrun error
81 #define CYGARC_REG_SCSSR1_FER 0x10 // framing error
82 #define CYGARC_REG_SCSSR1_PER 0x08 // parity error
83 #define CYGARC_REG_SCSSR1_TEND 0x04 // transmit end
84 #define CYGARC_REG_SCSSR1_MPB 0x02 // multiprocessor bit
85 #define CYGARC_REG_SCSSR1_MPBT 0x01 // multiprocessor bit transfer
86
87 // When clearing the status register, always write the value:
88 // CYGARC_REG_SCSSR_CLEARMASK & ~bit
89 // to prevent other bits than the one of interest to be cleared.
90 #define CYGARC_REG_SCSSR1_CLEARMASK 0xf8
91
92
93 // Baud rate values calculation, depending on peripheral clock (Pf)
94 // n is CKS setting (0-3)
95 // N = (Pf/(64*2^(2n-1)*B))-1
96 // With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get
97 // N = (Pf/(32*_CKS*B))-1
98 //
99 // The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS
100 // setting for the given baud rate and peripheral clock.
101 //
102 // The error of the CKS+count value can be computed by:
103 // E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100
104 //
105 #define CYGARC_SCBRR_PRESCALE(_b_) \
106 ((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \
107 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \
108 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64)
109
110 // These two macros provide the static values we need to stuff into the
111 // registers.
112 #define CYGARC_SCBRR_CKSx(_b_) \
113 ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \
114 (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \
115 (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3)
116 #define CYGARC_SCBRR_N(_b_) \
117 (((_b_) < 4800) ? 0 : \
118 ((_b_) > 115200) ? 0 : \
119 ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1))
120
121
122 //++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++
123 #ifdef CYGARC_SH_MOD_IRDA
124
125 //--------------------------------------------------------------------------
126 // IrDA (infrared data association). Can also act as regular serial w FIFO
127
128 #define CYGARC_REG_SCSMR1 0xFFE00000 // serial mode register
129 #define CYGARC_REG_SCBRR1 0xFFE00004 // bit rate register
130 #define CYGARC_REG_SCSCR1 0xFFE00008 // serial control register
131 #define CYGARC_REG_SCTDR1 0xFFE0000C // transmit data register
132 #define CYGARC_REG_SCSSR1 0xFFE00010 // serial status register
133 #define CYGARC_REG_SCRDR1 0xFFE00014 // receive data register
134 #define CYGARC_REG_SCRCMR1 0xFFE00018
135 #define CYGARC_REG_SCSPTR1 0xFFE0001C // serial port register
136
137 // Serial Mode Register
138 #define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode
139 #define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width
140 #define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?)
141 #define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1
142 #define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0
143 #define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask
144
145 // Serial Control Register
146 #define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable
147 #define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable
148 #define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable
149 #define CYGARC_REG_SCSCR1_RE 0x10 // receive enable
150 #define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1
151 #define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0
152
153 // Serial Status Register
154 #define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors
155 #define CYGARC_REG_SCSSR1_PER_shift 12
156 #define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors
157 #define CYGARC_REG_SCSSR1_FER_shift 8
158 #define CYGARC_REG_SCSSR1_ER 0x0080 // receive error
159 #define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end
160 #define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty
161 #define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection
162 #define CYGARC_REG_SCSSR1_FER 0x0008 // framing error
163 #define CYGARC_REG_SCSSR1_PER 0x0004 // parity error
164 #define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full
165 #define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready
166
167 // When clearing the status register, always write the value:
168 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
169 // to prevent other bits than the one of interest to be cleared.
170 #define CYGARC_REG_SCSSR1_CLEARMASK 0xf3
171
172 // Serial FIFO Control Register
173 #define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger
174 #define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char
175 #define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars
176 #define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars
177 #define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars
178
179 #define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger
180 #define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars
181 #define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars
182 #define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars
183 #define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char
184
185 #define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable
186 #define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset
187 #define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset
188 #define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test
189
190
191 // Serial FIFO Data Count Set Register
192 #define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo
193 #define CYGARC_REG_SCFDR1_RCOUNT_shift 0
194 #define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo
195 #define CYGARC_REG_SCFDR1_TCOUNT_shift 8
196
197 #endif // CYGARC_SH_MOD_IRDA
198
199 //++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++
200 #ifdef CYGARC_SH_MOD_SCIF
201
202 //--------------------------------------------------------------------------
203 // Serial w FIFO registers
204
205 #define CYGARC_REG_SCSMR2 0xffe80000 // Serial mode
206 #define CYGARC_REG_SCBRR2 0xffe80004 // Bit rate
207 #define CYGARC_REG_SCSCR2 0xffe80008 // Serial control
208 #define CYGARC_REG_SCFTDR2 0xffe8000c // Transmit FIFO data
209 #define CYGARC_REG_SCFSR2 0xffe80010 // Serial status
210 #define CYGARC_REG_SCFRDR2 0xffe80014 // Receive data FIFO
211 #define CYGARC_REG_SCFCR2 0xffe80018 // FIFO control register
212 #define CYGARC_REG_SCFDR2 0xffe8001c // FIFO data count set
213 #define CYGARC_REG_SCSPTR2 0xffe80020 // serial port register
214 #define CYGARC_REG_SCLSR2 0xffe80024 // line status register
215
216 // Serial Mode Register
217 #define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set)
218 #define CYGARC_REG_SCSMR2_PE 0x20 // parity enable
219 #define CYGARC_REG_SCSMR2_OE 0x10 // parity mode
220 #define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length
221 #define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1
222 #define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0
223 #define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask
224
225 // Serial Control Register
226 #define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable
227 #define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable
228 #define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable
229 #define CYGARC_REG_SCSCR2_RE 0x10 // receive enable
230 #define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1
231 #define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0
232
233 // Serial Status Register
234 #define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors
235 #define CYGARC_REG_SCSSR2_PER_shift 12
236 #define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors
237 #define CYGARC_REG_SCSSR2_FER_shift 8
238 #define CYGARC_REG_SCSSR2_ER 0x0080 // receive error
239 #define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end
240 #define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty
241 #define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection
242 #define CYGARC_REG_SCSSR2_FER 0x0008 // framing error
243 #define CYGARC_REG_SCSSR2_PER 0x0004 // parity error
244 #define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full
245 #define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready
246
247 // When clearing the status register, always write the value:
248 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
249 // to prevent other bits than the one of interest to be cleared.
250 #define CYGARC_REG_SCSSR2_CLEARMASK 0xf3
251
252 // Serial FIFO Control Register
253 #define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger
254 #define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char
255 #define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars
256 #define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars
257 #define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars
258
259 #define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger
260 #define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars
261 #define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars
262 #define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars
263 #define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char
264
265 #define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable
266 #define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset
267 #define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset
268 #define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test
269
270
271 // Serial FIFO Data Count Set Register
272 #define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo
273 #define CYGARC_REG_SCFDR2_RCOUNT_shift 0
274 #define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo
275 #define CYGARC_REG_SCFDR2_TCOUNT_shift 8
276
277 #endif // CYGARC_SH_MOD_SCIF