diff packages/hal/mips/tx39/current/include/var_cache.h @ 130:eb9fd8c04db3 ecos-sw-2000-10-23

Merge from eCos master repository on 2000-10-23-17:01:37-BST
author jlarmour
date Mon, 23 Oct 2000 17:10:57 +0000
parents bf00f99aec69
children e0c0827131d1
line wrap: on
line diff
--- a/packages/hal/mips/tx39/current/include/var_cache.h
+++ b/packages/hal/mips/tx39/current/include/var_cache.h
@@ -117,15 +117,15 @@
 // otherwise. Hence we read bytes from the ROM space since this is
 // most likely to be code, and will not get out of sync even if it is not.
 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
-#define HAL_DCACHE_INVALIDATE_ALL()                                             \
-{                                                                               \
-    CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000);                         \
-    CYG_BYTE volatile tmp = 0;                                                  \
-    int i;                                                                      \
-    for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE )            \
-    {                                                                           \
-        tmp = addr[i];                                                          \
-    }                                                                           \
+#define HAL_DCACHE_INVALIDATE_ALL()                                     \
+{                                                                       \
+    volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000);                 \
+    volatile CYG_BYTE tmp = 0;                                          \
+    int i;                                                              \
+    for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE )    \
+    {                                                                   \
+        tmp = addr[i];                                                  \
+    }                                                                   \
 }
 
 // Synchronize the contents of the cache with memory.