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annotate packages/hal/mips/tx39/current/include/var_cache.h @ 130:eb9fd8c04db3 ecos-sw-2000-10-23

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Merge from eCos master repository on 2000-10-23-17:01:37-BST
author jlarmour
date Mon, 23 Oct 2000 17:10:57 +0000
parents bf00f99aec69
children e0c0827131d1
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1 #ifndef CYGONCE_IMP_CACHE_H
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2 #define CYGONCE_IMP_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // imp_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors: nickg
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39 // Date: 1998-02-17
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/imp_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <pkgconf/hal.h>
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53 #include <cyg/infra/cyg_type.h>
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54
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55 #include <cyg/hal/plf_cache.h>
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56
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57 //=============================================================================
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58 // Toshiba TX3904
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59
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60 #ifdef CYGPKG_HAL_MIPS_TX3904
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61
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62 //-----------------------------------------------------------------------------
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63 // Cache dimensions
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64
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65 // Data cache
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66 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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67 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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68 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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69
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70 // Instruction cache
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71 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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72 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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73 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
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74
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75 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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76 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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77
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78 //-----------------------------------------------------------------------------
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79 // Global control of data cache
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80
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81 // Enable the data cache
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82 // This uses a bit in the config register, which is TX39 specific.
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83 #define HAL_DCACHE_ENABLE_DEFINED
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84 #define HAL_DCACHE_ENABLE() \
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85 { \
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86 asm volatile ("mfc0 $2,$3;" \
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87 "ori $2,$2,0x0010;" \
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88 "mtc0 $2,$3;" \
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89 : \
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90 : \
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91 : "$2" \
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92 ); \
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93 \
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94 }
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95
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96 // Disable the data cache
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97 #define HAL_DCACHE_DISABLE_DEFINED
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98 #define HAL_DCACHE_DISABLE() \
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99 { \
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100 asm volatile ("mfc0 $2,$3;" \
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101 "la $3,0xFFFFFFEF;" \
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102 "and $2,$2,$3;" \
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103 "mtc0 $2,$3;" \
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104 : \
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105 : \
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106 : "$2", "$3" \
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107 ); \
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108 \
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109 }
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110
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111
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112 // Invalidate the entire cache
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113 // The TX39 only has hit-invalidate on the DCACHE, not
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114 // index-invalidate, so we cannot just empty the cache out without
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115 // knowing what is in it. This is annoying. So, the best we can do is
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116 // fill the cache with data that is unlikely to be there
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117 // otherwise. Hence we read bytes from the ROM space since this is
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118 // most likely to be code, and will not get out of sync even if it is not.
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119 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
130
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120 #define HAL_DCACHE_INVALIDATE_ALL() \
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121 { \
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122 volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000); \
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123 volatile CYG_BYTE tmp = 0; \
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124 int i; \
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125 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
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126 { \
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127 tmp = addr[i]; \
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128 } \
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129 }
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130
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131 // Synchronize the contents of the cache with memory.
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132 #define HAL_DCACHE_SYNC_DEFINED
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133 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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134
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135 // Set the data cache refill burst size
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136 //#define HAL_DCACHE_BURST_SIZE(_size_)
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137
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138 // Set the data cache write mode
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139 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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140
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141 //#define HAL_DCACHE_WRITETHRU_MODE 0
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142 //#define HAL_DCACHE_WRITEBACK_MODE 1
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143
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144 // Load the contents of the given address range into the data cache
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145 // and then lock the cache so that it stays there.
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146 #define HAL_DCACHE_LOCK_DEFINED
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147 #define HAL_DCACHE_LOCK(_base_, _size_) \
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148 { \
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149 asm volatile ("mfc0 $2,$7;" \
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150 "ori $2,$2,0x0100;" \
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151 "mtc0 $2,$7;" \
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152 : \
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153 : \
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154 : "$2" \
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155 ); \
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156 }
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157
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158 // Undo a previous lock operation
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159 #define HAL_DCACHE_UNLOCK_DEFINED
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160 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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161 { \
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162 asm volatile ("mfc0 $2,$7;" \
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163 "la $3,0xFFFFFEFF;" \
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164 "and $2,$2,$3;" \
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165 "mtc0 $2,$7;" \
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166 : \
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167 : \
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168 : "$2", "$3" \
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169 ); \
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170 }
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171
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172 // Unlock entire cache
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173 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
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174 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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175
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176
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177 //-----------------------------------------------------------------------------
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178 // Data cache line control
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179
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180 // Allocate cache lines for the given address range without reading its
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181 // contents from memory.
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182 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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183
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184 // Write dirty cache lines to memory and invalidate the cache entries
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185 // for the given address range.
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186 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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187 #define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
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188
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189 // Write dirty cache lines to memory for the given address range.
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190 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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191 #define HAL_DCACHE_STORE_DEFINED // Disable default definition
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192
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193 //-----------------------------------------------------------------------------
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194 // Global control of Instruction cache
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195
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196 // Enable the instruction cache
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197 // This uses a bit in the config register, which is TX39 specific.
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198 #define HAL_ICACHE_ENABLE_DEFINED
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199 #define HAL_ICACHE_ENABLE() \
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200 { \
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201 asm volatile ("mfc0 $2,$3;" \
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202 "ori $2,$2,0x0020;" \
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203 "mtc0 $2,$3;" \
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204 : \
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205 : \
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206 : "$2" \
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207 ); \
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208 \
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209 }
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210
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211 // Disable the instruction cache
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212 #define HAL_ICACHE_DISABLE_DEFINED
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213 #define HAL_ICACHE_DISABLE() \
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214 { \
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215 asm volatile ("mfc0 $2,$3;" \
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216 "la $3,0xFFFFFFDF;" \
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217 "and $2,$2,$3;" \
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218 "mtc0 $2,$3;" \
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219 "j 1f;" \
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220 "nop;" \
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221 ".balign 16,0;" \
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222 "1:;" \
6
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223 : \
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224 : \
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225 : "$2", "$3" \
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226 ); \
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227 \
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228 }
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229
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230 // Load the contents of the given address range into the instruction cache
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231 // and then lock the cache so that it stays there.
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232 #define HAL_ICACHE_LOCK_DEFINED
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233 #define HAL_ICACHE_LOCK(_base_, _size_) \
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234 { \
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235 asm volatile ("mfc0 $2,$7;" \
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236 "ori $2,$2,0x0200;" \
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237 "mtc0 $2,$7;" \
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238 : \
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239 : \
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240 : "$2" \
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241 ); \
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242 }
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243
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244 // Undo a previous lock operation
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245 #define HAL_ICACHE_UNLOCK_DEFINED
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246 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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247 { \
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248 asm volatile ("mfc0 $2,$7;" \
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249 "la $3,0xFFFFFDFF;" \
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250 "and $2,$2,$3;" \
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251 "mtc0 $2,$7;" \
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252 : \
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253 : \
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254 : "$2", "$3" \
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255 ); \
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256 }
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257
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258 // Unlock entire cache
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259 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
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260 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
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261
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262 //-----------------------------------------------------------------------------
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263 // Instruction cache line control
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264 // On the TX39, the instruction cache must be disabled to use the index-invalidate
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265 // cache operation.
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266
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267 // Invalidate the entire cache
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268 // This uses the index-invalidate cache operation.
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269 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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270 #define HAL_ICACHE_INVALIDATE_ALL() \
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271 { \
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272 register CYG_ADDRESS _baddr_ = 0x80000000; \
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273 register CYG_ADDRESS _addr_ = 0x80000000; \
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274 register CYG_WORD _state_; \
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275 HAL_ICACHE_IS_ENABLED(_state_); \
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276 HAL_ICACHE_DISABLE(); \
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277 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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278 { \
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279 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
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280 } \
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281 if( _state_ ) HAL_ICACHE_ENABLE(); \
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282 }
6
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283
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284 // Invalidate cache lines in the given range without writing to memory.
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285 // This uses the index-invalidate cache operation since the TX39 does not
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286 // have hit-invalidate on the instruction cache.
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287 #define HAL_ICACHE_INVALIDATE_DEFINED
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288 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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289 { \
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290 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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291 register CYG_WORD _size_ = (_asize_); \
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292 register CYG_WORD _state_; \
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293 HAL_ICACHE_IS_ENABLED(_state_); \
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294 HAL_ICACHE_DISABLE(); \
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295 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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296 { \
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297 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
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298 } \
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299 if( _state_ ) HAL_ICACHE_ENABLE(); \
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300 }
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301
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302 #endif // CYGPKG_HAL_MIPS_TX3904
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303
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304 //-----------------------------------------------------------------------------
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305 #endif // ifndef CYGONCE_IMP_CACHE_H
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306 // End of imp_cache.h