Mercurial > ecos
changeset 1800:022b1537390b
* include/plf_io.h: removed SPI definitions. They are defined in
the variant HAL.
| author | asl |
|---|---|
| date | Wed, 06 Oct 2004 08:21:57 +0000 |
| parents | 5ecf352a5b70 |
| children | 73eed70a0752 |
| files | packages/hal/arm/at91/jtst/current/ChangeLog packages/hal/arm/at91/jtst/current/include/plf_io.h |
| diffstat | 2 files changed, 5 insertions(+), 46 deletions(-) [+] |
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--- a/packages/hal/arm/at91/jtst/current/ChangeLog +++ b/packages/hal/arm/at91/jtst/current/ChangeLog @@ -1,3 +1,8 @@ +2004-10-6 Andrea Michelotti <amichelotti@atmel.com> + + * include/plf_io.h: removed SPI definitions. They are defined in + the variant HAL. + 2004-10-4 Andrea Michelotti <amichelotti@atmel.com> * include/hal_platform_setup.h: added generation of three
--- a/packages/hal/arm/at91/jtst/current/include/plf_io.h +++ b/packages/hal/arm/at91/jtst/current/include/plf_io.h @@ -98,52 +98,6 @@ #define AT91_PDC_PTCR_RXDIS 0x2 -// SPI interface -#define AT91_SPI_CR 0x0 // control register -#define AT91_SPI_CR_DIS 0x2 // disable SP -#define AT91_SPI_CR_EN 0x1 // enable SPI -#define AT91_SPI_CR_RST 0x80 // SW reset SPI -#define AT91_SPI_MR 0x4 // mode register -#define AT91_SPI_RDR 0x8 // receive data register -#define AT91_SPI_TDR 0x8 // trasmit data register -#define AT91_SPI_SR 0x10 // status register -#define AT91_SPI_IER 0x14 // interrupt register -#define AT91_SPI_IDR 0x18 // interrupt disable register -#define AT91_SPI_IMR 0x1C // interrupt mask register -#define AT91_SPI_CSR0 0x30 // chip select 0 -#define AT91_SPI_CSR1 0x34 // chip select 1 -#define AT91_SPI_CSR2 0x38 // chip select 2 -#define AT91_SPI_CSR3 0x3C // chip select 3 -// interrupts mask -#define AT91_SPI_INT_RDRF 0x1 -#define AT91_SPI_INT_TDRE 0x2 -#define AT91_SPI_INT_MODF 0x4 -#define AT91_SPI_INT_OVRE 0x8 -#define AT91_SPI_INT_ENDRX 0x10 -#define AT91_SPI_INT_ENDTX 0x20 -#define AT91_SPI_INT_RXBUFF 0x40 -#define AT91_SPI_INT_TXBUFF 0x80 - -// -#define AT91_SPI_BIT_WIDTH_8 0x0 -#define AT91_SPI_BIT_WIDTH_9 0x1 -#define AT91_SPI_BIT_WIDTH_10 0x2 -#define AT91_SPI_BIT_WIDTH_11 0x3 -#define AT91_SPI_BIT_WIDTH_12 0x4 -#define AT91_SPI_BIT_WIDTH_13 0x5 -#define AT91_SPI_BIT_WIDTH_14 0x6 -#define AT91_SPI_BIT_WIDTH_15 0x7 -#define AT91_SPI_BIT_WIDTH_16 0x8 - -#define AT91_SPI_DATA_CHANGE_HILO 0 -#define AT91_SPI_DATA_CHANGE_LOHI 1 - - -#define AT91_SPI_CLK_PHASE_HI 0 -#define AT91_SPI_CLK_PHASE_LOW 1 - - - // CLOCK divider interface #define AT91_CLKGEN_CPTMAX0 0x0 //counter 0