Mercurial > ecos

changeset 1179:028ac74b016c

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Use new PHY support
author gthomas
date Tue, 26 Aug 2003 17:54:09 +0000
parents 0832585993c1
children f30dbfbd254c
files packages/devs/eth/powerpc/fcc/current/ChangeLog packages/devs/eth/powerpc/fcc/current/src/if_fcc.c packages/devs/eth/powerpc/rattler/current/ChangeLog packages/devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl packages/devs/eth/powerpc/rattler/current/include/rattler_eth.inl
diffstat 5 files changed, 65 insertions(+), 45 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/eth/powerpc/fcc/current/ChangeLog
+++ b/packages/devs/eth/powerpc/fcc/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-08-26  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_fcc.c: Use new PHY support.
+
 2003-08-19  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/if_fcc.c: 
--- a/packages/devs/eth/powerpc/fcc/current/src/if_fcc.c
+++ b/packages/devs/eth/powerpc/fcc/current/src/if_fcc.c
@@ -158,6 +158,9 @@ fcc_eth_init(struct cyg_netdevtab_entry 
     // The FCC seems rather picky about these...
     static long rxbd_base = 0x3000;
     static long txbd_base = 0xB000;
+#ifdef CYGPKG_DEVS_ETH_PHY
+    unsigned short phy_state = 0;
+#endif
 
     // Set up pointers to FCC controller
     switch (qi->int_vector) {
@@ -306,49 +309,34 @@ fcc_eth_init(struct cyg_netdevtab_entry 
         CPCR_FLG;              /* ISSUE COMMAND */
     while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); 
 
+    // Operating mode
+    if (!_eth_phy_init(qi->phy)) {
+        return false;
+    }
 #ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
-    {
-        unsigned short phy_state;
-        unsigned short reset_mode;
-        int phy_unit = 0;
-        int phy_ok;
-        int phy_timeout = 5*100;
-
-        // Reset PHY (transceiver)
-        _eth_phy_init(qi->phy);
+    if (!_eth_phy_reset(qi->phy)) {
+        return false;
+    }
+#endif
+    phy_state = _eth_phy_state(qi->phy);
+    os_printf("FCC ETH: ");
+    if ((phy_state & ETH_PHY_STAT_LINK) != 0) {
+        if ((phy_state & ETH_PHY_STAT_100MB) != 0) {
+            // Link can handle 100Mb
+            os_printf("100Mb");
+            if ((phy_state & ETH_PHY_STAT_FDX) != 0) {
+                os_printf("/Full Duplex");
+            } 
+        } else {
+            // Assume 10Mb, half duplex
+            os_printf("10Mb");
+        }
+    } else {
+        os_printf("/***NO LINK***");
+        return false;
+    }
+    os_printf("\n");
 
-        if (_eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state)) {
-            if ((phy_state & PHY_BMSR_LINK) !=  PHY_BMSR_LINK) {
-                _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, PHY_BMCR_RESET);
-                for (i = 0;  i < 10;  i++) {
-                    phy_ok = _eth_phy_read(qi->phy, PHY_BMCR, phy_unit, &phy_state);
-                    if (!phy_ok) break;
-                    if (!(phy_state & PHY_BMCR_RESET)) break;
-                }
-                if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
-                    diag_printf("%s: Can't get PHY unit to soft reset: %x\n", dtp->name, phy_state);
-                    return false;
-                }
-                reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
-                _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, reset_mode);
-                while (phy_timeout-- >= 0) {
-                    phy_ok = _eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state);
-                    if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
-                        break;
-                    } else {
-                        CYGACC_CALL_IF_DELAY_US(10000);   // 10ms
-                    }
-                }
-                if (phy_timeout <= 0) {
-                    diag_printf("** %s Warning: PHY LINK UP failed\n", dtp->name);
-                }
-            }
-            else {
-                diag_printf("** %s Info: PHY LINK already UP \n", dtp->name);
-            }
-        }
-    }
-#endif // CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
 
     // Initialize upper level driver for ecos
     (sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
--- a/packages/devs/eth/powerpc/rattler/current/ChangeLog
+++ b/packages/devs/eth/powerpc/rattler/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-26  Gary Thomas  <gary@mlbassoc.com>
+
+	* include/rattler_eth.inl: 
+	* cdl/rattler_eth_drivers.cdl: Update PHY support, using AMD AM79C874.
+
 2003-08-19  Gary Thomas  <gary@mlbassoc.com>
 
 	* include/rattler_eth.inl: 
--- a/packages/devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
+++ b/packages/devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
@@ -61,6 +61,7 @@ cdl_package CYGPKG_DEVS_ETH_POWERPC_RATT
 
     requires      CYGPKG_DEVS_ETH_POWERPC_FCC
     requires      CYGPKG_HAL_POWERPC_RATTLER
+    requires      CYGHWR_DEVS_ETH_PHY_AM79C874
 
     cdl_option CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1 {
         display       "Include fcc1/eth0 ethernet device"
--- a/packages/devs/eth/powerpc/rattler/current/include/rattler_eth.inl
+++ b/packages/devs/eth/powerpc/rattler/current/include/rattler_eth.inl
@@ -71,9 +71,19 @@ static void
 fcc1_phy_init(void)
 {
     // Set up PHY reset line
+    IMM->io_regs[PORT_B].pdat |= FCC1_PHY_RESET;
+    IMM->io_regs[PORT_C].pdir |= FCC1_PHY_CLOCK;
+}
+
+//
+// Reset the PHY associated with FCC1/eth0
+//
+static void 
+fcc1_phy_reset(void)
+{
+    // Toggle PHY reset line
     IMM->io_regs[PORT_B].pdat &= ~FCC1_PHY_RESET;
     IMM->io_regs[PORT_B].pdat |= FCC1_PHY_RESET;
-    IMM->io_regs[PORT_C].pdir |= FCC1_PHY_CLOCK;
 }
 
 //
@@ -135,8 +145,9 @@ fcc1_phy_set_dir(int data_dir)
     }
 }
 
-ETH_PHY_ACCESS_FUNS(fcc1_phy,
+ETH_PHY_BIT_LEVEL_ACCESS_FUNS(fcc1_phy,
                     fcc1_phy_init,
+                    fcc1_phy_reset,
                     fcc1_phy_set_data,
                     fcc1_phy_get_data,
                     fcc1_phy_set_clock,
@@ -193,9 +204,19 @@ static void
 fcc2_phy_init(void)
 {
     // Set up PHY reset line
+    IMM->io_regs[PORT_B].pdat |= FCC2_PHY_RESET;
+    IMM->io_regs[PORT_C].pdir |= FCC2_PHY_CLOCK;
+}
+
+//
+// Reset the PHY associated with FCC2/eth1
+//
+static void 
+fcc2_phy_reset(void)
+{
+    // Toggle the PHY reset line
     IMM->io_regs[PORT_B].pdat &= ~FCC2_PHY_RESET;
     IMM->io_regs[PORT_B].pdat |= FCC2_PHY_RESET;
-    IMM->io_regs[PORT_C].pdir |= FCC2_PHY_CLOCK;
 }
 
 //
@@ -257,8 +278,9 @@ fcc2_phy_set_dir(int data_dir)
     }
 }
 
-ETH_PHY_ACCESS_FUNS(fcc2_phy,
+ETH_PHY_BIT_LEVEL_ACCESS_FUNS(fcc2_phy,
                     fcc2_phy_init,
+                    fcc2_phy_reset,
                     fcc2_phy_set_data,
                     fcc2_phy_get_data,
                     fcc2_phy_set_clock,