Mercurial > ecos
changeset 2785:07e89f5d0ee3
* src/spi_stm32.c:
* cdl/spi_stm32.cdl:
Add option to automatically disable JTAG port when initialising SPI3.
| author | nickg |
|---|---|
| date | Tue, 10 Feb 2009 16:12:53 +0000 |
| parents | 70c6da0cc793 |
| children | 856d1552c172 |
| files | packages/devs/spi/cortexm/stm32/current/ChangeLog packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c |
| diffstat | 3 files changed, 30 insertions(+), 1 deletions(-) [+] |
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--- a/packages/devs/spi/cortexm/stm32/current/ChangeLog +++ b/packages/devs/spi/cortexm/stm32/current/ChangeLog @@ -1,3 +1,9 @@ +2009-02-10 Chris Holgate <chris@zynaptic.com> + + * src/spi_stm32.c: + * cdl/spi_stm32.cdl: + Add option to automatically disable JTAG port when initialising SPI3. + 2009-02-10 Nick Garnett <nickg@ecoscentric.com> * src/spi_stm32.c (bus3_setup): Fix typo.
--- a/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl +++ b/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl @@ -165,11 +165,24 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 { display "ST STM32 SPI bus 3" description " - Enable SPI bus 3 on the STM32 device. + Enable SPI bus 3 on the STM32 device. Note that SPI bus 3 shares pins + with the JTAG port which means that debug should ideally be disabled + on startup. However, there is also the option of disabling it during + SPI bus initialisation instead. " flavor bool default_value false + cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT { + display "Disable debug port" + description " + When set the debug port will automatically be disabled on + initialising SPI bus 3, freeing up the SPI interface pins. + " + flavor bool + default_value false + } + cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS { display "SPI chip selects" description "
--- a/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c +++ b/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c @@ -614,6 +614,16 @@ static void spi_transaction_dma void cyg_spi_cortexm_stm32_init (void) { +#if defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && \ + defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT) + // Disable debug port, freeing up SPI bus 3 pins. + cyg_uint32 reg_val; + HAL_READ_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val); + reg_val &= ~((cyg_uint32) CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK); + reg_val |= CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS; + HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val); +#endif + #ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 stm32_spi_bus_setup (&cyg_spi_stm32_bus1); #endif